Lines Matching +full:mac +full:- +full:s
1 // SPDX-License-Identifier: GPL-2.0-only
14 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
40 * t1_wait_op_done - wait until an operation is completed
43 * @mask: a single-bit field within @reg that indicates completion
56 u32 val = readl(adapter->regs + reg) & mask; in t1_wait_op_done()
60 if (--attempts == 0) in t1_wait_op_done()
76 writel(addr, adapter->regs + A_TPI_ADDR); in __t1_tpi_write()
77 writel(value, adapter->regs + A_TPI_WR_DATA); in __t1_tpi_write()
78 writel(F_TPIWR, adapter->regs + A_TPI_CSR); in __t1_tpi_write()
83 pr_alert("%s: TPI write to 0x%x failed\n", in __t1_tpi_write()
84 adapter->name, addr); in __t1_tpi_write()
92 spin_lock(&adapter->tpi_lock); in t1_tpi_write()
94 spin_unlock(&adapter->tpi_lock); in t1_tpi_write()
105 writel(addr, adapter->regs + A_TPI_ADDR); in __t1_tpi_read()
106 writel(0, adapter->regs + A_TPI_CSR); in __t1_tpi_read()
111 pr_alert("%s: TPI read from 0x%x failed\n", in __t1_tpi_read()
112 adapter->name, addr); in __t1_tpi_read()
114 *valp = readl(adapter->regs + A_TPI_RD_DATA); in __t1_tpi_read()
122 spin_lock(&adapter->tpi_lock); in t1_tpi_read()
124 spin_unlock(&adapter->tpi_lock); in t1_tpi_read()
133 writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR); in t1_tpi_par()
137 * Called when a port's link settings change to propagate the new values to the
138 * associated PHY and MAC. After performing the common tasks it invokes an
139 * OS-specific handler.
144 struct cphy *phy = adapter->port[port_id].phy; in t1_link_changed()
145 struct link_config *lc = &adapter->port[port_id].link_config; in t1_link_changed()
147 phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc); in t1_link_changed()
149 lc->speed = speed < 0 ? SPEED_INVALID : speed; in t1_link_changed()
150 lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex; in t1_link_changed()
151 if (!(lc->requested_fc & PAUSE_AUTONEG)) in t1_link_changed()
152 fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); in t1_link_changed()
154 if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) { in t1_link_changed()
155 /* Set MAC speed, duplex, and flow control to match PHY. */ in t1_link_changed()
156 struct cmac *mac = adapter->port[port_id].mac; in t1_link_changed() local
158 mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc); in t1_link_changed()
159 lc->fc = (unsigned char)fc; in t1_link_changed()
168 pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause); in t1_pci_intr_handler()
171 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, in t1_pci_intr_handler()
175 adapter->pending_thread_intr |= F_PL_INTR_SGE_ERR; in t1_pci_intr_handler()
176 pr_alert("%s: PCI error encountered.\n", adapter->name); in t1_pci_intr_handler()
191 u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE); in fpga_phy_intr_handler()
195 struct cphy *phy = adapter->port[p].phy; in fpga_phy_intr_handler()
196 int phy_cause = phy->ops->interrupt_handler(phy); in fpga_phy_intr_handler()
201 writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE); in fpga_phy_intr_handler()
210 u32 cause = readl(adapter->regs + A_PL_CAUSE); in fpga_slow_intr()
215 if (t1_sge_intr_error_handler(adapter->sge)) in fpga_slow_intr()
227 u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE); in fpga_slow_intr()
230 writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE); in fpga_slow_intr()
239 writel(cause, adapter->regs + A_PL_CAUSE); in fpga_slow_intr()
249 * Wait until Elmer's MI1 interface is ready for new operations.
262 } while (busy && --attempts); in mi1_wait_until_ready()
264 pr_alert("%s: MDIO operation timed out\n", adapter->name); in mi1_wait_until_ready()
273 u32 clkdiv = bi->clock_elmer0 / (2 * bi->mdio_mdc) - 1; in mi1_mdio_init()
274 u32 val = F_MI1_PREAMBLE_ENABLE | V_MI1_MDI_INVERT(bi->mdio_mdiinv) | in mi1_mdio_init()
275 V_MI1_MDI_ENABLE(bi->mdio_mdien) | V_MI1_CLK_DIV(clkdiv); in mi1_mdio_init()
277 if (!(bi->caps & SUPPORTED_10000baseT_Full)) in mi1_mdio_init()
289 struct adapter *adapter = dev->ml_priv; in mi1_mdio_read()
293 spin_lock(&adapter->tpi_lock); in mi1_mdio_read()
299 spin_unlock(&adapter->tpi_lock); in mi1_mdio_read()
306 struct adapter *adapter = dev->ml_priv; in mi1_mdio_write()
309 spin_lock(&adapter->tpi_lock); in mi1_mdio_write()
315 spin_unlock(&adapter->tpi_lock); in mi1_mdio_write()
331 struct adapter *adapter = dev->ml_priv; in mi1_mdio_ext_read()
335 spin_lock(&adapter->tpi_lock); in mi1_mdio_ext_read()
351 spin_unlock(&adapter->tpi_lock); in mi1_mdio_ext_read()
358 struct adapter *adapter = dev->ml_priv; in mi1_mdio_ext_write()
361 spin_lock(&adapter->tpi_lock); in mi1_mdio_ext_write()
374 spin_unlock(&adapter->tpi_lock); in mi1_mdio_ext_write()
414 .desc = "Chelsio T110 1x10GBase-CX4 TOE",
498 .desc = "Chelsio T210 1x10GBase-CX4 TOE",
542 * Return the board_info structure with a given index. Out-of-range indices
554 u8 pad[2]; /* make multiple-of-4 size requirement explicit */
572 return -EINVAL; in t1_seeprom_read()
574 pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr); in t1_seeprom_read()
577 pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val); in t1_seeprom_read()
578 } while (!(val & F_VPD_OP_FLAG) && --i); in t1_seeprom_read()
581 pr_err("%s: reading EEPROM address 0x%x failed\n", in t1_seeprom_read()
582 adapter->name, addr); in t1_seeprom_read()
583 return -EIO; in t1_seeprom_read()
585 pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, &v); in t1_seeprom_read()
602 * Read a port's MAC address from the VPD ROM.
616 * Set up the MAC/PHY according to the requested link settings.
618 * If the PHY can auto-negotiate first decide what to advertise, then
619 * enable/disable auto-negotiation as desired and reset.
621 * If the PHY does not auto-negotiate we just reset it.
623 * If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
624 * otherwise do it later based on the outcome of auto-negotiation.
626 int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc) in t1_link_start() argument
628 unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); in t1_link_start()
630 if (lc->supported & SUPPORTED_Autoneg) { in t1_link_start()
631 lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE); in t1_link_start()
634 (mac->adapter->params.nports < 2))) in t1_link_start()
635 lc->advertising |= ADVERTISED_PAUSE; in t1_link_start()
637 lc->advertising |= ADVERTISED_ASYM_PAUSE; in t1_link_start()
639 lc->advertising |= ADVERTISED_PAUSE; in t1_link_start()
642 phy->ops->advertise(phy, lc->advertising); in t1_link_start()
644 if (lc->autoneg == AUTONEG_DISABLE) { in t1_link_start()
645 lc->speed = lc->requested_speed; in t1_link_start()
646 lc->duplex = lc->requested_duplex; in t1_link_start()
647 lc->fc = (unsigned char)fc; in t1_link_start()
648 mac->ops->set_speed_duplex_fc(mac, lc->speed, in t1_link_start()
649 lc->duplex, fc); in t1_link_start()
651 phy->state = PHY_AUTONEG_RDY; in t1_link_start()
652 phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex); in t1_link_start()
653 phy->ops->reset(phy, 0); in t1_link_start()
655 phy->state = PHY_AUTONEG_EN; in t1_link_start()
656 phy->ops->autoneg_enable(phy); /* also resets PHY */ in t1_link_start()
659 phy->state = PHY_AUTONEG_RDY; in t1_link_start()
660 mac->ops->set_speed_duplex_fc(mac, -1, -1, fc); in t1_link_start()
661 lc->fc = (unsigned char)fc; in t1_link_start()
662 phy->ops->reset(phy, 0); in t1_link_start()
678 switch (board_info(adapter)->board) { in t1_elmer0_ext_intr_handler()
690 phy = adapter->port[i].phy; in t1_elmer0_ext_intr_handler()
691 phy_cause = phy->ops->interrupt_handler(phy); in t1_elmer0_ext_intr_handler()
699 phy = adapter->port[0].phy; in t1_elmer0_ext_intr_handler()
700 phy_cause = phy->ops->interrupt_handler(phy); in t1_elmer0_ext_intr_handler()
708 * Elmer0's interrupt cause isn't useful here because there is in t1_elmer0_ext_intr_handler()
710 * we are forced to check every PHY's interrupt status in t1_elmer0_ext_intr_handler()
714 phy = adapter->port[p].phy; in t1_elmer0_ext_intr_handler()
715 phy_cause = phy->ops->interrupt_handler(phy); in t1_elmer0_ext_intr_handler()
726 phy = adapter->port[0].phy; in t1_elmer0_ext_intr_handler()
727 phy_cause = phy->ops->interrupt_handler(phy); in t1_elmer0_ext_intr_handler()
735 dev_dbg(&adapter->pdev->dev, in t1_elmer0_ext_intr_handler()
738 struct cmac *mac = adapter->port[0].mac; in t1_elmer0_ext_intr_handler() local
740 mac->ops->interrupt_handler(mac); in t1_elmer0_ext_intr_handler()
748 dev_info(&adapter->pdev->dev, "XPAK %s\n", in t1_elmer0_ext_intr_handler()
762 adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP; in t1_interrupts_enable()
764 t1_sge_intr_enable(adapter->sge); in t1_interrupts_enable()
765 t1_tp_intr_enable(adapter->tp); in t1_interrupts_enable()
766 if (adapter->espi) { in t1_interrupts_enable()
767 adapter->slow_intr_mask |= F_PL_INTR_ESPI; in t1_interrupts_enable()
768 t1_espi_intr_enable(adapter->espi); in t1_interrupts_enable()
771 /* Enable MAC/PHY interrupts for each port. */ in t1_interrupts_enable()
773 adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac); in t1_interrupts_enable()
774 adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy); in t1_interrupts_enable()
779 u32 pl_intr = readl(adapter->regs + A_PL_ENABLE); in t1_interrupts_enable()
781 /* PCI-X interrupts */ in t1_interrupts_enable()
782 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, in t1_interrupts_enable()
785 adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX; in t1_interrupts_enable()
787 writel(pl_intr, adapter->regs + A_PL_ENABLE); in t1_interrupts_enable()
796 t1_sge_intr_disable(adapter->sge); in t1_interrupts_disable()
797 t1_tp_intr_disable(adapter->tp); in t1_interrupts_disable()
798 if (adapter->espi) in t1_interrupts_disable()
799 t1_espi_intr_disable(adapter->espi); in t1_interrupts_disable()
801 /* Disable MAC/PHY interrupts for each port. */ in t1_interrupts_disable()
803 adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac); in t1_interrupts_disable()
804 adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy); in t1_interrupts_disable()
809 writel(0, adapter->regs + A_PL_ENABLE); in t1_interrupts_disable()
811 /* PCI-X interrupts */ in t1_interrupts_disable()
812 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0); in t1_interrupts_disable()
814 adapter->slow_intr_mask = 0; in t1_interrupts_disable()
822 t1_sge_intr_clear(adapter->sge); in t1_interrupts_clear()
823 t1_tp_intr_clear(adapter->tp); in t1_interrupts_clear()
824 if (adapter->espi) in t1_interrupts_clear()
825 t1_espi_intr_clear(adapter->espi); in t1_interrupts_clear()
827 /* Clear MAC/PHY interrupts for each port. */ in t1_interrupts_clear()
829 adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac); in t1_interrupts_clear()
830 adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy); in t1_interrupts_clear()
835 u32 pl_intr = readl(adapter->regs + A_PL_CAUSE); in t1_interrupts_clear()
838 adapter->regs + A_PL_CAUSE); in t1_interrupts_clear()
841 /* PCI-X interrupts */ in t1_interrupts_clear()
842 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff); in t1_interrupts_clear()
850 u32 cause = readl(adapter->regs + A_PL_CAUSE); in asic_slow_intr()
853 cause &= adapter->slow_intr_mask; in asic_slow_intr()
857 if (t1_sge_intr_error_handler(adapter->sge)) in asic_slow_intr()
861 t1_tp_intr_handler(adapter->tp); in asic_slow_intr()
863 t1_espi_intr_handler(adapter->espi); in asic_slow_intr()
871 * the interim and let the thread reenable them when it's done. in asic_slow_intr()
873 adapter->pending_thread_intr |= F_PL_INTR_EXT; in asic_slow_intr()
874 adapter->slow_intr_mask &= ~F_PL_INTR_EXT; in asic_slow_intr()
875 writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA, in asic_slow_intr()
876 adapter->regs + A_PL_ENABLE); in asic_slow_intr()
881 writel(cause, adapter->regs + A_PL_CAUSE); in asic_slow_intr()
882 readl(adapter->regs + A_PL_CAUSE); /* flush writes */ in asic_slow_intr()
895 /* Power sequencing is a work-around for Intel's XPAKs. */
914 p->chip_version = bi->chip_term; in t1_get_board_rev()
915 p->is_asic = (p->chip_version != CHBT_TERM_FPGA); in t1_get_board_rev()
916 if (p->chip_version == CHBT_TERM_T1 || in t1_get_board_rev()
917 p->chip_version == CHBT_TERM_T2 || in t1_get_board_rev()
918 p->chip_version == CHBT_TERM_FPGA) { in t1_get_board_rev()
919 u32 val = readl(adapter->regs + A_TP_PC_CONFIG); in t1_get_board_rev()
923 p->chip_revision = TERM_T1B; in t1_get_board_rev()
925 p->chip_revision = TERM_T2; in t1_get_board_rev()
927 return -1; in t1_get_board_rev()
929 return -1; in t1_get_board_rev()
934 * Enable board components other than the Chelsio chip, such as external MAC
939 switch (bi->board) { in board_init()
977 * MAC and PHYs are initialized separately.
981 int err = -EIO; in t1_init_hw_modules()
984 if (!bi->clock_mc4) { in t1_init_hw_modules()
985 u32 val = readl(adapter->regs + A_MC4_CFG); in t1_init_hw_modules()
987 writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG); in t1_init_hw_modules()
989 adapter->regs + A_MC5_CONFIG); in t1_init_hw_modules()
992 if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac, in t1_init_hw_modules()
993 bi->espi_nports)) in t1_init_hw_modules()
996 if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core)) in t1_init_hw_modules()
999 err = t1_sge_configure(adapter->sge, &adapter->params.sge); in t1_init_hw_modules()
1009 * Determine a card's PCI mode.
1016 pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode); in get_pci_mode()
1017 p->speed = speed_map[G_PCI_MODE_CLK(pci_mode)]; in get_pci_mode()
1018 p->width = (pci_mode & F_PCI_MODE_64BIT) ? 64 : 32; in get_pci_mode()
1019 p->is_pcix = (pci_mode & F_PCI_MODE_PCIX) != 0; in get_pci_mode()
1023 * Release the structures holding the SW per-Terminator-HW-module state.
1030 struct cmac *mac = adapter->port[i].mac; in t1_free_sw_modules() local
1031 struct cphy *phy = adapter->port[i].phy; in t1_free_sw_modules()
1033 if (mac) in t1_free_sw_modules()
1034 mac->ops->destroy(mac); in t1_free_sw_modules()
1036 phy->ops->destroy(phy); in t1_free_sw_modules()
1039 if (adapter->sge) in t1_free_sw_modules()
1040 t1_sge_destroy(adapter->sge); in t1_free_sw_modules()
1041 if (adapter->tp) in t1_free_sw_modules()
1042 t1_tp_destroy(adapter->tp); in t1_free_sw_modules()
1043 if (adapter->espi) in t1_free_sw_modules()
1044 t1_espi_destroy(adapter->espi); in t1_free_sw_modules()
1050 lc->supported = bi->caps; in init_link_config()
1051 lc->requested_speed = lc->speed = SPEED_INVALID; in init_link_config()
1052 lc->requested_duplex = lc->duplex = DUPLEX_INVALID; in init_link_config()
1053 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX; in init_link_config()
1054 if (lc->supported & SUPPORTED_Autoneg) { in init_link_config()
1055 lc->advertising = lc->supported; in init_link_config()
1056 lc->autoneg = AUTONEG_ENABLE; in init_link_config()
1057 lc->requested_fc |= PAUSE_AUTONEG; in init_link_config()
1059 lc->advertising = 0; in init_link_config()
1060 lc->autoneg = AUTONEG_DISABLE; in init_link_config()
1072 adapter->params.brd_info = bi; in t1_init_sw_modules()
1073 adapter->params.nports = bi->port_number; in t1_init_sw_modules()
1074 adapter->params.stats_update_period = bi->gmac->stats_update_period; in t1_init_sw_modules()
1076 adapter->sge = t1_sge_create(adapter, &adapter->params.sge); in t1_init_sw_modules()
1077 if (!adapter->sge) { in t1_init_sw_modules()
1078 pr_err("%s: SGE initialization failed\n", in t1_init_sw_modules()
1079 adapter->name); in t1_init_sw_modules()
1083 if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) { in t1_init_sw_modules()
1084 pr_err("%s: ESPI initialization failed\n", in t1_init_sw_modules()
1085 adapter->name); in t1_init_sw_modules()
1089 adapter->tp = t1_tp_create(adapter, &adapter->params.tp); in t1_init_sw_modules()
1090 if (!adapter->tp) { in t1_init_sw_modules()
1091 pr_err("%s: TP initialization failed\n", in t1_init_sw_modules()
1092 adapter->name); in t1_init_sw_modules()
1097 bi->mdio_ops->init(adapter, bi); in t1_init_sw_modules()
1098 if (bi->gphy->reset) in t1_init_sw_modules()
1099 bi->gphy->reset(adapter); in t1_init_sw_modules()
1100 if (bi->gmac->reset) in t1_init_sw_modules()
1101 bi->gmac->reset(adapter); in t1_init_sw_modules()
1105 struct cmac *mac; in t1_init_sw_modules() local
1106 int phy_addr = bi->mdio_phybaseaddr + i; in t1_init_sw_modules()
1108 adapter->port[i].phy = bi->gphy->create(adapter->port[i].dev, in t1_init_sw_modules()
1109 phy_addr, bi->mdio_ops); in t1_init_sw_modules()
1110 if (!adapter->port[i].phy) { in t1_init_sw_modules()
1111 pr_err("%s: PHY %d initialization failed\n", in t1_init_sw_modules()
1112 adapter->name, i); in t1_init_sw_modules()
1116 adapter->port[i].mac = mac = bi->gmac->create(adapter, i); in t1_init_sw_modules()
1117 if (!mac) { in t1_init_sw_modules()
1118 pr_err("%s: MAC %d initialization failed\n", in t1_init_sw_modules()
1119 adapter->name, i); in t1_init_sw_modules()
1124 * Get the port's MAC addresses either from the EEPROM if one in t1_init_sw_modules()
1125 * exists or the one hardcoded in the MAC. in t1_init_sw_modules()
1127 if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY) in t1_init_sw_modules()
1128 mac->ops->macaddress_get(mac, hw_addr); in t1_init_sw_modules()
1130 pr_err("%s: could not read MAC address from VPD ROM\n", in t1_init_sw_modules()
1131 adapter->port[i].dev->name); in t1_init_sw_modules()
1134 eth_hw_addr_set(adapter->port[i].dev, hw_addr); in t1_init_sw_modules()
1135 init_link_config(&adapter->port[i].link_config, bi); in t1_init_sw_modules()
1138 get_pci_mode(adapter, &adapter->params.pci); in t1_init_sw_modules()
1144 return -1; in t1_init_sw_modules()