Lines Matching +full:tx +full:- +full:port +full:- +full:mapping
1 // SPDX-License-Identifier: GPL-2.0-only
14 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
71 * Period of the TX buffer reclaim timer. This timer does not need to run
72 * frequently as TX buffers are usually reclaimed by new TX packets.
170 unsigned int in_use; /* # of in-use command descriptors */
174 unsigned int stop_thres; /* SW TX queue suspend threshold */
214 /* T204 TX SW scheduler */
216 /* Per T204 TX port */
218 unsigned int avail; /* available bits - quota */
228 unsigned int max_avail; /* max bits to be sent to any port */
229 unsigned int port; /* port index (round robin ports) */ member
230 unsigned int num; /* num skbs in per port queues */
244 * separate the RX(in irq context) and TX state in order to decrease memory
252 unsigned long stopped_tx_queues; /* bitmap of suspended Tx queues */
255 unsigned int intrtimer_nres; /* no-resource interrupt timer */
256 unsigned int fixed_intrtimer;/* non-adaptive interrupt timer */
257 struct timer_list tx_reclaim_timer; /* reclaims TX buffers */
277 struct sched *s = sge->tx_sched; in tx_sched_stop()
280 tasklet_kill(&s->sched_tsk); in tx_sched_stop()
283 __skb_queue_purge(&s->p[s->port].skbq); in tx_sched_stop()
288 * re-computes scheduler parameters to scope with the change.
290 unsigned int t1_sched_update_parms(struct sge *sge, unsigned int port, in t1_sched_update_parms() argument
293 struct sched *s = sge->tx_sched; in t1_sched_update_parms()
294 struct sched_port *p = &s->p[port]; in t1_sched_update_parms()
299 p->speed = speed; in t1_sched_update_parms()
301 p->mtu = mtu; in t1_sched_update_parms()
304 unsigned long long drain = 1024ULL * p->speed * (p->mtu - 40); in t1_sched_update_parms()
305 do_div(drain, (p->mtu + 50) * 1000); in t1_sched_update_parms()
306 p->drain_bits_per_1024ns = (unsigned int) drain; in t1_sched_update_parms()
308 if (p->speed < 1000) in t1_sched_update_parms()
309 p->drain_bits_per_1024ns = in t1_sched_update_parms()
310 90 * p->drain_bits_per_1024ns / 100; in t1_sched_update_parms()
313 if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) { in t1_sched_update_parms()
314 p->drain_bits_per_1024ns -= 16; in t1_sched_update_parms()
315 s->max_avail = max(4096U, p->mtu + 16 + 14 + 4); in t1_sched_update_parms()
316 max_avail_segs = max(1U, 4096 / (p->mtu - 40)); in t1_sched_update_parms()
318 s->max_avail = 16384; in t1_sched_update_parms()
319 max_avail_segs = max(1U, 9000 / (p->mtu - 40)); in t1_sched_update_parms()
323 "max_avail_segs %u drain_bits_per_1024ns %u\n", p->mtu, in t1_sched_update_parms()
324 p->speed, s->max_avail, max_avail_segs, in t1_sched_update_parms()
325 p->drain_bits_per_1024ns); in t1_sched_update_parms()
327 return max_avail_segs * (p->mtu - 40); in t1_sched_update_parms()
334 * data that can be pushed per port.
338 struct sched *s = sge->tx_sched;
341 s->max_avail = val;
347 * t1_sched_set_drain_bits_per_us() tells the scheduler at which rate a port
350 void t1_sched_set_drain_bits_per_us(struct sge *sge, unsigned int port,
353 struct sched *s = sge->tx_sched;
354 struct sched_port *p = &s->p[port];
355 p->drain_bits_per_1024ns = val * 1024 / 1000;
356 t1_sched_update_parms(sge, port, 0, 0);
371 return -ENOMEM; in tx_sched_init()
374 tasklet_setup(&s->sched_tsk, restart_sched); in tx_sched_init()
375 s->sge = sge; in tx_sched_init()
376 sge->tx_sched = s; in tx_sched_init()
379 skb_queue_head_init(&s->p[i].skbq); in tx_sched_init()
388 * and updates the per port quota (number of bits that can be sent to the any
389 * port).
393 struct sched *s = sge->tx_sched; in sched_update_avail()
398 delta_time_ns = ktime_to_ns(ktime_sub(now, s->last_updated)); in sched_update_avail()
405 struct sched_port *p = &s->p[i]; in sched_update_avail()
408 delta_avail = (p->drain_bits_per_1024ns * delta_time_ns) >> 13; in sched_update_avail()
409 p->avail = min(p->avail + delta_avail, s->max_avail); in sched_update_avail()
412 s->last_updated = now; in sched_update_avail()
418 * sched_skb() is called from two different places. In the tx path, any
419 * packet generating load on an output port will call sched_skb()
423 * length of the skb is <= the current quota of the output port.
428 struct sched *s = sge->tx_sched; in sched_skb()
434 if (!s->num) in sched_skb()
437 skbq = &s->p[skb->dev->if_port].skbq; in sched_skb()
439 s->num++; in sched_skb()
448 s->port = (s->port + 1) & (MAX_NPORTS - 1); in sched_skb()
449 skbq = &s->p[s->port].skbq; in sched_skb()
456 len = skb->len; in sched_skb()
457 if (len <= s->p[s->port].avail) { in sched_skb()
458 s->p[s->port].avail -= len; in sched_skb()
459 s->num--; in sched_skb()
466 if (update-- && sched_update_avail(sge)) in sched_skb()
473 if (s->num && !skb) { in sched_skb()
474 struct cmdQ *q = &sge->cmdQ[0]; in sched_skb()
475 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); in sched_skb()
476 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { in sched_skb()
477 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); in sched_skb()
478 writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL); in sched_skb()
492 writel(val, adapter->regs + A_SG_DOORBELL); in doorbell_pio()
501 unsigned int cidx = q->cidx; in free_freelQ_buffers()
503 while (q->credits--) { in free_freelQ_buffers()
504 struct freelQ_ce *ce = &q->centries[cidx]; in free_freelQ_buffers()
506 dma_unmap_single(&pdev->dev, dma_unmap_addr(ce, dma_addr), in free_freelQ_buffers()
508 dev_kfree_skb(ce->skb); in free_freelQ_buffers()
509 ce->skb = NULL; in free_freelQ_buffers()
510 if (++cidx == q->size) in free_freelQ_buffers()
520 struct pci_dev *pdev = sge->adapter->pdev; in free_rx_resources()
523 if (sge->respQ.entries) { in free_rx_resources()
524 size = sizeof(struct respQ_e) * sge->respQ.size; in free_rx_resources()
525 dma_free_coherent(&pdev->dev, size, sge->respQ.entries, in free_rx_resources()
526 sge->respQ.dma_addr); in free_rx_resources()
530 struct freelQ *q = &sge->freelQ[i]; in free_rx_resources()
532 if (q->centries) { in free_rx_resources()
534 kfree(q->centries); in free_rx_resources()
536 if (q->entries) { in free_rx_resources()
537 size = sizeof(struct freelQ_e) * q->size; in free_rx_resources()
538 dma_free_coherent(&pdev->dev, size, q->entries, in free_rx_resources()
539 q->dma_addr); in free_rx_resources()
550 struct pci_dev *pdev = sge->adapter->pdev; in alloc_rx_resources()
554 struct freelQ *q = &sge->freelQ[i]; in alloc_rx_resources()
556 q->genbit = 1; in alloc_rx_resources()
557 q->size = p->freelQ_size[i]; in alloc_rx_resources()
558 q->dma_offset = sge->rx_pkt_pad ? 0 : NET_IP_ALIGN; in alloc_rx_resources()
559 size = sizeof(struct freelQ_e) * q->size; in alloc_rx_resources()
560 q->entries = dma_alloc_coherent(&pdev->dev, size, in alloc_rx_resources()
561 &q->dma_addr, GFP_KERNEL); in alloc_rx_resources()
562 if (!q->entries) in alloc_rx_resources()
565 size = sizeof(struct freelQ_ce) * q->size; in alloc_rx_resources()
566 q->centries = kzalloc(size, GFP_KERNEL); in alloc_rx_resources()
567 if (!q->centries) in alloc_rx_resources()
578 sge->freelQ[!sge->jumbo_fl].rx_buffer_size = SGE_RX_SM_BUF_SIZE + in alloc_rx_resources()
580 sge->freelQ[!sge->jumbo_fl].dma_offset; in alloc_rx_resources()
582 size = (16 * 1024) - SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); in alloc_rx_resources()
584 sge->freelQ[sge->jumbo_fl].rx_buffer_size = size; in alloc_rx_resources()
590 sge->freelQ[!sge->jumbo_fl].recycleq_idx = 0; in alloc_rx_resources()
591 sge->freelQ[sge->jumbo_fl].recycleq_idx = 1; in alloc_rx_resources()
593 sge->respQ.genbit = 1; in alloc_rx_resources()
594 sge->respQ.size = SGE_RESPQ_E_N; in alloc_rx_resources()
595 sge->respQ.credits = 0; in alloc_rx_resources()
596 size = sizeof(struct respQ_e) * sge->respQ.size; in alloc_rx_resources()
597 sge->respQ.entries = in alloc_rx_resources()
598 dma_alloc_coherent(&pdev->dev, size, &sge->respQ.dma_addr, in alloc_rx_resources()
600 if (!sge->respQ.entries) in alloc_rx_resources()
606 return -ENOMEM; in alloc_rx_resources()
610 * Reclaims n TX descriptors and frees the buffers associated with them.
615 struct pci_dev *pdev = sge->adapter->pdev; in free_cmdQ_buffers()
616 unsigned int cidx = q->cidx; in free_cmdQ_buffers()
618 q->in_use -= n; in free_cmdQ_buffers()
619 ce = &q->centries[cidx]; in free_cmdQ_buffers()
620 while (n--) { in free_cmdQ_buffers()
622 dma_unmap_single(&pdev->dev, in free_cmdQ_buffers()
626 if (q->sop) in free_cmdQ_buffers()
627 q->sop = 0; in free_cmdQ_buffers()
629 if (ce->skb) { in free_cmdQ_buffers()
630 dev_kfree_skb_any(ce->skb); in free_cmdQ_buffers()
631 q->sop = 1; in free_cmdQ_buffers()
634 if (++cidx == q->size) { in free_cmdQ_buffers()
636 ce = q->centries; in free_cmdQ_buffers()
639 q->cidx = cidx; in free_cmdQ_buffers()
643 * Free TX resources.
649 struct pci_dev *pdev = sge->adapter->pdev; in free_tx_resources()
653 struct cmdQ *q = &sge->cmdQ[i]; in free_tx_resources()
655 if (q->centries) { in free_tx_resources()
656 if (q->in_use) in free_tx_resources()
657 free_cmdQ_buffers(sge, q, q->in_use); in free_tx_resources()
658 kfree(q->centries); in free_tx_resources()
660 if (q->entries) { in free_tx_resources()
661 size = sizeof(struct cmdQ_e) * q->size; in free_tx_resources()
662 dma_free_coherent(&pdev->dev, size, q->entries, in free_tx_resources()
663 q->dma_addr); in free_tx_resources()
669 * Allocates basic TX resources, consisting of memory mapped command Qs.
673 struct pci_dev *pdev = sge->adapter->pdev; in alloc_tx_resources()
677 struct cmdQ *q = &sge->cmdQ[i]; in alloc_tx_resources()
679 q->genbit = 1; in alloc_tx_resources()
680 q->sop = 1; in alloc_tx_resources()
681 q->size = p->cmdQ_size[i]; in alloc_tx_resources()
682 q->in_use = 0; in alloc_tx_resources()
683 q->status = 0; in alloc_tx_resources()
684 q->processed = q->cleaned = 0; in alloc_tx_resources()
685 q->stop_thres = 0; in alloc_tx_resources()
686 spin_lock_init(&q->lock); in alloc_tx_resources()
687 size = sizeof(struct cmdQ_e) * q->size; in alloc_tx_resources()
688 q->entries = dma_alloc_coherent(&pdev->dev, size, in alloc_tx_resources()
689 &q->dma_addr, GFP_KERNEL); in alloc_tx_resources()
690 if (!q->entries) in alloc_tx_resources()
693 size = sizeof(struct cmdQ_ce) * q->size; in alloc_tx_resources()
694 q->centries = kzalloc(size, GFP_KERNEL); in alloc_tx_resources()
695 if (!q->centries) in alloc_tx_resources()
702 * packet from each port, plus reserve an additional 24 entries for in alloc_tx_resources()
706 sge->cmdQ[0].stop_thres = sge->adapter->params.nports * in alloc_tx_resources()
712 return -ENOMEM; in alloc_tx_resources()
719 writel((u32)addr, adapter->regs + base_reg_lo); in setup_ring_params()
720 writel(addr >> 32, adapter->regs + base_reg_hi); in setup_ring_params()
721 writel(size, adapter->regs + size_reg); in setup_ring_params()
729 struct sge *sge = adapter->sge; in t1_vlan_mode()
732 sge->sge_control |= F_VLAN_XTRACT; in t1_vlan_mode()
734 sge->sge_control &= ~F_VLAN_XTRACT; in t1_vlan_mode()
735 if (adapter->open_device_map) { in t1_vlan_mode()
736 writel(sge->sge_control, adapter->regs + A_SG_CONTROL); in t1_vlan_mode()
737 readl(adapter->regs + A_SG_CONTROL); /* flush */ in t1_vlan_mode()
743 * but sge->sge_control is setup and ready to go.
747 struct adapter *ap = sge->adapter; in configure_sge()
749 writel(0, ap->regs + A_SG_CONTROL); in configure_sge()
750 setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].size, in configure_sge()
752 setup_ring_params(ap, sge->cmdQ[1].dma_addr, sge->cmdQ[1].size, in configure_sge()
754 setup_ring_params(ap, sge->freelQ[0].dma_addr, in configure_sge()
755 sge->freelQ[0].size, A_SG_FL0BASELWR, in configure_sge()
757 setup_ring_params(ap, sge->freelQ[1].dma_addr, in configure_sge()
758 sge->freelQ[1].size, A_SG_FL1BASELWR, in configure_sge()
762 writel(SGE_RX_SM_BUF_SIZE + 1, ap->regs + A_SG_FLTHRESHOLD); in configure_sge()
764 setup_ring_params(ap, sge->respQ.dma_addr, sge->respQ.size, in configure_sge()
766 writel((u32)sge->respQ.size - 1, ap->regs + A_SG_RSPQUEUECREDIT); in configure_sge()
768 sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE | in configure_sge()
771 V_RX_PKT_OFFSET(sge->rx_pkt_pad); in configure_sge()
774 sge->sge_control |= F_ENABLE_BIG_ENDIAN; in configure_sge()
777 /* Initialize no-resource timer */ in configure_sge()
778 sge->intrtimer_nres = SGE_INTRTIMER_NRES * core_ticks_per_usec(ap); in configure_sge()
784 * Return the payload capacity of the jumbo free-list buffers.
788 return sge->freelQ[sge->jumbo_fl].rx_buffer_size - in jumbo_payload_capacity()
789 sge->freelQ[sge->jumbo_fl].dma_offset - in jumbo_payload_capacity()
800 for_each_port(sge->adapter, i) in t1_sge_destroy()
801 free_percpu(sge->port_stats[i]); in t1_sge_destroy()
803 kfree(sge->tx_sched); in t1_sge_destroy()
817 * If the SGE doesn't automatically align packets properly (!sge->rx_pkt_pad),
823 struct pci_dev *pdev = sge->adapter->pdev; in refill_free_list()
824 struct freelQ_ce *ce = &q->centries[q->pidx]; in refill_free_list()
825 struct freelQ_e *e = &q->entries[q->pidx]; in refill_free_list()
826 unsigned int dma_len = q->rx_buffer_size - q->dma_offset; in refill_free_list()
828 while (q->credits < q->size) { in refill_free_list()
830 dma_addr_t mapping; in refill_free_list() local
832 skb = dev_alloc_skb(q->rx_buffer_size); in refill_free_list()
836 skb_reserve(skb, q->dma_offset); in refill_free_list()
837 mapping = dma_map_single(&pdev->dev, skb->data, dma_len, in refill_free_list()
839 skb_reserve(skb, sge->rx_pkt_pad); in refill_free_list()
841 ce->skb = skb; in refill_free_list()
842 dma_unmap_addr_set(ce, dma_addr, mapping); in refill_free_list()
844 e->addr_lo = (u32)mapping; in refill_free_list()
845 e->addr_hi = (u64)mapping >> 32; in refill_free_list()
846 e->len_gen = V_CMD_LEN(dma_len) | V_CMD_GEN1(q->genbit); in refill_free_list()
848 e->gen2 = V_CMD_GEN2(q->genbit); in refill_free_list()
852 if (++q->pidx == q->size) { in refill_free_list()
853 q->pidx = 0; in refill_free_list()
854 q->genbit ^= 1; in refill_free_list()
855 ce = q->centries; in refill_free_list()
856 e = q->entries; in refill_free_list()
858 q->credits++; in refill_free_list()
869 struct adapter *adapter = sge->adapter; in freelQs_empty()
870 u32 irq_reg = readl(adapter->regs + A_SG_INT_ENABLE); in freelQs_empty()
873 refill_free_list(sge, &sge->freelQ[0]); in freelQs_empty()
874 refill_free_list(sge, &sge->freelQ[1]); in freelQs_empty()
876 if (sge->freelQ[0].credits > (sge->freelQ[0].size >> 2) && in freelQs_empty()
877 sge->freelQ[1].credits > (sge->freelQ[1].size >> 2)) { in freelQs_empty()
879 irqholdoff_reg = sge->fixed_intrtimer; in freelQs_empty()
883 irqholdoff_reg = sge->intrtimer_nres; in freelQs_empty()
885 writel(irqholdoff_reg, adapter->regs + A_SG_INTRTIMER); in freelQs_empty()
886 writel(irq_reg, adapter->regs + A_SG_INT_ENABLE); in freelQs_empty()
902 u32 val = readl(sge->adapter->regs + A_PL_ENABLE); in t1_sge_intr_disable()
904 writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); in t1_sge_intr_disable()
905 writel(0, sge->adapter->regs + A_SG_INT_ENABLE); in t1_sge_intr_disable()
914 u32 val = readl(sge->adapter->regs + A_PL_ENABLE); in t1_sge_intr_enable()
916 if (sge->adapter->port[0].dev->hw_features & NETIF_F_TSO) in t1_sge_intr_enable()
918 writel(en, sge->adapter->regs + A_SG_INT_ENABLE); in t1_sge_intr_enable()
919 writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); in t1_sge_intr_enable()
927 writel(SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_CAUSE); in t1_sge_intr_clear()
928 writel(0xffffffff, sge->adapter->regs + A_SG_INT_CAUSE); in t1_sge_intr_clear()
936 struct adapter *adapter = sge->adapter; in t1_sge_intr_error_handler()
937 u32 cause = readl(adapter->regs + A_SG_INT_CAUSE); in t1_sge_intr_error_handler()
940 if (adapter->port[0].dev->hw_features & NETIF_F_TSO) in t1_sge_intr_error_handler()
943 sge->stats.respQ_empty++; in t1_sge_intr_error_handler()
945 sge->stats.respQ_overflow++; in t1_sge_intr_error_handler()
947 adapter->name); in t1_sge_intr_error_handler()
950 sge->stats.freelistQ_empty++; in t1_sge_intr_error_handler()
954 sge->stats.pkt_too_big++; in t1_sge_intr_error_handler()
956 adapter->name); in t1_sge_intr_error_handler()
959 sge->stats.pkt_mismatch++; in t1_sge_intr_error_handler()
960 pr_alert("%s: SGE packet mismatch\n", adapter->name); in t1_sge_intr_error_handler()
964 adapter->pending_thread_intr |= F_PL_INTR_SGE_ERR; in t1_sge_intr_error_handler()
968 writel(cause, adapter->regs + A_SG_INT_CAUSE); in t1_sge_intr_error_handler()
974 return &sge->stats; in t1_sge_get_intr_counts()
977 void t1_sge_get_port_stats(const struct sge *sge, int port, in t1_sge_get_port_stats() argument
984 struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[port], cpu); in t1_sge_get_port_stats()
986 ss->rx_cso_good += st->rx_cso_good; in t1_sge_get_port_stats()
987 ss->tx_cso += st->tx_cso; in t1_sge_get_port_stats()
988 ss->tx_tso += st->tx_tso; in t1_sge_get_port_stats()
989 ss->tx_need_hdrroom += st->tx_need_hdrroom; in t1_sge_get_port_stats()
990 ss->vlan_xtract += st->vlan_xtract; in t1_sge_get_port_stats()
991 ss->vlan_insert += st->vlan_insert; in t1_sge_get_port_stats()
996 * recycle_fl_buf - recycle a free list buffer
1005 struct freelQ_e *from = &fl->entries[idx]; in recycle_fl_buf()
1006 struct freelQ_e *to = &fl->entries[fl->pidx]; in recycle_fl_buf()
1008 fl->centries[fl->pidx] = fl->centries[idx]; in recycle_fl_buf()
1009 to->addr_lo = from->addr_lo; in recycle_fl_buf()
1010 to->addr_hi = from->addr_hi; in recycle_fl_buf()
1011 to->len_gen = G_CMD_LEN(from->len_gen) | V_CMD_GEN1(fl->genbit); in recycle_fl_buf()
1013 to->gen2 = V_CMD_GEN2(fl->genbit); in recycle_fl_buf()
1014 fl->credits++; in recycle_fl_buf()
1016 if (++fl->pidx == fl->size) { in recycle_fl_buf()
1017 fl->pidx = 0; in recycle_fl_buf()
1018 fl->genbit ^= 1; in recycle_fl_buf()
1027 * get_packet - return the next ingress packet buffer
1043 const struct freelQ_ce *ce = &fl->centries[fl->cidx]; in get_packet()
1044 struct pci_dev *pdev = adapter->pdev; in get_packet()
1048 skb = napi_alloc_skb(&adapter->napi, len); in get_packet()
1053 dma_sync_single_for_cpu(&pdev->dev, in get_packet()
1057 skb_copy_from_linear_data(ce->skb, skb->data, len); in get_packet()
1058 dma_sync_single_for_device(&pdev->dev, in get_packet()
1062 recycle_fl_buf(fl, fl->cidx); in get_packet()
1067 if (fl->credits < 2) { in get_packet()
1068 recycle_fl_buf(fl, fl->cidx); in get_packet()
1072 dma_unmap_single(&pdev->dev, dma_unmap_addr(ce, dma_addr), in get_packet()
1074 skb = ce->skb; in get_packet()
1075 prefetch(skb->data); in get_packet()
1082 * unexpected_offload - handle an unexpected offload packet
1092 struct freelQ_ce *ce = &fl->centries[fl->cidx]; in unexpected_offload()
1093 struct sk_buff *skb = ce->skb; in unexpected_offload()
1095 dma_sync_single_for_cpu(&adapter->pdev->dev, in unexpected_offload()
1099 adapter->name, *skb->data); in unexpected_offload()
1100 recycle_fl_buf(fl, fl->cidx); in unexpected_offload()
1104 * T1/T2 SGE limits the maximum DMA size per TX descriptor to
1118 unsigned int nfrags = skb_shinfo(skb)->nr_frags; in compute_large_page_tx_descs()
1122 len -= SGE_TX_DESC_MAX_PLEN; in compute_large_page_tx_descs()
1124 for (i = 0; nfrags--; i++) { in compute_large_page_tx_descs()
1125 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in compute_large_page_tx_descs()
1129 len -= SGE_TX_DESC_MAX_PLEN; in compute_large_page_tx_descs()
1142 static inline void write_tx_desc(struct cmdQ_e *e, dma_addr_t mapping, in write_tx_desc() argument
1148 e->addr_lo = (u32)mapping; in write_tx_desc()
1149 e->addr_hi = (u64)mapping >> 32; in write_tx_desc()
1150 e->len_gen = V_CMD_LEN(len) | V_CMD_GEN1(gen); in write_tx_desc()
1151 e->flags = F_CMD_DATAVALID | V_CMD_EOP(eop) | V_CMD_GEN2(gen); in write_tx_desc()
1157 * write_tx_descs_large_page() writes additional SGE tx descriptors if
1174 *desc_len -= SGE_TX_DESC_MAX_PLEN; in write_large_page_tx_descs()
1177 ce1->skb = NULL; in write_large_page_tx_descs()
1183 if (++pidx == q->size) { in write_large_page_tx_descs()
1186 ce1 = q->centries; in write_large_page_tx_descs()
1187 e1 = q->entries; in write_large_page_tx_descs()
1205 dma_addr_t mapping, desc_mapping; in write_tx_descs() local
1209 nfrags = skb_shinfo(skb)->nr_frags; in write_tx_descs()
1211 e = e1 = &q->entries[pidx]; in write_tx_descs()
1212 ce = &q->centries[pidx]; in write_tx_descs()
1214 mapping = dma_map_single(&adapter->pdev->dev, skb->data, in write_tx_descs()
1217 desc_mapping = mapping; in write_tx_descs()
1225 e->addr_lo = (u32)desc_mapping; in write_tx_descs()
1226 e->addr_hi = (u64)desc_mapping >> 32; in write_tx_descs()
1227 e->len_gen = V_CMD_LEN(first_desc_len) | V_CMD_GEN1(gen); in write_tx_descs()
1228 ce->skb = NULL; in write_tx_descs()
1234 desc_len -= first_desc_len; in write_tx_descs()
1237 if (++pidx == q->size) { in write_tx_descs()
1240 e1 = q->entries; in write_tx_descs()
1241 ce = q->centries; in write_tx_descs()
1252 ce->skb = NULL; in write_tx_descs()
1253 dma_unmap_addr_set(ce, dma_addr, mapping); in write_tx_descs()
1256 for (i = 0; nfrags--; i++) { in write_tx_descs()
1257 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in write_tx_descs()
1260 if (++pidx == q->size) { in write_tx_descs()
1263 e1 = q->entries; in write_tx_descs()
1264 ce = q->centries; in write_tx_descs()
1267 mapping = skb_frag_dma_map(&adapter->pdev->dev, frag, 0, in write_tx_descs()
1269 desc_mapping = mapping; in write_tx_descs()
1278 ce->skb = NULL; in write_tx_descs()
1279 dma_unmap_addr_set(ce, dma_addr, mapping); in write_tx_descs()
1282 ce->skb = skb; in write_tx_descs()
1284 e->flags = flags; in write_tx_descs()
1288 * Clean up completed Tx buffers.
1292 unsigned int reclaim = q->processed - q->cleaned; in reclaim_completed_tx()
1296 q->processed, q->cleaned); in reclaim_completed_tx()
1298 q->cleaned += reclaim; in reclaim_completed_tx()
1309 struct sge *sge = s->sge; in restart_sched()
1310 struct adapter *adapter = sge->adapter; in restart_sched()
1311 struct cmdQ *q = &sge->cmdQ[0]; in restart_sched()
1315 spin_lock(&q->lock); in restart_sched()
1318 credits = q->size - q->in_use; in restart_sched()
1322 count = 1 + skb_shinfo(skb)->nr_frags; in restart_sched()
1324 q->in_use += count; in restart_sched()
1325 genbit = q->genbit; in restart_sched()
1326 pidx = q->pidx; in restart_sched()
1327 q->pidx += count; in restart_sched()
1328 if (q->pidx >= q->size) { in restart_sched()
1329 q->pidx -= q->size; in restart_sched()
1330 q->genbit ^= 1; in restart_sched()
1333 credits = q->size - q->in_use; in restart_sched()
1338 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); in restart_sched()
1339 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { in restart_sched()
1340 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); in restart_sched()
1341 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); in restart_sched()
1344 spin_unlock(&q->lock); in restart_sched()
1348 * sge_rx - process an ingress ethernet packet
1359 struct adapter *adapter = sge->adapter; in sge_rx()
1363 skb = get_packet(adapter, fl, len - sge->rx_pkt_pad); in sge_rx()
1365 sge->stats.rx_drops++; in sge_rx()
1369 p = (const struct cpl_rx_pkt *) skb->data; in sge_rx()
1370 if (p->iff >= adapter->params.nports) { in sge_rx()
1376 st = this_cpu_ptr(sge->port_stats[p->iff]); in sge_rx()
1377 dev = adapter->port[p->iff].dev; in sge_rx()
1379 skb->protocol = eth_type_trans(skb, dev); in sge_rx()
1380 if ((dev->features & NETIF_F_RXCSUM) && p->csum == 0xffff && in sge_rx()
1381 skb->protocol == htons(ETH_P_IP) && in sge_rx()
1382 (skb->data[9] == IPPROTO_TCP || skb->data[9] == IPPROTO_UDP)) { in sge_rx()
1383 ++st->rx_cso_good; in sge_rx()
1384 skb->ip_summed = CHECKSUM_UNNECESSARY; in sge_rx()
1388 if (p->vlan_valid) { in sge_rx()
1389 st->vlan_xtract++; in sge_rx()
1390 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(p->vlan)); in sge_rx()
1397 * we can resume Tx operation after temporarily disabling its packet queue.
1401 unsigned int r = q->processed - q->cleaned; in enough_free_Tx_descs()
1403 return q->in_use - r < (q->size >> 1); in enough_free_Tx_descs()
1408 * after the Tx packet schedulers have been suspended to restart the Tx path.
1412 struct adapter *adap = sge->adapter; in restart_tx_queues()
1415 if (!enough_free_Tx_descs(&sge->cmdQ[0])) in restart_tx_queues()
1419 struct net_device *nd = adap->port[i].dev; in restart_tx_queues()
1421 if (test_and_clear_bit(nd->if_port, &sge->stopped_tx_queues) && in restart_tx_queues()
1423 sge->stats.cmdQ_restarted[2]++; in restart_tx_queues()
1437 struct sge *sge = adapter->sge; in update_tx_info()
1438 struct cmdQ *cmdq = &sge->cmdQ[0]; in update_tx_info()
1440 cmdq->processed += pr0; in update_tx_info()
1446 clear_bit(CMDQ_STAT_RUNNING, &cmdq->status); in update_tx_info()
1448 if (cmdq->cleaned + cmdq->in_use != cmdq->processed && in update_tx_info()
1449 !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) { in update_tx_info()
1450 set_bit(CMDQ_STAT_RUNNING, &cmdq->status); in update_tx_info()
1451 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); in update_tx_info()
1453 if (sge->tx_sched) in update_tx_info()
1454 tasklet_hi_schedule(&sge->tx_sched->sched_tsk); in update_tx_info()
1459 if (unlikely(sge->stopped_tx_queues != 0)) in update_tx_info()
1471 struct sge *sge = adapter->sge; in process_responses()
1472 struct respQ *q = &sge->respQ; in process_responses()
1473 struct respQ_e *e = &q->entries[q->cidx]; in process_responses()
1478 while (done < budget && e->GenerationBit == q->genbit) { in process_responses()
1479 flags |= e->Qsleeping; in process_responses()
1481 cmdq_processed[0] += e->Cmdq0CreditReturn; in process_responses()
1482 cmdq_processed[1] += e->Cmdq1CreditReturn; in process_responses()
1484 /* We batch updates to the TX side to avoid cacheline in process_responses()
1485 * ping-pong of TX state information on MP where the sender in process_responses()
1494 sge->cmdQ[1].processed += cmdq_processed[1]; in process_responses()
1498 if (likely(e->DataValid)) { in process_responses()
1499 struct freelQ *fl = &sge->freelQ[e->FreelistQid]; in process_responses()
1501 BUG_ON(!e->Sop || !e->Eop); in process_responses()
1502 if (unlikely(e->Offload)) in process_responses()
1505 sge_rx(sge, fl, e->BufferLength); in process_responses()
1511 * single free-list buffer; cf. the BUG above. in process_responses()
1513 if (++fl->cidx == fl->size) in process_responses()
1514 fl->cidx = 0; in process_responses()
1515 prefetch(fl->centries[fl->cidx].skb); in process_responses()
1517 if (unlikely(--fl->credits < in process_responses()
1518 fl->size - SGE_FREEL_REFILL_THRESH)) in process_responses()
1521 sge->stats.pure_rsps++; in process_responses()
1524 if (unlikely(++q->cidx == q->size)) { in process_responses()
1525 q->cidx = 0; in process_responses()
1526 q->genbit ^= 1; in process_responses()
1527 e = q->entries; in process_responses()
1531 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) { in process_responses()
1532 writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT); in process_responses()
1533 q->credits = 0; in process_responses()
1538 sge->cmdQ[1].processed += cmdq_processed[1]; in process_responses()
1545 const struct respQ *Q = &adapter->sge->respQ; in responses_pending()
1546 const struct respQ_e *e = &Q->entries[Q->cidx]; in responses_pending()
1548 return e->GenerationBit == Q->genbit; in responses_pending()
1553 * non data-carrying) responses. Such respones are too light-weight to justify
1557 * encounters a valid data-carrying response, 0 otherwise.
1561 struct sge *sge = adapter->sge; in process_pure_responses()
1562 struct respQ *q = &sge->respQ; in process_pure_responses()
1563 struct respQ_e *e = &q->entries[q->cidx]; in process_pure_responses()
1564 const struct freelQ *fl = &sge->freelQ[e->FreelistQid]; in process_pure_responses()
1568 prefetch(fl->centries[fl->cidx].skb); in process_pure_responses()
1569 if (e->DataValid) in process_pure_responses()
1573 flags |= e->Qsleeping; in process_pure_responses()
1575 cmdq_processed[0] += e->Cmdq0CreditReturn; in process_pure_responses()
1576 cmdq_processed[1] += e->Cmdq1CreditReturn; in process_pure_responses()
1579 if (unlikely(++q->cidx == q->size)) { in process_pure_responses()
1580 q->cidx = 0; in process_pure_responses()
1581 q->genbit ^= 1; in process_pure_responses()
1582 e = q->entries; in process_pure_responses()
1586 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) { in process_pure_responses()
1587 writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT); in process_pure_responses()
1588 q->credits = 0; in process_pure_responses()
1590 sge->stats.pure_rsps++; in process_pure_responses()
1591 } while (e->GenerationBit == q->genbit && !e->DataValid); in process_pure_responses()
1594 sge->cmdQ[1].processed += cmdq_processed[1]; in process_pure_responses()
1596 return e->GenerationBit == q->genbit; in process_pure_responses()
1611 writel(adapter->sge->respQ.cidx, in t1_poll()
1612 adapter->regs + A_SG_SLEEPING); in t1_poll()
1622 spin_lock_irq(&adapter->async_lock); in t1_interrupt_thread()
1623 pending_thread_intr = adapter->pending_thread_intr; in t1_interrupt_thread()
1624 adapter->pending_thread_intr = 0; in t1_interrupt_thread()
1625 spin_unlock_irq(&adapter->async_lock); in t1_interrupt_thread()
1636 adapter->name); in t1_interrupt_thread()
1637 t1_sge_stop(adapter->sge); in t1_interrupt_thread()
1641 spin_lock_irq(&adapter->async_lock); in t1_interrupt_thread()
1642 adapter->slow_intr_mask |= F_PL_INTR_EXT; in t1_interrupt_thread()
1644 writel(F_PL_INTR_EXT, adapter->regs + A_PL_CAUSE); in t1_interrupt_thread()
1645 writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA, in t1_interrupt_thread()
1646 adapter->regs + A_PL_ENABLE); in t1_interrupt_thread()
1647 spin_unlock_irq(&adapter->async_lock); in t1_interrupt_thread()
1655 struct sge *sge = adapter->sge; in t1_interrupt()
1659 writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE); in t1_interrupt()
1661 if (napi_schedule_prep(&adapter->napi)) { in t1_interrupt()
1663 __napi_schedule(&adapter->napi); in t1_interrupt()
1666 writel(sge->respQ.cidx, adapter->regs + A_SG_SLEEPING); in t1_interrupt()
1668 napi_enable(&adapter->napi); in t1_interrupt()
1674 spin_lock(&adapter->async_lock); in t1_interrupt()
1676 spin_unlock(&adapter->async_lock); in t1_interrupt()
1679 sge->stats.unhandled_irqs++; in t1_interrupt()
1700 struct sge *sge = adapter->sge; in t1_sge_tx()
1701 struct cmdQ *q = &sge->cmdQ[qid]; in t1_sge_tx()
1704 spin_lock(&q->lock); in t1_sge_tx()
1708 pidx = q->pidx; in t1_sge_tx()
1709 credits = q->size - q->in_use; in t1_sge_tx()
1710 count = 1 + skb_shinfo(skb)->nr_frags; in t1_sge_tx()
1717 set_bit(dev->if_port, &sge->stopped_tx_queues); in t1_sge_tx()
1718 sge->stats.cmdQ_full[2]++; in t1_sge_tx()
1719 pr_err("%s: Tx ring full while queue awake!\n", in t1_sge_tx()
1720 adapter->name); in t1_sge_tx()
1722 spin_unlock(&q->lock); in t1_sge_tx()
1726 if (unlikely(credits - count < q->stop_thres)) { in t1_sge_tx()
1728 set_bit(dev->if_port, &sge->stopped_tx_queues); in t1_sge_tx()
1729 sge->stats.cmdQ_full[2]++; in t1_sge_tx()
1732 /* T204 cmdQ0 skbs that are destined for a certain port have to go in t1_sge_tx()
1735 if (sge->tx_sched && !qid && skb->dev) { in t1_sge_tx()
1743 spin_unlock(&q->lock); in t1_sge_tx()
1746 pidx = q->pidx; in t1_sge_tx()
1747 count = 1 + skb_shinfo(skb)->nr_frags; in t1_sge_tx()
1751 q->in_use += count; in t1_sge_tx()
1752 genbit = q->genbit; in t1_sge_tx()
1753 pidx = q->pidx; in t1_sge_tx()
1754 q->pidx += count; in t1_sge_tx()
1755 if (q->pidx >= q->size) { in t1_sge_tx()
1756 q->pidx -= q->size; in t1_sge_tx()
1757 q->genbit ^= 1; in t1_sge_tx()
1759 spin_unlock(&q->lock); in t1_sge_tx()
1767 * then the interrupt handler will detect the outstanding TX packet in t1_sge_tx()
1773 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); in t1_sge_tx()
1774 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { in t1_sge_tx()
1775 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); in t1_sge_tx()
1776 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); in t1_sge_tx()
1781 if (spin_trylock(&q->lock)) { in t1_sge_tx()
1782 credits = q->size - q->in_use; in t1_sge_tx()
1793 * eth_hdr_len - return the length of an Ethernet header
1802 return e->h_proto == htons(ETH_P_8021Q) ? VLAN_ETH_HLEN : ETH_HLEN; in eth_hdr_len()
1810 struct adapter *adapter = dev->ml_priv; in t1_start_xmit()
1811 struct sge *sge = adapter->sge; in t1_start_xmit()
1812 struct sge_port_stats *st = this_cpu_ptr(sge->port_stats[dev->if_port]); in t1_start_xmit()
1817 if (skb->protocol == htons(ETH_P_CPL5)) in t1_start_xmit()
1821 * We are using a non-standard hard_header_len. in t1_start_xmit()
1824 if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) { in t1_start_xmit()
1826 ++st->tx_need_hdrroom; in t1_start_xmit()
1832 if (skb_shinfo(skb)->gso_size) { in t1_start_xmit()
1836 ++st->tx_tso; in t1_start_xmit()
1842 hdr->opcode = CPL_TX_PKT_LSO; in t1_start_xmit()
1843 hdr->ip_csum_dis = hdr->l4_csum_dis = 0; in t1_start_xmit()
1844 hdr->ip_hdr_words = ip_hdr(skb)->ihl; in t1_start_xmit()
1845 hdr->tcp_hdr_words = tcp_hdr(skb)->doff; in t1_start_xmit()
1846 hdr->eth_type_mss = htons(MK_ETH_TYPE_MSS(eth_type, in t1_start_xmit()
1847 skb_shinfo(skb)->gso_size)); in t1_start_xmit()
1848 hdr->len = htonl(skb->len - sizeof(*hdr)); in t1_start_xmit()
1857 if (unlikely(skb->len < ETH_HLEN || in t1_start_xmit()
1858 skb->len > dev->mtu + eth_hdr_len(skb->data))) { in t1_start_xmit()
1860 skb->len, eth_hdr_len(skb->data), dev->mtu); in t1_start_xmit()
1865 if (skb->ip_summed == CHECKSUM_PARTIAL && in t1_start_xmit()
1866 ip_hdr(skb)->protocol == IPPROTO_UDP) { in t1_start_xmit()
1877 if ((unlikely(!adapter->sge->espibug_skb[dev->if_port]))) { in t1_start_xmit()
1878 if (skb->protocol == htons(ETH_P_ARP) && in t1_start_xmit()
1879 arp_hdr(skb)->ar_op == htons(ARPOP_REQUEST)) { in t1_start_xmit()
1880 adapter->sge->espibug_skb[dev->if_port] = skb; in t1_start_xmit()
1881 /* We want to re-use this skb later. We in t1_start_xmit()
1890 cpl->opcode = CPL_TX_PKT; in t1_start_xmit()
1891 cpl->ip_csum_dis = 1; /* SW calculates IP csum */ in t1_start_xmit()
1892 cpl->l4_csum_dis = skb->ip_summed == CHECKSUM_PARTIAL ? 0 : 1; in t1_start_xmit()
1895 st->tx_cso += (skb->ip_summed == CHECKSUM_PARTIAL); in t1_start_xmit()
1897 cpl->iff = dev->if_port; in t1_start_xmit()
1900 cpl->vlan_valid = 1; in t1_start_xmit()
1901 cpl->vlan = htons(skb_vlan_tag_get(skb)); in t1_start_xmit()
1902 st->vlan_insert++; in t1_start_xmit()
1904 cpl->vlan_valid = 0; in t1_start_xmit()
1920 * Callback for the Tx buffer reclaim timer. Runs with softirqs disabled.
1928 struct cmdQ *q = &sge->cmdQ[i]; in sge_tx_reclaim_cb()
1930 if (!spin_trylock(&q->lock)) in sge_tx_reclaim_cb()
1934 if (i == 0 && q->in_use) { /* flush pending credits */ in sge_tx_reclaim_cb()
1935 writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL); in sge_tx_reclaim_cb()
1937 spin_unlock(&q->lock); in sge_tx_reclaim_cb()
1939 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); in sge_tx_reclaim_cb()
1947 sge->fixed_intrtimer = p->rx_coalesce_usecs * in t1_sge_set_coalesce_params()
1948 core_ticks_per_usec(sge->adapter); in t1_sge_set_coalesce_params()
1949 writel(sge->fixed_intrtimer, sge->adapter->regs + A_SG_INTRTIMER); in t1_sge_set_coalesce_params()
1954 * Allocates both RX and TX resources and configures the SGE. However,
1960 return -ENOMEM; in t1_sge_configure()
1963 return -ENOMEM; in t1_sge_configure()
1973 p->large_buf_capacity = jumbo_payload_capacity(sge); in t1_sge_configure()
1983 writel(0, sge->adapter->regs + A_SG_CONTROL); in t1_sge_stop()
1984 readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ in t1_sge_stop()
1986 if (is_T2(sge->adapter)) in t1_sge_stop()
1987 del_timer_sync(&sge->espibug_timer); in t1_sge_stop()
1989 del_timer_sync(&sge->tx_reclaim_timer); in t1_sge_stop()
1990 if (sge->tx_sched) in t1_sge_stop()
1994 kfree_skb(sge->espibug_skb[i]); in t1_sge_stop()
2002 refill_free_list(sge, &sge->freelQ[0]); in t1_sge_start()
2003 refill_free_list(sge, &sge->freelQ[1]); in t1_sge_start()
2005 writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL); in t1_sge_start()
2006 doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE); in t1_sge_start()
2007 readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ in t1_sge_start()
2009 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); in t1_sge_start()
2011 if (is_T2(sge->adapter)) in t1_sge_start()
2012 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); in t1_sge_start()
2021 struct adapter *adapter = sge->adapter; in espibug_workaround_t204()
2022 unsigned int nports = adapter->params.nports; in espibug_workaround_t204()
2025 if (adapter->open_device_map & PORT_MASK) { in espibug_workaround_t204()
2032 struct sk_buff *skb = sge->espibug_skb[i]; in espibug_workaround_t204()
2034 if (!netif_running(adapter->port[i].dev) || in espibug_workaround_t204()
2035 netif_queue_stopped(adapter->port[i].dev) || in espibug_workaround_t204()
2039 if (!skb->cb[0]) { in espibug_workaround_t204()
2045 skb->len - 10, in espibug_workaround_t204()
2048 skb->cb[0] = 0xff; in espibug_workaround_t204()
2055 t1_sge_tx(skb, adapter, 0, adapter->port[i].dev); in espibug_workaround_t204()
2058 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); in espibug_workaround_t204()
2064 struct adapter *adapter = sge->adapter; in espibug_workaround()
2066 if (netif_running(adapter->port[0].dev)) { in espibug_workaround()
2067 struct sk_buff *skb = sge->espibug_skb[0]; in espibug_workaround()
2071 if (!skb->cb[0]) { in espibug_workaround()
2077 skb->len - 10, in espibug_workaround()
2080 skb->cb[0] = 0xff; in espibug_workaround()
2087 t1_sge_tx(skb, adapter, 0, adapter->port[0].dev); in espibug_workaround()
2090 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); in espibug_workaround()
2104 sge->adapter = adapter; in t1_sge_create()
2105 sge->netdev = adapter->port[0].dev; in t1_sge_create()
2106 sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : 2; in t1_sge_create()
2107 sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0; in t1_sge_create()
2110 sge->port_stats[i] = alloc_percpu(struct sge_port_stats); in t1_sge_create()
2111 if (!sge->port_stats[i]) in t1_sge_create()
2115 timer_setup(&sge->tx_reclaim_timer, sge_tx_reclaim_cb, 0); in t1_sge_create()
2117 if (is_T2(sge->adapter)) { in t1_sge_create()
2118 timer_setup(&sge->espibug_timer, in t1_sge_create()
2119 adapter->params.nports > 1 ? espibug_workaround_t204 : espibug_workaround, in t1_sge_create()
2122 if (adapter->params.nports > 1) in t1_sge_create()
2125 sge->espibug_timeout = 1; in t1_sge_create()
2127 if (adapter->params.nports > 1) in t1_sge_create()
2128 sge->espibug_timeout = HZ/100; in t1_sge_create()
2132 p->cmdQ_size[0] = SGE_CMDQ0_E_N; in t1_sge_create()
2133 p->cmdQ_size[1] = SGE_CMDQ1_E_N; in t1_sge_create()
2134 p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE; in t1_sge_create()
2135 p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE; in t1_sge_create()
2136 if (sge->tx_sched) { in t1_sge_create()
2137 if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) in t1_sge_create()
2138 p->rx_coalesce_usecs = 15; in t1_sge_create()
2140 p->rx_coalesce_usecs = 50; in t1_sge_create()
2142 p->rx_coalesce_usecs = 50; in t1_sge_create()
2144 p->coalesce_enable = 0; in t1_sge_create()
2145 p->sample_interval_usecs = 0; in t1_sge_create()
2150 free_percpu(sge->port_stats[i]); in t1_sge_create()
2151 --i; in t1_sge_create()