Lines Matching refs:pmwrite
91 static int pmwrite(struct cmac *cmac, u32 reg, u32 data32) in pmwrite() function
117 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
118 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
119 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
120 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
123 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0); in pm3393_interrupt_enable()
124 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0); in pm3393_interrupt_enable()
125 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0); in pm3393_interrupt_enable()
126 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0); in pm3393_interrupt_enable()
128 pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0xffff); in pm3393_interrupt_enable()
129 pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0xffff); in pm3393_interrupt_enable()
130 pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
131 pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
132 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0xffff); in pm3393_interrupt_enable()
133 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0xffff); in pm3393_interrupt_enable()
134 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0xffff); in pm3393_interrupt_enable()
135 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0xffff); in pm3393_interrupt_enable()
136 pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0xffff); in pm3393_interrupt_enable()
141 pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, in pm3393_interrupt_enable()
156 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
157 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
158 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
159 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
160 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0); in pm3393_interrupt_disable()
161 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0); in pm3393_interrupt_disable()
162 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0); in pm3393_interrupt_disable()
163 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0); in pm3393_interrupt_disable()
164 pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0); in pm3393_interrupt_disable()
165 pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0); in pm3393_interrupt_disable()
166 pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
167 pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
168 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0); in pm3393_interrupt_disable()
169 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0); in pm3393_interrupt_disable()
170 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0); in pm3393_interrupt_disable()
171 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0); in pm3393_interrupt_disable()
172 pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0); in pm3393_interrupt_disable()
175 pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
255 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, in pm3393_enable()
265 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, val); in pm3393_enable()
275 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_CONTROL, in pm3393_enable_port()
294 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, RXXG_CONF1_VAL); in pm3393_disable()
296 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, TXXG_CONF1_VAL); in pm3393_disable()
328 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH, mtu); in pm3393_set_mtu()
329 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE, mtu); in pm3393_set_mtu()
348 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, in pm3393_set_rx_mode()
357 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, 0xffff); in pm3393_set_rx_mode()
358 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, 0xffff); in pm3393_set_rx_mode()
359 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, 0xffff); in pm3393_set_rx_mode()
360 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, 0xffff); in pm3393_set_rx_mode()
373 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]); in pm3393_set_rx_mode()
374 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, mc_filter[1]); in pm3393_set_rx_mode()
375 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, mc_filter[2]); in pm3393_set_rx_mode()
376 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, mc_filter[3]); in pm3393_set_rx_mode()
380 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode); in pm3393_set_rx_mode()
440 pmwrite(mac, SUNI1x10GEXP_REG_MSTAT_CONTROL, in pm3393_update_statistics()
524 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_15_0, lo); in pm3393_macaddress_set()
525 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_31_16, mid); in pm3393_macaddress_set()
526 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_47_32, hi); in pm3393_macaddress_set()
529 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_15_0, lo); in pm3393_macaddress_set()
530 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_31_16, mid); in pm3393_macaddress_set()
531 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_47_32, hi); in pm3393_macaddress_set()
539 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val); in pm3393_macaddress_set()
541 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW, lo); in pm3393_macaddress_set()
542 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID, mid); in pm3393_macaddress_set()
543 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH, hi); in pm3393_macaddress_set()
546 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val); in pm3393_macaddress_set()