47 #define TRICN_CMD_READ  0x11
48 #define TRICN_CMD_WRITE 0x21
62 	writel(0, adapter->regs + A_ESPI_GOSTAT);  in tricn_write()
86 		tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81);  in tricn_init()
87 		tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81);  in tricn_init()
88 		tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81);  in tricn_init()
91 		tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1);  in tricn_init()
93 		tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1);  in tricn_init()
95 		tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1);  in tricn_init()
96 	tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1);  in tricn_init()
97 	tricn_write(adapter, 0, 2, 5, TRICN_CNFG, 0xe1);  in tricn_init()
98 	tricn_write(adapter, 0, 2, 6, TRICN_CNFG, 0xf1);  in tricn_init()
99 	tricn_write(adapter, 0, 2, 7, TRICN_CNFG, 0x80);  in tricn_init()
100 	tricn_write(adapter, 0, 2, 8, TRICN_CNFG, 0xf1);  in tricn_init()
105 	return 0;  in tricn_init()
119 	enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK;  in t1_espi_intr_enable()
127 	writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS);  in t1_espi_intr_clear()
135 	writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE);  in t1_espi_intr_disable()
170 	return 0;  in t1_espi_intr_handler()
180 	u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200;  in espi_setup_for_pm3393()
182 	writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0);  in espi_setup_for_pm3393()
183 	writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN1);  in espi_setup_for_pm3393()
184 	writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2);  in espi_setup_for_pm3393()
185 	writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN3);  in espi_setup_for_pm3393()
186 	writel(0x100, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);  in espi_setup_for_pm3393()
189 	writel(0x08000008, adapter->regs + A_ESPI_TRAIN);  in espi_setup_for_pm3393()
195 	writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0);  in espi_setup_for_vsc7321()
196 	writel(0x1f401f4, adapter->regs + A_ESPI_SCH_TOKEN1);  in espi_setup_for_vsc7321()
197 	writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2);  in espi_setup_for_vsc7321()
198 	writel(0xa00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);  in espi_setup_for_vsc7321()
199 	writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);  in espi_setup_for_vsc7321()
203 	writel(0x08000008, adapter->regs + A_ESPI_TRAIN);  in espi_setup_for_vsc7321()
214 			writel(0xf00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);  in espi_setup_for_ixf1010()
215 			writel(0x3c0, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);  in espi_setup_for_ixf1010()
217 			writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);  in espi_setup_for_ixf1010()
218 			writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);  in espi_setup_for_ixf1010()
221 		writel(0x1fff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);  in espi_setup_for_ixf1010()
222 		writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);  in espi_setup_for_ixf1010()
230 	u32 status_enable_extra = 0;  in t1_espi_init()
234 	writel(0, adapter->regs + A_ESPI_TRAIN);  in t1_espi_init()
240 		writel(nports == 4 ? 0x200040 : 0x1000080,  in t1_espi_init()
243 		writel(0x800100, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);  in t1_espi_init()
273 	return 0;  in t1_espi_init()
290 #if 0
303 #endif  /*  0  */
311 		return 0;  in t1_espi_get_mon()
313 	sel = V_MONITORED_PORT_NUM((addr & 0x3c) >> 2);  in t1_espi_get_mon()
316 			return 0;  in t1_espi_get_mon()
333  * compare with t1_espi_get_mon(), it reads espiInTxSop[0 ~ 3] in
352 	for (i = 0 ; i < nport; i++, valp++) {  in t1_espi_get_mon_t204()
362 	return 0;  in t1_espi_get_mon_t204()