1 // SPDX-License-Identifier: GPL-2.0
2 /* cavium_ptp.c - PTP 1588 clock on Cavium hardware
3  * Copyright (c) 2003-2015, 2017 Cavium, Inc.
67 		return ERR_PTR(-ENODEV);  in cavium_ptp_get()
71 		ptp = ERR_PTR(-EPROBE_DEFER);  in cavium_ptp_get()
83 	pci_dev_put(ptp->pdev);  in cavium_ptp_put()
88  * cavium_ptp_adjfine() - Adjust ptp frequency
98 	u64 comp;  in cavium_ptp_adjfine()  local
104 		scaled_ppm = -scaled_ppm;  in cavium_ptp_adjfine()
110 	 * convention compensation value is in 64 bit fixed-point  in cavium_ptp_adjfine()
117 	 * comp = tbase + tbase * scaled_ppm / (1M * 2^16)  in cavium_ptp_adjfine()
119 	 * in cavium_ptp_init() -> tbase = 1/Hz. Then we use endian  in cavium_ptp_adjfine()
122 	comp = ((u64)1000000000ull << 32) / clock->clock_rate;  in cavium_ptp_adjfine()
123 	adj = comp * scaled_ppm;  in cavium_ptp_adjfine()
126 	comp = neg_adj ? comp - adj : comp + adj;  in cavium_ptp_adjfine()
128 	spin_lock_irqsave(&clock->spin_lock, flags);  in cavium_ptp_adjfine()
129 	writeq(comp, clock->reg_base + PTP_CLOCK_COMP);  in cavium_ptp_adjfine()
130 	spin_unlock_irqrestore(&clock->spin_lock, flags);  in cavium_ptp_adjfine()
136  * cavium_ptp_adjtime() - Adjust ptp time
146 	spin_lock_irqsave(&clock->spin_lock, flags);  in cavium_ptp_adjtime()
147 	timecounter_adjtime(&clock->time_counter, delta);  in cavium_ptp_adjtime()
148 	spin_unlock_irqrestore(&clock->spin_lock, flags);  in cavium_ptp_adjtime()
157  * cavium_ptp_gettime() - Get hardware clock time with adjustment
169 	spin_lock_irqsave(&clock->spin_lock, flags);  in cavium_ptp_gettime()
170 	nsec = timecounter_read(&clock->time_counter);  in cavium_ptp_gettime()
171 	spin_unlock_irqrestore(&clock->spin_lock, flags);  in cavium_ptp_gettime()
179  * cavium_ptp_settime() - Set hardware clock time. Reset adjustment
193 	spin_lock_irqsave(&clock->spin_lock, flags);  in cavium_ptp_settime()
194 	timecounter_init(&clock->time_counter, &clock->cycle_counter, nsec);  in cavium_ptp_settime()
195 	spin_unlock_irqrestore(&clock->spin_lock, flags);  in cavium_ptp_settime()
201  * cavium_ptp_enable() - Request to enable or disable an ancillary feature.
209 	return -EOPNOTSUPP;  in cavium_ptp_enable()
217 	return readq(clock->reg_base + PTP_CLOCK_HI);  in cavium_ptp_cc_read()
223 	struct device *dev = &pdev->dev;  in cavium_ptp_probe()
232 		err = -ENOMEM;  in cavium_ptp_probe()
236 	clock->pdev = pdev;  in cavium_ptp_probe()
246 	clock->reg_base = pcim_iomap_table(pdev)[PCI_PTP_BAR_NO];  in cavium_ptp_probe()
248 	spin_lock_init(&clock->spin_lock);  in cavium_ptp_probe()
250 	cc = &clock->cycle_counter;  in cavium_ptp_probe()
251 	cc->read = cavium_ptp_cc_read;  in cavium_ptp_probe()
252 	cc->mask = CYCLECOUNTER_MASK(64);  in cavium_ptp_probe()
253 	cc->mult = 1;  in cavium_ptp_probe()
254 	cc->shift = 0;  in cavium_ptp_probe()
256 	timecounter_init(&clock->time_counter, &clock->cycle_counter,  in cavium_ptp_probe()
259 	clock->clock_rate = ptp_cavium_clock_get();  in cavium_ptp_probe()
261 	clock->ptp_info = (struct ptp_clock_info) {  in cavium_ptp_probe()
275 	clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);  in cavium_ptp_probe()
277 	writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);  in cavium_ptp_probe()
279 	clock_comp = ((u64)1000000000ull << 32) / clock->clock_rate;  in cavium_ptp_probe()
280 	writeq(clock_comp, clock->reg_base + PTP_CLOCK_COMP);  in cavium_ptp_probe()
282 	clock->ptp_clock = ptp_clock_register(&clock->ptp_info, dev);  in cavium_ptp_probe()
283 	if (IS_ERR(clock->ptp_clock)) {  in cavium_ptp_probe()
284 		err = PTR_ERR(clock->ptp_clock);  in cavium_ptp_probe()
292 	clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);  in cavium_ptp_probe()
294 	writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);  in cavium_ptp_probe()
305 	 * `dev->driver_data`.  in cavium_ptp_probe()
319 	ptp_clock_unregister(clock->ptp_clock);  in cavium_ptp_remove()
321 	clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);  in cavium_ptp_remove()
323 	writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);  in cavium_ptp_remove()