72 #define ct_reg_addr_init(_bna, _pcidev)					\  argument
80 	(_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva +		\
82 	(_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva +		\
86 #define ct_bit_defn_init(_bna, _pcidev)					\  argument
88 	(_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0 |		\
90 	(_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0 |		\
92 	(_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK);		\
93 	(_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK);		\
94 	(_bna)->bits.halt_status_bits = __HFN_INT_LL_HALT;		\
95 	(_bna)->bits.halt_mask_bits = __HFN_INT_LL_HALT;		\
98 #define ct2_reg_addr_init(_bna, _pcidev)				\  argument
100 	(_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva +		\
102 	(_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva +		\
106 #define ct2_bit_defn_init(_bna, _pcidev)				\  argument
108 	(_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0_CT2 |	\
110 	(_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0_CT2 |	\
112 	(_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK_CT2);	\
113 	(_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK_CT2);	\
114 	(_bna)->bits.halt_status_bits = __HFN_INT_CPQ_HALT_CT2;		\
115 	(_bna)->bits.halt_mask_bits = __HFN_INT_CPQ_HALT_CT2;		\
118 #define bna_reg_addr_init(_bna, _pcidev)				\  argument
122 		ct_reg_addr_init((_bna), (_pcidev));			\
123 		ct_bit_defn_init((_bna), (_pcidev));			\
126 		ct2_reg_addr_init((_bna), (_pcidev));			\
127 		ct2_bit_defn_init((_bna), (_pcidev));			\
132 #define bna_port_id_get(_bna) ((_bna)->ioceth.ioc.port_id)  argument
138 #define BNA_IS_MBOX_INTR(_bna, _intr_status)				\  argument
139 	((_intr_status) & (_bna)->bits.mbox_status_bits)
141 #define BNA_IS_HALT_INTR(_bna, _intr_status)				\  argument
142 	((_intr_status) & (_bna)->bits.halt_status_bits)
144 #define BNA_IS_ERR_INTR(_bna, _intr_status)	\  argument
145 	((_intr_status) & (_bna)->bits.error_status_bits)
147 #define BNA_IS_MBOX_ERR_INTR(_bna, _intr_status)	\  argument
148 	(BNA_IS_MBOX_INTR(_bna, _intr_status) |		\
149 	BNA_IS_ERR_INTR(_bna, _intr_status))
154 #define bna_halt_clear(_bna)						\  argument
157 	init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt);	\
159 	writel(init_halt, (_bna)->ioceth.ioc.ioc_regs.ll_halt);	\
160 	init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt);	\
163 #define bna_intx_disable(_bna, _cur_mask)				\  argument
165 	(_cur_mask) = readl((_bna)->regs.fn_int_mask);		\
166 	writel(0xffffffff, (_bna)->regs.fn_int_mask);		\
189 #define bna_intr_status_get(_bna, _status)				\  argument
191 	(_status) = readl((_bna)->regs.fn_int_status);			\
193 		writel(((_status) & ~(_bna)->bits.mbox_status_bits),	\
194 			(_bna)->regs.fn_int_status);			\
233 #define bna_ib_start(_bna, _ib, _is_regular)				\  argument
238 		bna_intx_disable((_bna), intx_mask);			\
240 		bna_intx_enable((_bna), intx_mask);			\
248 #define bna_ib_stop(_bna, _ib)						\  argument
255 		bna_intx_disable((_bna), intx_mask);			\
257 		bna_intx_enable((_bna), intx_mask);			\