Lines Matching refs:tp
92 #define tg3_flag(tp, flag) \ argument
93 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
94 #define tg3_flag_set(tp, flag) \ argument
95 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
96 #define tg3_flag_clear(tp, flag) \ argument
97 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
130 #define TG3_MAX_MTU(tp) \ argument
131 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
137 #define TG3_RX_STD_RING_SIZE(tp) \ argument
138 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
141 #define TG3_RX_JMB_RING_SIZE(tp) \ argument
142 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
156 #define TG3_RX_STD_RING_BYTES(tp) \ argument
157 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
158 #define TG3_RX_JMB_RING_BYTES(tp) \ argument
159 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
160 #define TG3_RX_RCB_RING_BYTES(tp) \ argument
161 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
176 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ argument
177 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
179 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ argument
180 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
195 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD argument
197 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) argument
201 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset) argument
203 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD) argument
213 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3) argument
214 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1) argument
470 static void tg3_write32(struct tg3 *tp, u32 off, u32 val) in tg3_write32() argument
472 writel(val, tp->regs + off); in tg3_write32()
475 static u32 tg3_read32(struct tg3 *tp, u32 off) in tg3_read32() argument
477 return readl(tp->regs + off); in tg3_read32()
480 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) in tg3_ape_write32() argument
482 writel(val, tp->aperegs + off); in tg3_ape_write32()
485 static u32 tg3_ape_read32(struct tg3 *tp, u32 off) in tg3_ape_read32() argument
487 return readl(tp->aperegs + off); in tg3_ape_read32()
490 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) in tg3_write_indirect_reg32() argument
494 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
495 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_write_indirect_reg32()
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_reg32()
497 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
500 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) in tg3_write_flush_reg32() argument
502 writel(val, tp->regs + off); in tg3_write_flush_reg32()
503 readl(tp->regs + off); in tg3_write_flush_reg32()
506 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) in tg3_read_indirect_reg32() argument
511 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
512 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_read_indirect_reg32()
513 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_reg32()
514 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
518 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) in tg3_write_indirect_mbox() argument
523 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + in tg3_write_indirect_mbox()
528 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + in tg3_write_indirect_mbox()
533 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
534 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_write_indirect_mbox()
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_mbox()
536 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
543 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, in tg3_write_indirect_mbox()
544 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); in tg3_write_indirect_mbox()
548 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) in tg3_read_indirect_mbox() argument
553 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
554 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_read_indirect_mbox()
555 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_mbox()
556 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
565 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) in _tw32_flush() argument
567 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) in _tw32_flush()
569 tp->write32(tp, off, val); in _tw32_flush()
572 tg3_write32(tp, off, val); in _tw32_flush()
575 tp->read32(tp, off); in _tw32_flush()
584 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) in tw32_mailbox_flush() argument
586 tp->write32_mbox(tp, off, val); in tw32_mailbox_flush()
587 if (tg3_flag(tp, FLUSH_POSTED_WRITES) || in tw32_mailbox_flush()
588 (!tg3_flag(tp, MBOX_WRITE_REORDER) && in tw32_mailbox_flush()
589 !tg3_flag(tp, ICH_WORKAROUND))) in tw32_mailbox_flush()
590 tp->read32_mbox(tp, off); in tw32_mailbox_flush()
593 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) in tg3_write32_tx_mbox() argument
595 void __iomem *mbox = tp->regs + off; in tg3_write32_tx_mbox()
597 if (tg3_flag(tp, TXD_MBOX_HWBUG)) in tg3_write32_tx_mbox()
599 if (tg3_flag(tp, MBOX_WRITE_REORDER) || in tg3_write32_tx_mbox()
600 tg3_flag(tp, FLUSH_POSTED_WRITES)) in tg3_write32_tx_mbox()
604 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) in tg3_read32_mbox_5906() argument
606 return readl(tp->regs + off + GRCMBOX_BASE); in tg3_read32_mbox_5906()
609 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) in tg3_write32_mbox_5906() argument
611 writel(val, tp->regs + off + GRCMBOX_BASE); in tg3_write32_mbox_5906()
614 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
615 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
616 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
617 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
618 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
620 #define tw32(reg, val) tp->write32(tp, reg, val)
621 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
622 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
623 #define tr32(reg) tp->read32(tp, reg)
625 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) in tg3_write_mem() argument
629 if (tg3_asic_rev(tp) == ASIC_REV_5906 && in tg3_write_mem()
633 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_mem()
634 if (tg3_flag(tp, SRAM_USE_CONFIG)) { in tg3_write_mem()
635 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_write_mem()
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_write_mem()
639 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_write_mem()
647 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_mem()
650 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) in tg3_read_mem() argument
654 if (tg3_asic_rev(tp) == ASIC_REV_5906 && in tg3_read_mem()
660 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_mem()
661 if (tg3_flag(tp, SRAM_USE_CONFIG)) { in tg3_read_mem()
662 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_read_mem()
663 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_read_mem()
666 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_read_mem()
674 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_mem()
677 static void tg3_ape_lock_init(struct tg3 *tp) in tg3_ape_lock_init() argument
682 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_lock_init()
697 if (!tp->pci_fn) in tg3_ape_lock_init()
700 bit = 1 << tp->pci_fn; in tg3_ape_lock_init()
702 tg3_ape_write32(tp, regbase + 4 * i, bit); in tg3_ape_lock_init()
707 static int tg3_ape_lock(struct tg3 *tp, int locknum) in tg3_ape_lock() argument
713 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_lock()
718 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_lock()
723 if (!tp->pci_fn) in tg3_ape_lock()
726 bit = 1 << tp->pci_fn; in tg3_ape_lock()
738 if (tg3_asic_rev(tp) == ASIC_REV_5761) { in tg3_ape_lock()
748 tg3_ape_write32(tp, req + off, bit); in tg3_ape_lock()
752 status = tg3_ape_read32(tp, gnt + off); in tg3_ape_lock()
755 if (pci_channel_offline(tp->pdev)) in tg3_ape_lock()
763 tg3_ape_write32(tp, gnt + off, bit); in tg3_ape_lock()
770 static void tg3_ape_unlock(struct tg3 *tp, int locknum) in tg3_ape_unlock() argument
774 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_unlock()
779 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_unlock()
784 if (!tp->pci_fn) in tg3_ape_unlock()
787 bit = 1 << tp->pci_fn; in tg3_ape_unlock()
799 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_unlock()
804 tg3_ape_write32(tp, gnt + 4 * locknum, bit); in tg3_ape_unlock()
807 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us) in tg3_ape_event_lock() argument
812 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) in tg3_ape_event_lock()
815 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); in tg3_ape_event_lock()
819 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_event_lock()
829 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us) in tg3_ape_wait_for_event() argument
834 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); in tg3_ape_wait_for_event()
845 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off, in tg3_ape_scratchpad_read() argument
851 if (!tg3_flag(tp, APE_HAS_NCSI)) in tg3_ape_scratchpad_read()
854 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_ape_scratchpad_read()
858 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_scratchpad_read()
862 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) + in tg3_ape_scratchpad_read()
865 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN); in tg3_ape_scratchpad_read()
874 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_scratchpad_read()
879 err = tg3_ape_event_lock(tp, 1000); in tg3_ape_scratchpad_read()
886 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata); in tg3_ape_scratchpad_read()
888 tg3_ape_write32(tp, bufoff, base_off); in tg3_ape_scratchpad_read()
889 tg3_ape_write32(tp, bufoff + sizeof(u32), length); in tg3_ape_scratchpad_read()
891 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_scratchpad_read()
892 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); in tg3_ape_scratchpad_read()
896 if (tg3_ape_wait_for_event(tp, 30000)) in tg3_ape_scratchpad_read()
900 u32 val = tg3_ape_read32(tp, msgoff + i); in tg3_ape_scratchpad_read()
910 static int tg3_ape_send_event(struct tg3 *tp, u32 event) in tg3_ape_send_event() argument
915 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_ape_send_event()
919 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_send_event()
924 err = tg3_ape_event_lock(tp, 20000); in tg3_ape_send_event()
928 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, in tg3_ape_send_event()
931 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_send_event()
932 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); in tg3_ape_send_event()
937 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) in tg3_ape_driver_state_change() argument
942 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_driver_state_change()
947 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_ape_driver_state_change()
948 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, in tg3_ape_driver_state_change()
950 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, in tg3_ape_driver_state_change()
952 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); in tg3_ape_driver_state_change()
953 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); in tg3_ape_driver_state_change()
954 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, in tg3_ape_driver_state_change()
956 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, in tg3_ape_driver_state_change()
958 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, in tg3_ape_driver_state_change()
964 if (device_may_wakeup(&tp->pdev->dev) && in tg3_ape_driver_state_change()
965 tg3_flag(tp, WOL_ENABLE)) { in tg3_ape_driver_state_change()
966 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, in tg3_ape_driver_state_change()
972 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); in tg3_ape_driver_state_change()
982 tg3_ape_send_event(tp, event); in tg3_ape_driver_state_change()
985 static void tg3_send_ape_heartbeat(struct tg3 *tp, in tg3_send_ape_heartbeat() argument
989 if (!tg3_flag(tp, ENABLE_APE) || in tg3_send_ape_heartbeat()
990 time_before(jiffies, tp->ape_hb_jiffies + interval)) in tg3_send_ape_heartbeat()
993 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_send_ape_heartbeat()
994 tp->ape_hb_jiffies = jiffies; in tg3_send_ape_heartbeat()
997 static void tg3_disable_ints(struct tg3 *tp) in tg3_disable_ints() argument
1002 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_disable_ints()
1003 for (i = 0; i < tp->irq_max; i++) in tg3_disable_ints()
1004 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); in tg3_disable_ints()
1007 static void tg3_enable_ints(struct tg3 *tp) in tg3_enable_ints() argument
1011 tp->irq_sync = 0; in tg3_enable_ints()
1015 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_enable_ints()
1017 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; in tg3_enable_ints()
1018 for (i = 0; i < tp->irq_cnt; i++) { in tg3_enable_ints()
1019 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_enable_ints()
1022 if (tg3_flag(tp, 1SHOT_MSI)) in tg3_enable_ints()
1025 tp->coal_now |= tnapi->coal_now; in tg3_enable_ints()
1029 if (!tg3_flag(tp, TAGGED_STATUS) && in tg3_enable_ints()
1030 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) in tg3_enable_ints()
1031 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_enable_ints()
1033 tw32(HOSTCC_MODE, tp->coal_now); in tg3_enable_ints()
1035 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); in tg3_enable_ints()
1040 struct tg3 *tp = tnapi->tp; in tg3_has_work() local
1045 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { in tg3_has_work()
1069 struct tg3 *tp = tnapi->tp; in tg3_int_reenable() local
1077 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi)) in tg3_int_reenable()
1078 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_int_reenable()
1082 static void tg3_switch_clocks(struct tg3 *tp) in tg3_switch_clocks() argument
1087 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS)) in tg3_switch_clocks()
1096 tp->pci_clock_ctrl = clock_ctrl; in tg3_switch_clocks()
1098 if (tg3_flag(tp, 5705_PLUS)) { in tg3_switch_clocks()
1117 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, in __tg3_readphy() argument
1124 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1126 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_readphy()
1130 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_readphy()
1161 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1162 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_readphy()
1166 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_readphy()
1171 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) in tg3_readphy() argument
1173 return __tg3_readphy(tp, tp->phy_addr, reg, val); in tg3_readphy()
1176 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, in __tg3_writephy() argument
1183 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in __tg3_writephy()
1187 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1189 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_writephy()
1193 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_writephy()
1220 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1221 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_writephy()
1225 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_writephy()
1230 static int tg3_writephy(struct tg3 *tp, int reg, u32 val) in tg3_writephy() argument
1232 return __tg3_writephy(tp, tp->phy_addr, reg, val); in tg3_writephy()
1235 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) in tg3_phy_cl45_write() argument
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_write()
1243 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_write()
1247 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_write()
1252 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); in tg3_phy_cl45_write()
1258 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) in tg3_phy_cl45_read() argument
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_read()
1266 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_read()
1270 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_read()
1275 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); in tg3_phy_cl45_read()
1281 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) in tg3_phydsp_read() argument
1285 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_read()
1287 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_read()
1292 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) in tg3_phydsp_write() argument
1296 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_write()
1298 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_write()
1303 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) in tg3_phy_auxctl_read() argument
1307 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, in tg3_phy_auxctl_read()
1311 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); in tg3_phy_auxctl_read()
1316 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) in tg3_phy_auxctl_write() argument
1321 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); in tg3_phy_auxctl_write()
1324 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable) in tg3_phy_toggle_auxctl_smdsp() argument
1329 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); in tg3_phy_toggle_auxctl_smdsp()
1339 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, in tg3_phy_toggle_auxctl_smdsp()
1345 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val) in tg3_phy_shdw_write() argument
1347 return tg3_writephy(tp, MII_TG3_MISC_SHDW, in tg3_phy_shdw_write()
1351 static int tg3_bmcr_reset(struct tg3 *tp) in tg3_bmcr_reset() argument
1360 err = tg3_writephy(tp, MII_BMCR, phy_control); in tg3_bmcr_reset()
1366 err = tg3_readphy(tp, MII_BMCR, &phy_control); in tg3_bmcr_reset()
1384 struct tg3 *tp = bp->priv; in tg3_mdio_read() local
1387 spin_lock_bh(&tp->lock); in tg3_mdio_read()
1389 if (__tg3_readphy(tp, mii_id, reg, &val)) in tg3_mdio_read()
1392 spin_unlock_bh(&tp->lock); in tg3_mdio_read()
1399 struct tg3 *tp = bp->priv; in tg3_mdio_write() local
1402 spin_lock_bh(&tp->lock); in tg3_mdio_write()
1404 if (__tg3_writephy(tp, mii_id, reg, val)) in tg3_mdio_write()
1407 spin_unlock_bh(&tp->lock); in tg3_mdio_write()
1412 static void tg3_mdio_config_5785(struct tg3 *tp) in tg3_mdio_config_5785() argument
1417 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_config_5785()
1448 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) in tg3_mdio_config_5785()
1461 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { in tg3_mdio_config_5785()
1462 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_config_5785()
1464 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_config_5785()
1479 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { in tg3_mdio_config_5785()
1480 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_config_5785()
1485 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_config_5785()
1493 static void tg3_mdio_start(struct tg3 *tp) in tg3_mdio_start() argument
1495 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; in tg3_mdio_start()
1496 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_mdio_start()
1499 if (tg3_flag(tp, MDIOBUS_INITED) && in tg3_mdio_start()
1500 tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_mdio_start()
1501 tg3_mdio_config_5785(tp); in tg3_mdio_start()
1504 static int tg3_mdio_init(struct tg3 *tp) in tg3_mdio_init() argument
1510 if (tg3_flag(tp, 5717_PLUS)) { in tg3_mdio_init()
1513 tp->phy_addr = tp->pci_fn + 1; in tg3_mdio_init()
1515 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) in tg3_mdio_init()
1521 tp->phy_addr += 7; in tg3_mdio_init()
1522 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) { in tg3_mdio_init()
1525 addr = ssb_gige_get_phyaddr(tp->pdev); in tg3_mdio_init()
1528 tp->phy_addr = addr; in tg3_mdio_init()
1530 tp->phy_addr = TG3_PHY_MII_ADDR; in tg3_mdio_init()
1532 tg3_mdio_start(tp); in tg3_mdio_init()
1534 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED)) in tg3_mdio_init()
1537 tp->mdio_bus = mdiobus_alloc(); in tg3_mdio_init()
1538 if (tp->mdio_bus == NULL) in tg3_mdio_init()
1541 tp->mdio_bus->name = "tg3 mdio bus"; in tg3_mdio_init()
1542 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", pci_dev_id(tp->pdev)); in tg3_mdio_init()
1543 tp->mdio_bus->priv = tp; in tg3_mdio_init()
1544 tp->mdio_bus->parent = &tp->pdev->dev; in tg3_mdio_init()
1545 tp->mdio_bus->read = &tg3_mdio_read; in tg3_mdio_init()
1546 tp->mdio_bus->write = &tg3_mdio_write; in tg3_mdio_init()
1547 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr); in tg3_mdio_init()
1554 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) in tg3_mdio_init()
1555 tg3_bmcr_reset(tp); in tg3_mdio_init()
1557 i = mdiobus_register(tp->mdio_bus); in tg3_mdio_init()
1559 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); in tg3_mdio_init()
1560 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1564 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_init()
1567 dev_warn(&tp->pdev->dev, "No PHY devices\n"); in tg3_mdio_init()
1568 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_init()
1569 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1592 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_mdio_init()
1596 tg3_flag_set(tp, MDIOBUS_INITED); in tg3_mdio_init()
1598 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_mdio_init()
1599 tg3_mdio_config_5785(tp); in tg3_mdio_init()
1604 static void tg3_mdio_fini(struct tg3 *tp) in tg3_mdio_fini() argument
1606 if (tg3_flag(tp, MDIOBUS_INITED)) { in tg3_mdio_fini()
1607 tg3_flag_clear(tp, MDIOBUS_INITED); in tg3_mdio_fini()
1608 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_fini()
1609 mdiobus_free(tp->mdio_bus); in tg3_mdio_fini()
1614 static inline void tg3_generate_fw_event(struct tg3 *tp) in tg3_generate_fw_event() argument
1622 tp->last_event_jiffies = jiffies; in tg3_generate_fw_event()
1628 static void tg3_wait_for_event_ack(struct tg3 *tp) in tg3_wait_for_event_ack() argument
1635 time_remain = (long)(tp->last_event_jiffies + 1 + in tg3_wait_for_event_ack()
1650 if (pci_channel_offline(tp->pdev)) in tg3_wait_for_event_ack()
1658 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data) in tg3_phy_gather_ump_data() argument
1663 if (!tg3_readphy(tp, MII_BMCR, ®)) in tg3_phy_gather_ump_data()
1665 if (!tg3_readphy(tp, MII_BMSR, ®)) in tg3_phy_gather_ump_data()
1670 if (!tg3_readphy(tp, MII_ADVERTISE, ®)) in tg3_phy_gather_ump_data()
1672 if (!tg3_readphy(tp, MII_LPA, ®)) in tg3_phy_gather_ump_data()
1677 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { in tg3_phy_gather_ump_data()
1678 if (!tg3_readphy(tp, MII_CTRL1000, ®)) in tg3_phy_gather_ump_data()
1680 if (!tg3_readphy(tp, MII_STAT1000, ®)) in tg3_phy_gather_ump_data()
1685 if (!tg3_readphy(tp, MII_PHYADDR, ®)) in tg3_phy_gather_ump_data()
1693 static void tg3_ump_link_report(struct tg3 *tp) in tg3_ump_link_report() argument
1697 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF)) in tg3_ump_link_report()
1700 tg3_phy_gather_ump_data(tp, data); in tg3_ump_link_report()
1702 tg3_wait_for_event_ack(tp); in tg3_ump_link_report()
1704 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); in tg3_ump_link_report()
1705 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); in tg3_ump_link_report()
1706 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]); in tg3_ump_link_report()
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]); in tg3_ump_link_report()
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]); in tg3_ump_link_report()
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]); in tg3_ump_link_report()
1711 tg3_generate_fw_event(tp); in tg3_ump_link_report()
1715 static void tg3_stop_fw(struct tg3 *tp) in tg3_stop_fw() argument
1717 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { in tg3_stop_fw()
1719 tg3_wait_for_event_ack(tp); in tg3_stop_fw()
1721 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); in tg3_stop_fw()
1723 tg3_generate_fw_event(tp); in tg3_stop_fw()
1726 tg3_wait_for_event_ack(tp); in tg3_stop_fw()
1731 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) in tg3_write_sig_pre_reset() argument
1733 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, in tg3_write_sig_pre_reset()
1736 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { in tg3_write_sig_pre_reset()
1739 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1744 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1749 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1760 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) in tg3_write_sig_post_reset() argument
1762 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { in tg3_write_sig_post_reset()
1765 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_post_reset()
1770 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_post_reset()
1781 static void tg3_write_sig_legacy(struct tg3 *tp, int kind) in tg3_write_sig_legacy() argument
1783 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_write_sig_legacy()
1786 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1791 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1796 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1806 static int tg3_poll_fw(struct tg3 *tp) in tg3_poll_fw() argument
1811 if (tg3_flag(tp, NO_FWARE_REPORTED)) in tg3_poll_fw()
1814 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_poll_fw()
1819 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_poll_fw()
1824 if (pci_channel_offline(tp->pdev)) in tg3_poll_fw()
1834 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); in tg3_poll_fw()
1837 if (pci_channel_offline(tp->pdev)) { in tg3_poll_fw()
1838 if (!tg3_flag(tp, NO_FWARE_REPORTED)) { in tg3_poll_fw()
1839 tg3_flag_set(tp, NO_FWARE_REPORTED); in tg3_poll_fw()
1840 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1854 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) { in tg3_poll_fw()
1855 tg3_flag_set(tp, NO_FWARE_REPORTED); in tg3_poll_fw()
1857 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1860 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) { in tg3_poll_fw()
1870 static void tg3_link_report(struct tg3 *tp) in tg3_link_report() argument
1872 if (!netif_carrier_ok(tp->dev)) { in tg3_link_report()
1873 netif_info(tp, link, tp->dev, "Link is down\n"); in tg3_link_report()
1874 tg3_ump_link_report(tp); in tg3_link_report()
1875 } else if (netif_msg_link(tp)) { in tg3_link_report()
1876 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", in tg3_link_report()
1877 (tp->link_config.active_speed == SPEED_1000 ? in tg3_link_report()
1879 (tp->link_config.active_speed == SPEED_100 ? in tg3_link_report()
1881 (tp->link_config.active_duplex == DUPLEX_FULL ? in tg3_link_report()
1884 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", in tg3_link_report()
1885 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? in tg3_link_report()
1887 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? in tg3_link_report()
1890 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_link_report()
1891 netdev_info(tp->dev, "EEE is %s\n", in tg3_link_report()
1892 tp->setlpicnt ? "enabled" : "disabled"); in tg3_link_report()
1894 tg3_ump_link_report(tp); in tg3_link_report()
1897 tp->link_up = netif_carrier_ok(tp->dev); in tg3_link_report()
1960 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) in tg3_setup_flow_control() argument
1964 u32 old_rx_mode = tp->rx_mode; in tg3_setup_flow_control()
1965 u32 old_tx_mode = tp->tx_mode; in tg3_setup_flow_control()
1967 if (tg3_flag(tp, USE_PHYLIB)) in tg3_setup_flow_control()
1968 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg; in tg3_setup_flow_control()
1970 autoneg = tp->link_config.autoneg; in tg3_setup_flow_control()
1972 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) { in tg3_setup_flow_control()
1973 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_setup_flow_control()
1978 flowctrl = tp->link_config.flowctrl; in tg3_setup_flow_control()
1980 tp->link_config.active_flowctrl = flowctrl; in tg3_setup_flow_control()
1983 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1985 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1987 if (old_rx_mode != tp->rx_mode) in tg3_setup_flow_control()
1988 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_setup_flow_control()
1991 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1993 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1995 if (old_tx_mode != tp->tx_mode) in tg3_setup_flow_control()
1996 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_setup_flow_control()
2003 struct tg3 *tp = netdev_priv(dev); in tg3_adjust_link() local
2004 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_adjust_link()
2006 spin_lock_bh(&tp->lock); in tg3_adjust_link()
2008 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | in tg3_adjust_link()
2011 oldflowctrl = tp->link_config.active_flowctrl; in tg3_adjust_link()
2020 tg3_asic_rev(tp) != ASIC_REV_5785) in tg3_adjust_link()
2029 tp->link_config.flowctrl); in tg3_adjust_link()
2037 tg3_setup_flow_control(tp, lcl_adv, rmt_adv); in tg3_adjust_link()
2041 if (mac_mode != tp->mac_mode) { in tg3_adjust_link()
2042 tp->mac_mode = mac_mode; in tg3_adjust_link()
2043 tw32_f(MAC_MODE, tp->mac_mode); in tg3_adjust_link()
2047 if (tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_adjust_link()
2067 if (phydev->link != tp->old_link || in tg3_adjust_link()
2068 phydev->speed != tp->link_config.active_speed || in tg3_adjust_link()
2069 phydev->duplex != tp->link_config.active_duplex || in tg3_adjust_link()
2070 oldflowctrl != tp->link_config.active_flowctrl) in tg3_adjust_link()
2073 tp->old_link = phydev->link; in tg3_adjust_link()
2074 tp->link_config.active_speed = phydev->speed; in tg3_adjust_link()
2075 tp->link_config.active_duplex = phydev->duplex; in tg3_adjust_link()
2077 spin_unlock_bh(&tp->lock); in tg3_adjust_link()
2080 tg3_link_report(tp); in tg3_adjust_link()
2083 static int tg3_phy_init(struct tg3 *tp) in tg3_phy_init() argument
2087 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) in tg3_phy_init()
2091 tg3_bmcr_reset(tp); in tg3_phy_init()
2093 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_init()
2096 phydev = phy_connect(tp->dev, phydev_name(phydev), in tg3_phy_init()
2099 dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); in tg3_phy_init()
2107 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init()
2118 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_init()
2122 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; in tg3_phy_init()
2129 static void tg3_phy_start(struct tg3 *tp) in tg3_phy_start() argument
2133 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_start()
2136 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_start()
2138 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_phy_start()
2139 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_phy_start()
2140 phydev->speed = tp->link_config.speed; in tg3_phy_start()
2141 phydev->duplex = tp->link_config.duplex; in tg3_phy_start()
2142 phydev->autoneg = tp->link_config.autoneg; in tg3_phy_start()
2144 phydev->advertising, tp->link_config.advertising); in tg3_phy_start()
2152 static void tg3_phy_stop(struct tg3 *tp) in tg3_phy_stop() argument
2154 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_stop()
2157 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_stop()
2160 static void tg3_phy_fini(struct tg3 *tp) in tg3_phy_fini() argument
2162 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_phy_fini()
2163 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_fini()
2164 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; in tg3_phy_fini()
2168 static int tg3_phy_set_extloopbk(struct tg3 *tp) in tg3_phy_set_extloopbk() argument
2173 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_set_extloopbk()
2176 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_set_extloopbk()
2178 err = tg3_phy_auxctl_write(tp, in tg3_phy_set_extloopbk()
2185 err = tg3_phy_auxctl_read(tp, in tg3_phy_set_extloopbk()
2191 err = tg3_phy_auxctl_write(tp, in tg3_phy_set_extloopbk()
2198 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) in tg3_phy_fet_toggle_apd() argument
2202 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { in tg3_phy_fet_toggle_apd()
2205 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_fet_toggle_apd()
2207 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { in tg3_phy_fet_toggle_apd()
2212 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); in tg3_phy_fet_toggle_apd()
2214 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_phy_fet_toggle_apd()
2218 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) in tg3_phy_toggle_apd() argument
2222 if (!tg3_flag(tp, 5705_PLUS) || in tg3_phy_toggle_apd()
2223 (tg3_flag(tp, 5717_PLUS) && in tg3_phy_toggle_apd()
2224 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) in tg3_phy_toggle_apd()
2227 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_apd()
2228 tg3_phy_fet_toggle_apd(tp, enable); in tg3_phy_toggle_apd()
2236 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable) in tg3_phy_toggle_apd()
2239 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg); in tg3_phy_toggle_apd()
2246 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg); in tg3_phy_toggle_apd()
2249 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable) in tg3_phy_toggle_automdix() argument
2253 if (!tg3_flag(tp, 5705_PLUS) || in tg3_phy_toggle_automdix()
2254 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_toggle_automdix()
2257 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_automdix()
2260 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { in tg3_phy_toggle_automdix()
2263 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_toggle_automdix()
2265 if (!tg3_readphy(tp, reg, &phy)) { in tg3_phy_toggle_automdix()
2270 tg3_writephy(tp, reg, phy); in tg3_phy_toggle_automdix()
2272 tg3_writephy(tp, MII_TG3_FET_TEST, ephy); in tg3_phy_toggle_automdix()
2277 ret = tg3_phy_auxctl_read(tp, in tg3_phy_toggle_automdix()
2284 tg3_phy_auxctl_write(tp, in tg3_phy_toggle_automdix()
2290 static void tg3_phy_set_wirespeed(struct tg3 *tp) in tg3_phy_set_wirespeed() argument
2295 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) in tg3_phy_set_wirespeed()
2298 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); in tg3_phy_set_wirespeed()
2300 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()
2304 static void tg3_phy_apply_otp(struct tg3 *tp) in tg3_phy_apply_otp() argument
2308 if (!tp->phy_otp) in tg3_phy_apply_otp()
2311 otp = tp->phy_otp; in tg3_phy_apply_otp()
2313 if (tg3_phy_toggle_auxctl_smdsp(tp, true)) in tg3_phy_apply_otp()
2318 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); in tg3_phy_apply_otp()
2322 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); in tg3_phy_apply_otp()
2326 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); in tg3_phy_apply_otp()
2329 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); in tg3_phy_apply_otp()
2332 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); in tg3_phy_apply_otp()
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); in tg3_phy_apply_otp()
2338 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_apply_otp()
2341 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_keee *eee) in tg3_eee_pull_config() argument
2344 struct ethtool_keee *dest = &tp->eee; in tg3_eee_pull_config()
2346 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_eee_pull_config()
2352 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val)) in tg3_eee_pull_config()
2363 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val)) in tg3_eee_pull_config()
2368 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val)) in tg3_eee_pull_config()
2381 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up) in tg3_phy_eee_adjust() argument
2385 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_adjust()
2388 tp->setlpicnt = 0; in tg3_phy_eee_adjust()
2390 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_phy_eee_adjust()
2392 tp->link_config.active_duplex == DUPLEX_FULL && in tg3_phy_eee_adjust()
2393 (tp->link_config.active_speed == SPEED_100 || in tg3_phy_eee_adjust()
2394 tp->link_config.active_speed == SPEED_1000)) { in tg3_phy_eee_adjust()
2397 if (tp->link_config.active_speed == SPEED_1000) in tg3_phy_eee_adjust()
2404 tg3_eee_pull_config(tp, NULL); in tg3_phy_eee_adjust()
2405 if (tp->eee.eee_active) in tg3_phy_eee_adjust()
2406 tp->setlpicnt = 2; in tg3_phy_eee_adjust()
2409 if (!tp->setlpicnt) { in tg3_phy_eee_adjust()
2411 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_eee_adjust()
2412 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); in tg3_phy_eee_adjust()
2413 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_eee_adjust()
2421 static void tg3_phy_eee_enable(struct tg3 *tp) in tg3_phy_eee_enable() argument
2425 if (tp->link_config.active_speed == SPEED_1000 && in tg3_phy_eee_enable()
2426 (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_phy_eee_enable()
2427 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_phy_eee_enable()
2428 tg3_flag(tp, 57765_CLASS)) && in tg3_phy_eee_enable()
2429 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_eee_enable()
2432 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); in tg3_phy_eee_enable()
2433 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_eee_enable()
2440 static int tg3_wait_macro_done(struct tg3 *tp) in tg3_wait_macro_done() argument
2447 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { in tg3_wait_macro_done()
2458 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) in tg3_phy_write_and_check_testpat() argument
2471 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2473 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_write_and_check_testpat()
2476 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, in tg3_phy_write_and_check_testpat()
2479 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_write_and_check_testpat()
2480 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2485 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2487 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); in tg3_phy_write_and_check_testpat()
2488 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2493 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); in tg3_phy_write_and_check_testpat()
2494 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2502 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || in tg3_phy_write_and_check_testpat()
2503 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || in tg3_phy_write_and_check_testpat()
2504 tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2512 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); in tg3_phy_write_and_check_testpat()
2513 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); in tg3_phy_write_and_check_testpat()
2514 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); in tg3_phy_write_and_check_testpat()
2524 static int tg3_phy_reset_chanpat(struct tg3 *tp) in tg3_phy_reset_chanpat() argument
2531 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_reset_chanpat()
2533 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_reset_chanpat()
2535 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); in tg3_phy_reset_chanpat()
2536 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_reset_chanpat()
2537 if (tg3_wait_macro_done(tp)) in tg3_phy_reset_chanpat()
2544 static int tg3_phy_reset_5703_4_5(struct tg3 *tp) in tg3_phy_reset_5703_4_5() argument
2553 err = tg3_bmcr_reset(tp); in tg3_phy_reset_5703_4_5()
2560 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) in tg3_phy_reset_5703_4_5()
2564 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2567 tg3_writephy(tp, MII_BMCR, in tg3_phy_reset_5703_4_5()
2571 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig)) in tg3_phy_reset_5703_4_5()
2574 tg3_writephy(tp, MII_CTRL1000, in tg3_phy_reset_5703_4_5()
2577 err = tg3_phy_toggle_auxctl_smdsp(tp, true); in tg3_phy_reset_5703_4_5()
2582 tg3_phydsp_write(tp, 0x8005, 0x0800); in tg3_phy_reset_5703_4_5()
2584 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); in tg3_phy_reset_5703_4_5()
2589 err = tg3_phy_reset_chanpat(tp); in tg3_phy_reset_5703_4_5()
2593 tg3_phydsp_write(tp, 0x8005, 0x0000); in tg3_phy_reset_5703_4_5()
2595 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); in tg3_phy_reset_5703_4_5()
2596 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); in tg3_phy_reset_5703_4_5()
2598 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset_5703_4_5()
2600 tg3_writephy(tp, MII_CTRL1000, phy9_orig); in tg3_phy_reset_5703_4_5()
2602 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32); in tg3_phy_reset_5703_4_5()
2607 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2612 static void tg3_carrier_off(struct tg3 *tp) in tg3_carrier_off() argument
2614 netif_carrier_off(tp->dev); in tg3_carrier_off()
2615 tp->link_up = false; in tg3_carrier_off()
2618 static void tg3_warn_mgmt_link_flap(struct tg3 *tp) in tg3_warn_mgmt_link_flap() argument
2620 if (tg3_flag(tp, ENABLE_ASF)) in tg3_warn_mgmt_link_flap()
2621 netdev_warn(tp->dev, in tg3_warn_mgmt_link_flap()
2628 static int tg3_phy_reset(struct tg3 *tp) in tg3_phy_reset() argument
2633 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_phy_reset()
2638 err = tg3_readphy(tp, MII_BMSR, &val); in tg3_phy_reset()
2639 err |= tg3_readphy(tp, MII_BMSR, &val); in tg3_phy_reset()
2643 if (netif_running(tp->dev) && tp->link_up) { in tg3_phy_reset()
2644 netif_carrier_off(tp->dev); in tg3_phy_reset()
2645 tg3_link_report(tp); in tg3_phy_reset()
2648 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_phy_reset()
2649 tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_phy_reset()
2650 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_phy_reset()
2651 err = tg3_phy_reset_5703_4_5(tp); in tg3_phy_reset()
2658 if (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_phy_reset()
2659 tg3_chip_rev(tp) != CHIPREV_5784_AX) { in tg3_phy_reset()
2666 err = tg3_bmcr_reset(tp); in tg3_phy_reset()
2672 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); in tg3_phy_reset()
2677 if (tg3_chip_rev(tp) == CHIPREV_5784_AX || in tg3_phy_reset()
2678 tg3_chip_rev(tp) == CHIPREV_5761_AX) { in tg3_phy_reset()
2688 if (tg3_flag(tp, 5717_PLUS) && in tg3_phy_reset()
2689 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) in tg3_phy_reset()
2692 tg3_phy_apply_otp(tp); in tg3_phy_reset()
2694 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_phy_reset()
2695 tg3_phy_toggle_apd(tp, true); in tg3_phy_reset()
2697 tg3_phy_toggle_apd(tp, false); in tg3_phy_reset()
2700 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && in tg3_phy_reset()
2701 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2702 tg3_phydsp_write(tp, 0x201f, 0x2aaa); in tg3_phy_reset()
2703 tg3_phydsp_write(tp, 0x000a, 0x0323); in tg3_phy_reset()
2704 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2707 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { in tg3_phy_reset()
2708 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2709 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2712 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { in tg3_phy_reset()
2713 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2714 tg3_phydsp_write(tp, 0x000a, 0x310b); in tg3_phy_reset()
2715 tg3_phydsp_write(tp, 0x201f, 0x9506); in tg3_phy_reset()
2716 tg3_phydsp_write(tp, 0x401f, 0x14e2); in tg3_phy_reset()
2717 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2719 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { in tg3_phy_reset()
2720 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2721 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); in tg3_phy_reset()
2722 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { in tg3_phy_reset()
2723 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); in tg3_phy_reset()
2724 tg3_writephy(tp, MII_TG3_TEST1, in tg3_phy_reset()
2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); in tg3_phy_reset()
2729 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2735 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_reset()
2737 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); in tg3_phy_reset()
2738 } else if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_phy_reset()
2740 err = tg3_phy_auxctl_read(tp, in tg3_phy_reset()
2743 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, in tg3_phy_reset()
2750 if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_phy_reset()
2751 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) in tg3_phy_reset()
2752 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_reset()
2756 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_phy_reset()
2758 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); in tg3_phy_reset()
2761 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0) in tg3_phy_reset()
2762 tg3_phydsp_write(tp, 0xffb, 0x4000); in tg3_phy_reset()
2764 tg3_phy_toggle_automdix(tp, true); in tg3_phy_reset()
2765 tg3_phy_set_wirespeed(tp); in tg3_phy_reset()
2785 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat) in tg3_set_function_status() argument
2789 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_function_status()
2790 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_set_function_status()
2791 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG); in tg3_set_function_status()
2795 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; in tg3_set_function_status()
2799 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_function_status()
2800 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_set_function_status()
2801 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status); in tg3_set_function_status()
2808 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp) in tg3_pwrsrc_switch_to_vmain() argument
2810 if (!tg3_flag(tp, IS_NIC)) in tg3_pwrsrc_switch_to_vmain()
2813 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_pwrsrc_switch_to_vmain()
2814 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_pwrsrc_switch_to_vmain()
2815 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_pwrsrc_switch_to_vmain()
2816 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) in tg3_pwrsrc_switch_to_vmain()
2819 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES); in tg3_pwrsrc_switch_to_vmain()
2821 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2824 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); in tg3_pwrsrc_switch_to_vmain()
2826 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2833 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp) in tg3_pwrsrc_die_with_vmain() argument
2837 if (!tg3_flag(tp, IS_NIC) || in tg3_pwrsrc_die_with_vmain()
2838 tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_pwrsrc_die_with_vmain()
2839 tg3_asic_rev(tp) == ASIC_REV_5701) in tg3_pwrsrc_die_with_vmain()
2842 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; in tg3_pwrsrc_die_with_vmain()
2857 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) in tg3_pwrsrc_switch_to_vaux() argument
2859 if (!tg3_flag(tp, IS_NIC)) in tg3_pwrsrc_switch_to_vaux()
2862 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_pwrsrc_switch_to_vaux()
2863 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_pwrsrc_switch_to_vaux()
2864 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2871 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_pwrsrc_switch_to_vaux()
2872 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_pwrsrc_switch_to_vaux()
2879 tp->grc_local_ctrl; in tg3_pwrsrc_switch_to_vaux()
2895 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_pwrsrc_switch_to_vaux()
2897 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2903 no_gpio2 = tp->nic_sram_data_cfg & in tg3_pwrsrc_switch_to_vaux()
2916 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2922 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2928 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2934 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable) in tg3_frob_aux_power_5717() argument
2939 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) in tg3_frob_aux_power_5717()
2942 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable) in tg3_frob_aux_power_5717()
2945 msg = tg3_set_function_status(tp, msg); in tg3_frob_aux_power_5717()
2951 tg3_pwrsrc_switch_to_vaux(tp); in tg3_frob_aux_power_5717()
2953 tg3_pwrsrc_die_with_vmain(tp); in tg3_frob_aux_power_5717()
2956 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); in tg3_frob_aux_power_5717()
2959 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol) in tg3_frob_aux_power() argument
2964 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS)) in tg3_frob_aux_power()
2967 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_frob_aux_power()
2968 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_frob_aux_power()
2969 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_frob_aux_power()
2970 tg3_frob_aux_power_5717(tp, include_wol ? in tg3_frob_aux_power()
2971 tg3_flag(tp, WOL_ENABLE) != 0 : 0); in tg3_frob_aux_power()
2975 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { in tg3_frob_aux_power()
2978 dev_peer = pci_get_drvdata(tp->pdev_peer); in tg3_frob_aux_power()
2993 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) || in tg3_frob_aux_power()
2994 tg3_flag(tp, ENABLE_ASF)) in tg3_frob_aux_power()
2998 tg3_pwrsrc_switch_to_vaux(tp); in tg3_frob_aux_power()
3000 tg3_pwrsrc_die_with_vmain(tp); in tg3_frob_aux_power()
3003 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) in tg3_5700_link_polarity() argument
3005 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) in tg3_5700_link_polarity()
3007 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { in tg3_5700_link_polarity()
3016 static bool tg3_phy_power_bug(struct tg3 *tp) in tg3_phy_power_bug() argument
3018 switch (tg3_asic_rev(tp)) { in tg3_phy_power_bug()
3023 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_phy_power_bug()
3027 if (!tp->pci_fn) in tg3_phy_power_bug()
3032 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_phy_power_bug()
3033 !tp->pci_fn) in tg3_phy_power_bug()
3041 static bool tg3_phy_led_bug(struct tg3 *tp) in tg3_phy_led_bug() argument
3043 switch (tg3_asic_rev(tp)) { in tg3_phy_led_bug()
3046 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_led_bug()
3047 !tp->pci_fn) in tg3_phy_led_bug()
3055 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) in tg3_power_down_phy() argument
3059 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) in tg3_power_down_phy()
3062 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_power_down_phy()
3063 if (tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_power_down_phy()
3075 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_phy()
3076 tg3_bmcr_reset(tp); in tg3_power_down_phy()
3081 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_power_down_phy()
3083 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { in tg3_power_down_phy()
3086 tg3_writephy(tp, MII_ADVERTISE, 0); in tg3_power_down_phy()
3087 tg3_writephy(tp, MII_BMCR, in tg3_power_down_phy()
3090 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_power_down_phy()
3092 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { in tg3_power_down_phy()
3094 tg3_writephy(tp, in tg3_power_down_phy()
3098 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_power_down_phy()
3102 if (!tg3_phy_led_bug(tp)) in tg3_power_down_phy()
3103 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_power_down_phy()
3109 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); in tg3_power_down_phy()
3115 if (tg3_phy_power_bug(tp)) in tg3_power_down_phy()
3118 if (tg3_chip_rev(tp) == CHIPREV_5784_AX || in tg3_power_down_phy()
3119 tg3_chip_rev(tp) == CHIPREV_5761_AX) { in tg3_power_down_phy()
3126 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); in tg3_power_down_phy()
3130 static int tg3_nvram_lock(struct tg3 *tp) in tg3_nvram_lock() argument
3132 if (tg3_flag(tp, NVRAM)) { in tg3_nvram_lock()
3135 if (tp->nvram_lock_cnt == 0) { in tg3_nvram_lock()
3147 tp->nvram_lock_cnt++; in tg3_nvram_lock()
3153 static void tg3_nvram_unlock(struct tg3 *tp) in tg3_nvram_unlock() argument
3155 if (tg3_flag(tp, NVRAM)) { in tg3_nvram_unlock()
3156 if (tp->nvram_lock_cnt > 0) in tg3_nvram_unlock()
3157 tp->nvram_lock_cnt--; in tg3_nvram_unlock()
3158 if (tp->nvram_lock_cnt == 0) in tg3_nvram_unlock()
3164 static void tg3_enable_nvram_access(struct tg3 *tp) in tg3_enable_nvram_access() argument
3166 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { in tg3_enable_nvram_access()
3174 static void tg3_disable_nvram_access(struct tg3 *tp) in tg3_disable_nvram_access() argument
3176 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { in tg3_disable_nvram_access()
3183 static int tg3_nvram_read_using_eeprom(struct tg3 *tp, in tg3_nvram_read_using_eeprom() argument
3225 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) in tg3_nvram_exec_cmd() argument
3244 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) in tg3_nvram_phys_addr() argument
3246 if (tg3_flag(tp, NVRAM) && in tg3_nvram_phys_addr()
3247 tg3_flag(tp, NVRAM_BUFFERED) && in tg3_nvram_phys_addr()
3248 tg3_flag(tp, FLASH) && in tg3_nvram_phys_addr()
3249 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && in tg3_nvram_phys_addr()
3250 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_phys_addr()
3252 addr = ((addr / tp->nvram_pagesize) << in tg3_nvram_phys_addr()
3254 (addr % tp->nvram_pagesize); in tg3_nvram_phys_addr()
3259 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) in tg3_nvram_logical_addr() argument
3261 if (tg3_flag(tp, NVRAM) && in tg3_nvram_logical_addr()
3262 tg3_flag(tp, NVRAM_BUFFERED) && in tg3_nvram_logical_addr()
3263 tg3_flag(tp, FLASH) && in tg3_nvram_logical_addr()
3264 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && in tg3_nvram_logical_addr()
3265 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_logical_addr()
3268 tp->nvram_pagesize) + in tg3_nvram_logical_addr()
3280 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) in tg3_nvram_read() argument
3284 if (!tg3_flag(tp, NVRAM)) in tg3_nvram_read()
3285 return tg3_nvram_read_using_eeprom(tp, offset, val); in tg3_nvram_read()
3287 offset = tg3_nvram_phys_addr(tp, offset); in tg3_nvram_read()
3292 ret = tg3_nvram_lock(tp); in tg3_nvram_read()
3296 tg3_enable_nvram_access(tp); in tg3_nvram_read()
3299 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | in tg3_nvram_read()
3305 tg3_disable_nvram_access(tp); in tg3_nvram_read()
3307 tg3_nvram_unlock(tp); in tg3_nvram_read()
3313 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) in tg3_nvram_read_be32() argument
3316 int res = tg3_nvram_read(tp, offset, &v); in tg3_nvram_read_be32()
3322 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, in tg3_nvram_write_block_using_eeprom() argument
3372 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, in tg3_nvram_write_block_unbuffered() argument
3376 u32 pagesize = tp->nvram_pagesize; in tg3_nvram_write_block_unbuffered()
3392 ret = tg3_nvram_read_be32(tp, phy_addr + j, in tg3_nvram_write_block_unbuffered()
3411 tg3_enable_nvram_access(tp); in tg3_nvram_write_block_unbuffered()
3419 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3428 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3434 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3454 ret = tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_unbuffered()
3463 tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_unbuffered()
3471 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, in tg3_nvram_write_block_buffered() argument
3483 page_off = offset % tp->nvram_pagesize; in tg3_nvram_write_block_buffered()
3485 phy_addr = tg3_nvram_phys_addr(tp, offset); in tg3_nvram_write_block_buffered()
3491 if (page_off == (tp->nvram_pagesize - 4)) in tg3_nvram_write_block_buffered()
3498 !tg3_flag(tp, FLASH) || in tg3_nvram_write_block_buffered()
3499 !tg3_flag(tp, 57765_PLUS)) in tg3_nvram_write_block_buffered()
3502 if (tg3_asic_rev(tp) != ASIC_REV_5752 && in tg3_nvram_write_block_buffered()
3503 !tg3_flag(tp, 5755_PLUS) && in tg3_nvram_write_block_buffered()
3504 (tp->nvram_jedecnum == JEDEC_ST) && in tg3_nvram_write_block_buffered()
3509 ret = tg3_nvram_exec_cmd(tp, cmd); in tg3_nvram_write_block_buffered()
3513 if (!tg3_flag(tp, FLASH)) { in tg3_nvram_write_block_buffered()
3518 ret = tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_buffered()
3526 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) in tg3_nvram_write_block() argument
3530 if (tg3_flag(tp, EEPROM_WRITE_PROT)) { in tg3_nvram_write_block()
3531 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & in tg3_nvram_write_block()
3536 if (!tg3_flag(tp, NVRAM)) { in tg3_nvram_write_block()
3537 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); in tg3_nvram_write_block()
3541 ret = tg3_nvram_lock(tp); in tg3_nvram_write_block()
3545 tg3_enable_nvram_access(tp); in tg3_nvram_write_block()
3546 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) in tg3_nvram_write_block()
3552 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) { in tg3_nvram_write_block()
3553 ret = tg3_nvram_write_block_buffered(tp, offset, len, in tg3_nvram_write_block()
3556 ret = tg3_nvram_write_block_unbuffered(tp, offset, len, in tg3_nvram_write_block()
3563 tg3_disable_nvram_access(tp); in tg3_nvram_write_block()
3564 tg3_nvram_unlock(tp); in tg3_nvram_write_block()
3567 if (tg3_flag(tp, EEPROM_WRITE_PROT)) { in tg3_nvram_write_block()
3568 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_nvram_write_block()
3581 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base) in tg3_pause_cpu() argument
3591 if (pci_channel_offline(tp->pdev)) in tg3_pause_cpu()
3599 static int tg3_rxcpu_pause(struct tg3 *tp) in tg3_rxcpu_pause() argument
3601 int rc = tg3_pause_cpu(tp, RX_CPU_BASE); in tg3_rxcpu_pause()
3611 static int tg3_txcpu_pause(struct tg3 *tp) in tg3_txcpu_pause() argument
3613 return tg3_pause_cpu(tp, TX_CPU_BASE); in tg3_txcpu_pause()
3617 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base) in tg3_resume_cpu() argument
3624 static void tg3_rxcpu_resume(struct tg3 *tp) in tg3_rxcpu_resume() argument
3626 tg3_resume_cpu(tp, RX_CPU_BASE); in tg3_rxcpu_resume()
3630 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base) in tg3_halt_cpu() argument
3634 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); in tg3_halt_cpu()
3636 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_halt_cpu()
3643 rc = tg3_rxcpu_pause(tp); in tg3_halt_cpu()
3649 if (tg3_flag(tp, IS_SSB_CORE)) in tg3_halt_cpu()
3652 rc = tg3_txcpu_pause(tp); in tg3_halt_cpu()
3656 netdev_err(tp->dev, "%s timed out, %s CPU\n", in tg3_halt_cpu()
3662 if (tg3_flag(tp, NVRAM)) in tg3_halt_cpu()
3667 static int tg3_fw_data_len(struct tg3 *tp, in tg3_fw_data_len() argument
3686 if (tp->fw_len == 0xffffffff) in tg3_fw_data_len()
3689 fw_len = tp->fw->size; in tg3_fw_data_len()
3695 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, in tg3_load_firmware_cpu() argument
3701 int total_len = tp->fw->size; in tg3_load_firmware_cpu()
3703 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { in tg3_load_firmware_cpu()
3704 netdev_err(tp->dev, in tg3_load_firmware_cpu()
3710 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766) in tg3_load_firmware_cpu()
3715 if (tg3_asic_rev(tp) != ASIC_REV_57766) { in tg3_load_firmware_cpu()
3719 int lock_err = tg3_nvram_lock(tp); in tg3_load_firmware_cpu()
3720 err = tg3_halt_cpu(tp, cpu_base); in tg3_load_firmware_cpu()
3722 tg3_nvram_unlock(tp); in tg3_load_firmware_cpu()
3727 write_op(tp, cpu_scratch_base + i, 0); in tg3_load_firmware_cpu()
3741 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++) in tg3_load_firmware_cpu()
3742 write_op(tp, cpu_scratch_base + in tg3_load_firmware_cpu()
3761 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc) in tg3_pause_cpu_and_set_pc() argument
3782 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) in tg3_load_5701_a0_firmware_fix() argument
3787 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_5701_a0_firmware_fix()
3795 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3801 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3808 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3811 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " in tg3_load_5701_a0_firmware_fix()
3818 tg3_rxcpu_resume(tp); in tg3_load_5701_a0_firmware_fix()
3823 static int tg3_validate_rxcpu_state(struct tg3 *tp) in tg3_validate_rxcpu_state() argument
3840 netdev_err(tp->dev, "Boot code not ready for service patches\n"); in tg3_validate_rxcpu_state()
3844 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE); in tg3_validate_rxcpu_state()
3846 netdev_warn(tp->dev, in tg3_validate_rxcpu_state()
3855 static void tg3_load_57766_firmware(struct tg3 *tp) in tg3_load_57766_firmware() argument
3859 if (!tg3_flag(tp, NO_NVRAM)) in tg3_load_57766_firmware()
3862 if (tg3_validate_rxcpu_state(tp)) in tg3_load_57766_firmware()
3865 if (!tp->fw) in tg3_load_57766_firmware()
3882 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_57766_firmware()
3886 if (tg3_rxcpu_pause(tp)) in tg3_load_57766_firmware()
3890 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr); in tg3_load_57766_firmware()
3892 tg3_rxcpu_resume(tp); in tg3_load_57766_firmware()
3896 static int tg3_load_tso_firmware(struct tg3 *tp) in tg3_load_tso_firmware() argument
3902 if (!tg3_flag(tp, FW_TSO)) in tg3_load_tso_firmware()
3905 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_tso_firmware()
3913 cpu_scratch_size = tp->fw_len; in tg3_load_tso_firmware()
3915 if (tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_load_tso_firmware()
3924 err = tg3_load_firmware_cpu(tp, cpu_base, in tg3_load_tso_firmware()
3931 err = tg3_pause_cpu_and_set_pc(tp, cpu_base, in tg3_load_tso_firmware()
3934 netdev_err(tp->dev, in tg3_load_tso_firmware()
3941 tg3_resume_cpu(tp, cpu_base); in tg3_load_tso_firmware()
3946 static void __tg3_set_one_mac_addr(struct tg3 *tp, const u8 *mac_addr, in __tg3_set_one_mac_addr() argument
3966 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1) in __tg3_set_mac_addr() argument
3974 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3977 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in __tg3_set_mac_addr()
3978 tg3_asic_rev(tp) == ASIC_REV_5704) { in __tg3_set_mac_addr()
3980 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3983 addr_high = (tp->dev->dev_addr[0] + in __tg3_set_mac_addr()
3984 tp->dev->dev_addr[1] + in __tg3_set_mac_addr()
3985 tp->dev->dev_addr[2] + in __tg3_set_mac_addr()
3986 tp->dev->dev_addr[3] + in __tg3_set_mac_addr()
3987 tp->dev->dev_addr[4] + in __tg3_set_mac_addr()
3988 tp->dev->dev_addr[5]) & in __tg3_set_mac_addr()
3993 static void tg3_enable_register_access(struct tg3 *tp) in tg3_enable_register_access() argument
3999 pci_write_config_dword(tp->pdev, in tg3_enable_register_access()
4000 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); in tg3_enable_register_access()
4003 static int tg3_power_up(struct tg3 *tp) in tg3_power_up() argument
4007 tg3_enable_register_access(tp); in tg3_power_up()
4009 err = pci_set_power_state(tp->pdev, PCI_D0); in tg3_power_up()
4012 tg3_pwrsrc_switch_to_vmain(tp); in tg3_power_up()
4014 netdev_err(tp->dev, "Transition to D0 failed\n"); in tg3_power_up()
4022 static void tg3_power_down_prepare(struct tg3 *tp) in tg3_power_down_prepare() argument
4027 tg3_enable_register_access(tp); in tg3_power_down_prepare()
4030 if (tg3_flag(tp, CLKREQ_BUG)) in tg3_power_down_prepare()
4031 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_power_down_prepare()
4038 device_should_wake = device_may_wakeup(&tp->pdev->dev) && in tg3_power_down_prepare()
4039 tg3_flag(tp, WOL_ENABLE); in tg3_power_down_prepare()
4041 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_power_down_prepare()
4043 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && in tg3_power_down_prepare()
4044 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_power_down_prepare()
4049 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_power_down_prepare()
4051 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4053 tp->link_config.speed = phydev->speed; in tg3_power_down_prepare()
4054 tp->link_config.duplex = phydev->duplex; in tg3_power_down_prepare()
4055 tp->link_config.autoneg = phydev->autoneg; in tg3_power_down_prepare()
4057 &tp->link_config.advertising, in tg3_power_down_prepare()
4068 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) { in tg3_power_down_prepare()
4069 if (tg3_flag(tp, WOL_SPEED_100MB)) { in tg3_power_down_prepare()
4097 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) in tg3_power_down_prepare()
4098 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4100 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_power_down_prepare()
4101 tg3_setup_phy(tp, false); in tg3_power_down_prepare()
4104 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_prepare()
4109 } else if (!tg3_flag(tp, ENABLE_ASF)) { in tg3_power_down_prepare()
4114 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); in tg3_power_down_prepare()
4120 if (tg3_flag(tp, WOL_CAP)) in tg3_power_down_prepare()
4121 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | in tg3_power_down_prepare()
4129 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_power_down_prepare()
4131 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_power_down_prepare()
4132 tg3_phy_auxctl_write(tp, in tg3_power_down_prepare()
4140 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_power_down_prepare()
4142 else if (tp->phy_flags & in tg3_power_down_prepare()
4144 if (tp->link_config.active_speed == SPEED_1000) in tg3_power_down_prepare()
4151 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; in tg3_power_down_prepare()
4152 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_power_down_prepare()
4153 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? in tg3_power_down_prepare()
4155 if (tg3_5700_link_polarity(tp, speed)) in tg3_power_down_prepare()
4164 if (!tg3_flag(tp, 5750_PLUS)) in tg3_power_down_prepare()
4165 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_power_down_prepare()
4168 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) && in tg3_power_down_prepare()
4169 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE))) in tg3_power_down_prepare()
4172 if (tg3_flag(tp, ENABLE_APE)) in tg3_power_down_prepare()
4184 if (!tg3_flag(tp, WOL_SPEED_100MB) && in tg3_power_down_prepare()
4185 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4186 tg3_asic_rev(tp) == ASIC_REV_5701)) { in tg3_power_down_prepare()
4189 base_val = tp->pci_clock_ctrl; in tg3_power_down_prepare()
4195 } else if (tg3_flag(tp, 5780_CLASS) || in tg3_power_down_prepare()
4196 tg3_flag(tp, CPMU_PRESENT) || in tg3_power_down_prepare()
4197 tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_prepare()
4199 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { in tg3_power_down_prepare()
4202 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4203 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_power_down_prepare()
4208 } else if (tg3_flag(tp, 5705_PLUS)) { in tg3_power_down_prepare()
4216 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, in tg3_power_down_prepare()
4219 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, in tg3_power_down_prepare()
4222 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_power_down_prepare()
4225 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4226 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_power_down_prepare()
4235 tp->pci_clock_ctrl | newbits3, 40); in tg3_power_down_prepare()
4239 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF)) in tg3_power_down_prepare()
4240 tg3_power_down_phy(tp, do_low_power); in tg3_power_down_prepare()
4242 tg3_frob_aux_power(tp, true); in tg3_power_down_prepare()
4245 if ((!tg3_flag(tp, IS_SSB_CORE)) && in tg3_power_down_prepare()
4246 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) || in tg3_power_down_prepare()
4247 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) { in tg3_power_down_prepare()
4252 if (!tg3_flag(tp, ENABLE_ASF)) { in tg3_power_down_prepare()
4255 err = tg3_nvram_lock(tp); in tg3_power_down_prepare()
4256 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_power_down_prepare()
4258 tg3_nvram_unlock(tp); in tg3_power_down_prepare()
4262 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); in tg3_power_down_prepare()
4264 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN); in tg3_power_down_prepare()
4269 static void tg3_power_down(struct tg3 *tp) in tg3_power_down() argument
4271 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); in tg3_power_down()
4272 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_power_down()
4275 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex) in tg3_aux_stat_to_speed_duplex() argument
4309 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_aux_stat_to_speed_duplex()
4322 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) in tg3_phy_autoneg_cfg() argument
4331 err = tg3_writephy(tp, MII_ADVERTISE, new_adv); in tg3_phy_autoneg_cfg()
4335 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_autoneg_cfg()
4338 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_phy_autoneg_cfg()
4339 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) in tg3_phy_autoneg_cfg()
4342 err = tg3_writephy(tp, MII_CTRL1000, new_adv); in tg3_phy_autoneg_cfg()
4347 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_autoneg_cfg()
4353 err = tg3_phy_toggle_auxctl_smdsp(tp, true); in tg3_phy_autoneg_cfg()
4357 if (!tp->eee.eee_enabled) in tg3_phy_autoneg_cfg()
4362 mii_eee_cap1_mod_linkmode_t(tp->eee.advertised, val); in tg3_phy_autoneg_cfg()
4363 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); in tg3_phy_autoneg_cfg()
4367 switch (tg3_asic_rev(tp)) { in tg3_phy_autoneg_cfg()
4377 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); in tg3_phy_autoneg_cfg()
4381 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) in tg3_phy_autoneg_cfg()
4382 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | in tg3_phy_autoneg_cfg()
4386 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_autoneg_cfg()
4395 static void tg3_phy_copper_begin(struct tg3 *tp) in tg3_phy_copper_begin() argument
4397 if (tp->link_config.autoneg == AUTONEG_ENABLE || in tg3_phy_copper_begin()
4398 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_phy_copper_begin()
4401 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4402 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4405 if (tg3_flag(tp, WOL_SPEED_100MB)) in tg3_phy_copper_begin()
4408 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) { in tg3_phy_copper_begin()
4409 if (!(tp->phy_flags & in tg3_phy_copper_begin()
4417 adv = tp->link_config.advertising; in tg3_phy_copper_begin()
4418 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_phy_copper_begin()
4422 fc = tp->link_config.flowctrl; in tg3_phy_copper_begin()
4425 tg3_phy_autoneg_cfg(tp, adv, fc); in tg3_phy_copper_begin()
4427 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4428 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4436 tg3_writephy(tp, MII_BMCR, in tg3_phy_copper_begin()
4442 tp->link_config.active_speed = tp->link_config.speed; in tg3_phy_copper_begin()
4443 tp->link_config.active_duplex = tp->link_config.duplex; in tg3_phy_copper_begin()
4445 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_phy_copper_begin()
4450 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL); in tg3_phy_copper_begin()
4454 switch (tp->link_config.speed) { in tg3_phy_copper_begin()
4468 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_phy_copper_begin()
4471 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && in tg3_phy_copper_begin()
4473 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); in tg3_phy_copper_begin()
4478 if (tg3_readphy(tp, MII_BMSR, &tmp) || in tg3_phy_copper_begin()
4479 tg3_readphy(tp, MII_BMSR, &tmp)) in tg3_phy_copper_begin()
4486 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_copper_begin()
4492 static int tg3_phy_pull_config(struct tg3 *tp) in tg3_phy_pull_config() argument
4497 err = tg3_readphy(tp, MII_BMCR, &val); in tg3_phy_pull_config()
4502 tp->link_config.autoneg = AUTONEG_DISABLE; in tg3_phy_pull_config()
4503 tp->link_config.advertising = 0; in tg3_phy_pull_config()
4504 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_phy_pull_config()
4510 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4513 tp->link_config.speed = SPEED_10; in tg3_phy_pull_config()
4516 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4519 tp->link_config.speed = SPEED_100; in tg3_phy_pull_config()
4522 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4523 tp->link_config.speed = SPEED_1000; in tg3_phy_pull_config()
4532 tp->link_config.duplex = DUPLEX_FULL; in tg3_phy_pull_config()
4534 tp->link_config.duplex = DUPLEX_HALF; in tg3_phy_pull_config()
4536 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; in tg3_phy_pull_config()
4542 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_pull_config()
4543 tp->link_config.advertising = ADVERTISED_Autoneg; in tg3_phy_pull_config()
4544 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_phy_pull_config()
4546 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4549 err = tg3_readphy(tp, MII_ADVERTISE, &val); in tg3_phy_pull_config()
4554 tp->link_config.advertising |= adv | ADVERTISED_TP; in tg3_phy_pull_config()
4556 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val); in tg3_phy_pull_config()
4558 tp->link_config.advertising |= ADVERTISED_FIBRE; in tg3_phy_pull_config()
4561 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4564 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4565 err = tg3_readphy(tp, MII_CTRL1000, &val); in tg3_phy_pull_config()
4571 err = tg3_readphy(tp, MII_ADVERTISE, &val); in tg3_phy_pull_config()
4576 tp->link_config.flowctrl = adv; in tg3_phy_pull_config()
4582 tp->link_config.advertising |= adv; in tg3_phy_pull_config()
4589 static int tg3_init_5401phy_dsp(struct tg3 *tp) in tg3_init_5401phy_dsp() argument
4595 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); in tg3_init_5401phy_dsp()
4597 err |= tg3_phydsp_write(tp, 0x0012, 0x1804); in tg3_init_5401phy_dsp()
4598 err |= tg3_phydsp_write(tp, 0x0013, 0x1204); in tg3_init_5401phy_dsp()
4599 err |= tg3_phydsp_write(tp, 0x8006, 0x0132); in tg3_init_5401phy_dsp()
4600 err |= tg3_phydsp_write(tp, 0x8006, 0x0232); in tg3_init_5401phy_dsp()
4601 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); in tg3_init_5401phy_dsp()
4608 static bool tg3_phy_eee_config_ok(struct tg3 *tp) in tg3_phy_eee_config_ok() argument
4612 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_config_ok()
4615 tg3_eee_pull_config(tp, &eee); in tg3_phy_eee_config_ok()
4617 if (tp->eee.eee_enabled) { in tg3_phy_eee_config_ok()
4618 if (!linkmode_equal(tp->eee.advertised, eee.advertised) || in tg3_phy_eee_config_ok()
4619 tp->eee.tx_lpi_timer != eee.tx_lpi_timer || in tg3_phy_eee_config_ok()
4620 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled) in tg3_phy_eee_config_ok()
4631 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv) in tg3_phy_copper_an_config_ok() argument
4635 advertising = tp->link_config.advertising; in tg3_phy_copper_an_config_ok()
4639 if (tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_phy_copper_an_config_ok()
4640 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); in tg3_phy_copper_an_config_ok()
4644 if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) in tg3_phy_copper_an_config_ok()
4650 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_an_config_ok()
4655 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl)) in tg3_phy_copper_an_config_ok()
4659 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_phy_copper_an_config_ok()
4660 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) { in tg3_phy_copper_an_config_ok()
4675 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv) in tg3_phy_copper_fetch_rmtadv() argument
4679 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_fetch_rmtadv()
4682 if (tg3_readphy(tp, MII_STAT1000, &val)) in tg3_phy_copper_fetch_rmtadv()
4688 if (tg3_readphy(tp, MII_LPA, rmtadv)) in tg3_phy_copper_fetch_rmtadv()
4692 tp->link_config.rmt_adv = lpeth; in tg3_phy_copper_fetch_rmtadv()
4697 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up) in tg3_test_and_report_link_chg() argument
4699 if (curr_link_up != tp->link_up) { in tg3_test_and_report_link_chg()
4701 netif_carrier_on(tp->dev); in tg3_test_and_report_link_chg()
4703 netif_carrier_off(tp->dev); in tg3_test_and_report_link_chg()
4704 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_test_and_report_link_chg()
4705 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_test_and_report_link_chg()
4708 tg3_link_report(tp); in tg3_test_and_report_link_chg()
4715 static void tg3_clear_mac_status(struct tg3 *tp) in tg3_clear_mac_status() argument
4727 static void tg3_setup_eee(struct tg3 *tp) in tg3_setup_eee() argument
4733 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) in tg3_setup_eee()
4742 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) | in tg3_setup_eee()
4746 if (tg3_asic_rev(tp) != ASIC_REV_5717) in tg3_setup_eee()
4749 if (tg3_flag(tp, ENABLE_APE)) in tg3_setup_eee()
4752 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0); in tg3_setup_eee()
4756 (tp->eee.tx_lpi_timer & 0xffff)); in tg3_setup_eee()
4763 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset) in tg3_setup_copper_phy() argument
4772 tg3_clear_mac_status(tp); in tg3_setup_copper_phy()
4774 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_setup_copper_phy()
4776 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in tg3_setup_copper_phy()
4780 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); in tg3_setup_copper_phy()
4785 if ((tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_setup_copper_phy()
4786 tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_setup_copper_phy()
4787 tg3_asic_rev(tp) == ASIC_REV_5705) && in tg3_setup_copper_phy()
4788 tp->link_up) { in tg3_setup_copper_phy()
4789 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4790 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4795 tg3_phy_reset(tp); in tg3_setup_copper_phy()
4797 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_setup_copper_phy()
4798 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4799 if (tg3_readphy(tp, MII_BMSR, &bmsr) || in tg3_setup_copper_phy()
4800 !tg3_flag(tp, INIT_COMPLETE)) in tg3_setup_copper_phy()
4804 err = tg3_init_5401phy_dsp(tp); in tg3_setup_copper_phy()
4808 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4811 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4818 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == in tg3_setup_copper_phy()
4821 tp->link_config.active_speed == SPEED_1000) { in tg3_setup_copper_phy()
4822 err = tg3_phy_reset(tp); in tg3_setup_copper_phy()
4824 err = tg3_init_5401phy_dsp(tp); in tg3_setup_copper_phy()
4829 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_setup_copper_phy()
4830 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) { in tg3_setup_copper_phy()
4832 tg3_writephy(tp, 0x15, 0x0a75); in tg3_setup_copper_phy()
4833 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4834 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_setup_copper_phy()
4835 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4839 tg3_readphy(tp, MII_TG3_ISTAT, &val); in tg3_setup_copper_phy()
4840 tg3_readphy(tp, MII_TG3_ISTAT, &val); in tg3_setup_copper_phy()
4842 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) in tg3_setup_copper_phy()
4843 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); in tg3_setup_copper_phy()
4844 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_setup_copper_phy()
4845 tg3_writephy(tp, MII_TG3_IMASK, ~0); in tg3_setup_copper_phy()
4847 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_setup_copper_phy()
4848 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_setup_copper_phy()
4849 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) in tg3_setup_copper_phy()
4850 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_setup_copper_phy()
4853 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); in tg3_setup_copper_phy()
4859 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4860 tp->link_config.rmt_adv = 0; in tg3_setup_copper_phy()
4862 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { in tg3_setup_copper_phy()
4863 err = tg3_phy_auxctl_read(tp, in tg3_setup_copper_phy()
4867 tg3_phy_auxctl_write(tp, in tg3_setup_copper_phy()
4876 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4877 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4886 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); in tg3_setup_copper_phy()
4889 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && in tg3_setup_copper_phy()
4894 tg3_aux_stat_to_speed_duplex(tp, aux_stat, in tg3_setup_copper_phy()
4900 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_copper_phy()
4901 if (tg3_readphy(tp, MII_BMCR, &bmcr)) in tg3_setup_copper_phy()
4911 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4912 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4914 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_copper_phy()
4915 bool eee_config_ok = tg3_phy_eee_config_ok(tp); in tg3_setup_copper_phy()
4919 tg3_phy_copper_an_config_ok(tp, &lcl_adv) && in tg3_setup_copper_phy()
4920 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv)) in tg3_setup_copper_phy()
4928 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_setup_copper_phy()
4930 tg3_setup_eee(tp); in tg3_setup_copper_phy()
4931 tg3_phy_reset(tp); in tg3_setup_copper_phy()
4935 tp->link_config.speed == current_speed && in tg3_setup_copper_phy()
4936 tp->link_config.duplex == current_duplex) { in tg3_setup_copper_phy()
4942 tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_setup_copper_phy()
4945 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_setup_copper_phy()
4953 if (!tg3_readphy(tp, reg, &val) && (val & bit)) in tg3_setup_copper_phy()
4954 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4956 tg3_setup_flow_control(tp, lcl_adv, rmt_adv); in tg3_setup_copper_phy()
4961 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_setup_copper_phy()
4962 tg3_phy_copper_begin(tp); in tg3_setup_copper_phy()
4964 if (tg3_flag(tp, ROBOSWITCH)) { in tg3_setup_copper_phy()
4969 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4970 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4973 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4974 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || in tg3_setup_copper_phy()
4975 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_setup_copper_phy()
4979 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_copper_phy()
4981 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
4982 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
4983 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
4985 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
4986 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_setup_copper_phy()
4987 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
4989 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
4994 if (tg3_flag(tp, RGMII_MODE)) { in tg3_setup_copper_phy()
4998 if (tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5000 else if (tp->link_config.active_speed == SPEED_100) in tg3_setup_copper_phy()
5003 else if (tp->link_config.active_speed == SPEED_1000) in tg3_setup_copper_phy()
5011 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5012 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_copper_phy()
5013 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5015 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_setup_copper_phy()
5017 tg3_5700_link_polarity(tp, tp->link_config.active_speed)) in tg3_setup_copper_phy()
5018 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5020 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5026 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && in tg3_setup_copper_phy()
5027 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) { in tg3_setup_copper_phy()
5028 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; in tg3_setup_copper_phy()
5029 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_setup_copper_phy()
5033 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_copper_phy()
5036 tg3_phy_eee_adjust(tp, current_link_up); in tg3_setup_copper_phy()
5038 if (tg3_flag(tp, USE_LINKCHG_REG)) { in tg3_setup_copper_phy()
5046 if (tg3_asic_rev(tp) == ASIC_REV_5700 && in tg3_setup_copper_phy()
5048 tp->link_config.active_speed == SPEED_1000 && in tg3_setup_copper_phy()
5049 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { in tg3_setup_copper_phy()
5055 tg3_write_mem(tp, in tg3_setup_copper_phy()
5061 if (tg3_flag(tp, CLKREQ_BUG)) { in tg3_setup_copper_phy()
5062 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
5063 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5064 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5067 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5071 tg3_test_and_report_link_chg(tp, current_link_up); in tg3_setup_copper_phy()
5140 static int tg3_fiber_aneg_smachine(struct tg3 *tp, in tg3_fiber_aneg_smachine() argument
5220 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5221 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5243 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_fiber_aneg_smachine()
5249 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5250 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5264 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5265 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5350 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5351 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5392 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) in fiber_autoneg() argument
5402 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; in fiber_autoneg()
5406 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); in fiber_autoneg()
5415 status = tg3_fiber_aneg_smachine(tp, &aninfo); in fiber_autoneg()
5422 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in fiber_autoneg()
5423 tw32_f(MAC_MODE, tp->mac_mode); in fiber_autoneg()
5437 static void tg3_init_bcm8002(struct tg3 *tp) in tg3_init_bcm8002() argument
5443 if (tg3_flag(tp, INIT_COMPLETE) && in tg3_init_bcm8002()
5448 tg3_writephy(tp, 0x16, 0x8007); in tg3_init_bcm8002()
5451 tg3_writephy(tp, MII_BMCR, BMCR_RESET); in tg3_init_bcm8002()
5459 tg3_writephy(tp, 0x10, 0x8411); in tg3_init_bcm8002()
5462 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5464 tg3_writephy(tp, 0x18, 0x00a0); in tg3_init_bcm8002()
5465 tg3_writephy(tp, 0x16, 0x41ff); in tg3_init_bcm8002()
5468 tg3_writephy(tp, 0x13, 0x0400); in tg3_init_bcm8002()
5470 tg3_writephy(tp, 0x13, 0x0000); in tg3_init_bcm8002()
5472 tg3_writephy(tp, 0x11, 0x0a50); in tg3_init_bcm8002()
5474 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5484 tg3_writephy(tp, 0x10, 0x8011); in tg3_init_bcm8002()
5487 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) in tg3_setup_fiber_hw_autoneg() argument
5500 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 && in tg3_setup_fiber_hw_autoneg()
5501 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) { in tg3_setup_fiber_hw_autoneg()
5513 if (tp->link_config.autoneg != AUTONEG_ENABLE) { in tg3_setup_fiber_hw_autoneg()
5528 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_hw_autoneg()
5537 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_hw_autoneg()
5544 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && in tg3_setup_fiber_hw_autoneg()
5545 tp->serdes_counter && in tg3_setup_fiber_hw_autoneg()
5549 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5560 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5561 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5581 tp->link_config.rmt_adv = in tg3_setup_fiber_hw_autoneg()
5584 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_hw_autoneg()
5586 tp->serdes_counter = 0; in tg3_setup_fiber_hw_autoneg()
5587 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5589 if (tp->serdes_counter) in tg3_setup_fiber_hw_autoneg()
5590 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5612 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_hw_autoneg()
5614 tp->phy_flags |= in tg3_setup_fiber_hw_autoneg()
5616 tp->serdes_counter = in tg3_setup_fiber_hw_autoneg()
5623 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5624 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5631 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) in tg3_setup_fiber_by_hand() argument
5638 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_by_hand()
5642 if (fiber_autoneg(tp, &txflags, &rxflags)) { in tg3_setup_fiber_by_hand()
5655 tp->link_config.rmt_adv = in tg3_setup_fiber_by_hand()
5658 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_by_hand()
5680 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_by_hand()
5685 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); in tg3_setup_fiber_by_hand()
5688 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_by_hand()
5696 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset) in tg3_setup_fiber_phy() argument
5705 orig_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5706 orig_active_speed = tp->link_config.active_speed; in tg3_setup_fiber_phy()
5707 orig_active_duplex = tp->link_config.active_duplex; in tg3_setup_fiber_phy()
5709 if (!tg3_flag(tp, HW_AUTONEG) && in tg3_setup_fiber_phy()
5710 tp->link_up && in tg3_setup_fiber_phy()
5711 tg3_flag(tp, INIT_COMPLETE)) { in tg3_setup_fiber_phy()
5727 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); in tg3_setup_fiber_phy()
5728 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; in tg3_setup_fiber_phy()
5729 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5732 if (tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_setup_fiber_phy()
5733 tg3_init_bcm8002(tp); in tg3_setup_fiber_phy()
5739 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_phy()
5742 if (tg3_flag(tp, HW_AUTONEG)) in tg3_setup_fiber_phy()
5743 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); in tg3_setup_fiber_phy()
5745 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); in tg3_setup_fiber_phy()
5747 tp->napi[0].hw_status->status = in tg3_setup_fiber_phy()
5749 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); in tg3_setup_fiber_phy()
5764 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_setup_fiber_phy()
5765 tp->serdes_counter == 0) { in tg3_setup_fiber_phy()
5766 tw32_f(MAC_MODE, (tp->mac_mode | in tg3_setup_fiber_phy()
5769 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5774 tp->link_config.active_speed = SPEED_1000; in tg3_setup_fiber_phy()
5775 tp->link_config.active_duplex = DUPLEX_FULL; in tg3_setup_fiber_phy()
5776 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5780 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_setup_fiber_phy()
5781 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_setup_fiber_phy()
5782 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5787 if (!tg3_test_and_report_link_chg(tp, current_link_up)) { in tg3_setup_fiber_phy()
5788 u32 now_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5790 orig_active_speed != tp->link_config.active_speed || in tg3_setup_fiber_phy()
5791 orig_active_duplex != tp->link_config.active_duplex) in tg3_setup_fiber_phy()
5792 tg3_link_report(tp); in tg3_setup_fiber_phy()
5798 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset) in tg3_setup_fiber_mii_phy() argument
5807 if ((tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_setup_fiber_mii_phy()
5808 tg3_asic_rev(tp) == ASIC_REV_5720) && in tg3_setup_fiber_mii_phy()
5809 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) && in tg3_setup_fiber_mii_phy()
5813 tg3_phy_reset(tp); in tg3_setup_fiber_mii_phy()
5815 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_fiber_mii_phy()
5818 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5823 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5826 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5829 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5838 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5841 tg3_clear_mac_status(tp); in tg3_setup_fiber_mii_phy()
5846 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5847 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5850 tg3_clear_mac_status(tp); in tg3_setup_fiber_mii_phy()
5853 tg3_phy_reset(tp); in tg3_setup_fiber_mii_phy()
5855 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_mii_phy()
5857 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5858 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5859 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_setup_fiber_mii_phy()
5866 err |= tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_fiber_mii_phy()
5868 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && in tg3_setup_fiber_mii_phy()
5869 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_setup_fiber_mii_phy()
5871 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_mii_phy()
5874 err |= tg3_readphy(tp, MII_ADVERTISE, &adv); in tg3_setup_fiber_mii_phy()
5880 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_mii_phy()
5881 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); in tg3_setup_fiber_mii_phy()
5884 tg3_writephy(tp, MII_ADVERTISE, newadv); in tg3_setup_fiber_mii_phy()
5886 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_setup_fiber_mii_phy()
5889 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; in tg3_setup_fiber_mii_phy()
5890 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5900 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_setup_fiber_mii_phy()
5910 if (tp->link_up) { in tg3_setup_fiber_mii_phy()
5913 err |= tg3_readphy(tp, MII_ADVERTISE, &adv); in tg3_setup_fiber_mii_phy()
5917 tg3_writephy(tp, MII_ADVERTISE, adv); in tg3_setup_fiber_mii_phy()
5918 tg3_writephy(tp, MII_BMCR, bmcr | in tg3_setup_fiber_mii_phy()
5922 tg3_carrier_off(tp); in tg3_setup_fiber_mii_phy()
5924 tg3_writephy(tp, MII_BMCR, new_bmcr); in tg3_setup_fiber_mii_phy()
5926 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5927 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5928 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_setup_fiber_mii_phy()
5934 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5952 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); in tg3_setup_fiber_mii_phy()
5953 err |= tg3_readphy(tp, MII_LPA, &remote_adv); in tg3_setup_fiber_mii_phy()
5962 tp->link_config.rmt_adv = in tg3_setup_fiber_mii_phy()
5964 } else if (!tg3_flag(tp, 5780_CLASS)) { in tg3_setup_fiber_mii_phy()
5974 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_mii_phy()
5976 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5977 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_fiber_mii_phy()
5978 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5980 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5985 tp->link_config.active_speed = current_speed; in tg3_setup_fiber_mii_phy()
5986 tp->link_config.active_duplex = current_duplex; in tg3_setup_fiber_mii_phy()
5988 tg3_test_and_report_link_chg(tp, current_link_up); in tg3_setup_fiber_mii_phy()
5992 static void tg3_serdes_parallel_detect(struct tg3 *tp) in tg3_serdes_parallel_detect() argument
5994 if (tp->serdes_counter) { in tg3_serdes_parallel_detect()
5996 tp->serdes_counter--; in tg3_serdes_parallel_detect()
6000 if (!tp->link_up && in tg3_serdes_parallel_detect()
6001 (tp->link_config.autoneg == AUTONEG_ENABLE)) { in tg3_serdes_parallel_detect()
6004 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_serdes_parallel_detect()
6009 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); in tg3_serdes_parallel_detect()
6010 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); in tg3_serdes_parallel_detect()
6013 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6015 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6016 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6026 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_serdes_parallel_detect()
6027 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6030 } else if (tp->link_up && in tg3_serdes_parallel_detect()
6031 (tp->link_config.autoneg == AUTONEG_ENABLE) && in tg3_serdes_parallel_detect()
6032 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_serdes_parallel_detect()
6036 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6038 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6043 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_serdes_parallel_detect()
6044 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); in tg3_serdes_parallel_detect()
6046 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6052 static int tg3_setup_phy(struct tg3 *tp, bool force_reset) in tg3_setup_phy() argument
6057 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_setup_phy()
6058 err = tg3_setup_fiber_phy(tp, force_reset); in tg3_setup_phy()
6059 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_setup_phy()
6060 err = tg3_setup_fiber_mii_phy(tp, force_reset); in tg3_setup_phy()
6062 err = tg3_setup_copper_phy(tp, force_reset); in tg3_setup_phy()
6064 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) { in tg3_setup_phy()
6082 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_setup_phy()
6083 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_setup_phy()
6088 if (tp->link_config.active_speed == SPEED_1000 && in tg3_setup_phy()
6089 tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_phy()
6096 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_setup_phy()
6097 if (tp->link_up) { in tg3_setup_phy()
6099 tp->coal.stats_block_coalesce_usecs); in tg3_setup_phy()
6105 if (tg3_flag(tp, ASPM_WORKAROUND)) { in tg3_setup_phy()
6107 if (!tp->link_up) in tg3_setup_phy()
6109 tp->pwrmgmt_thresh; in tg3_setup_phy()
6119 static u64 tg3_refclk_read(struct tg3 *tp, struct ptp_system_timestamp *sts) in tg3_refclk_read() argument
6132 static void tg3_refclk_write(struct tg3 *tp, u64 newval) in tg3_refclk_write() argument
6142 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6143 static inline void tg3_full_unlock(struct tg3 *tp);
6146 struct tg3 *tp = netdev_priv(dev); in tg3_get_ts_info() local
6150 if (tg3_flag(tp, PTP_CAPABLE)) { in tg3_get_ts_info()
6156 if (tp->ptp_clock) in tg3_get_ts_info()
6157 info->phc_index = ptp_clock_index(tp->ptp_clock); in tg3_get_ts_info()
6170 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_adjfine() local
6181 tg3_full_lock(tp, 0); in tg3_ptp_adjfine()
6191 tg3_full_unlock(tp); in tg3_ptp_adjfine()
6198 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_adjtime() local
6200 tg3_full_lock(tp, 0); in tg3_ptp_adjtime()
6201 tp->ptp_adjust += delta; in tg3_ptp_adjtime()
6202 tg3_full_unlock(tp); in tg3_ptp_adjtime()
6211 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_gettimex() local
6213 tg3_full_lock(tp, 0); in tg3_ptp_gettimex()
6214 ns = tg3_refclk_read(tp, sts); in tg3_ptp_gettimex()
6215 ns += tp->ptp_adjust; in tg3_ptp_gettimex()
6216 tg3_full_unlock(tp); in tg3_ptp_gettimex()
6227 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_settime() local
6231 tg3_full_lock(tp, 0); in tg3_ptp_settime()
6232 tg3_refclk_write(tp, ns); in tg3_ptp_settime()
6233 tp->ptp_adjust = 0; in tg3_ptp_settime()
6234 tg3_full_unlock(tp); in tg3_ptp_settime()
6242 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_enable() local
6255 tg3_full_lock(tp, 0); in tg3_ptp_enable()
6266 netdev_warn(tp->dev, in tg3_ptp_enable()
6273 netdev_warn(tp->dev, in tg3_ptp_enable()
6292 tg3_full_unlock(tp); in tg3_ptp_enable()
6302 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock, in tg3_hwclock_to_timestamp() argument
6307 tp->ptp_adjust); in tg3_hwclock_to_timestamp()
6310 static void tg3_read_tx_tstamp(struct tg3 *tp, u64 *hwclock) in tg3_read_tx_tstamp() argument
6318 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_ts_aux_work() local
6322 if (tp->ptp_txts_retrycnt > 2) in tg3_ptp_ts_aux_work()
6325 tg3_read_tx_tstamp(tp, &hwclock); in tg3_ptp_ts_aux_work()
6327 if (hwclock != tp->pre_tx_ts) { in tg3_ptp_ts_aux_work()
6328 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp); in tg3_ptp_ts_aux_work()
6329 skb_tstamp_tx(tp->tx_tstamp_skb, ×tamp); in tg3_ptp_ts_aux_work()
6332 tp->ptp_txts_retrycnt++; in tg3_ptp_ts_aux_work()
6335 dev_consume_skb_any(tp->tx_tstamp_skb); in tg3_ptp_ts_aux_work()
6336 tp->tx_tstamp_skb = NULL; in tg3_ptp_ts_aux_work()
6337 tp->ptp_txts_retrycnt = 0; in tg3_ptp_ts_aux_work()
6338 tp->pre_tx_ts = 0; in tg3_ptp_ts_aux_work()
6360 static void tg3_ptp_init(struct tg3 *tp) in tg3_ptp_init() argument
6362 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_ptp_init()
6366 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real())); in tg3_ptp_init()
6367 tp->ptp_adjust = 0; in tg3_ptp_init()
6368 tp->ptp_info = tg3_ptp_caps; in tg3_ptp_init()
6372 static void tg3_ptp_resume(struct tg3 *tp) in tg3_ptp_resume() argument
6374 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_ptp_resume()
6377 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust); in tg3_ptp_resume()
6378 tp->ptp_adjust = 0; in tg3_ptp_resume()
6381 static void tg3_ptp_fini(struct tg3 *tp) in tg3_ptp_fini() argument
6383 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock) in tg3_ptp_fini()
6386 ptp_clock_unregister(tp->ptp_clock); in tg3_ptp_fini()
6387 tp->ptp_clock = NULL; in tg3_ptp_fini()
6388 tp->ptp_adjust = 0; in tg3_ptp_fini()
6389 dev_consume_skb_any(tp->tx_tstamp_skb); in tg3_ptp_fini()
6390 tp->tx_tstamp_skb = NULL; in tg3_ptp_fini()
6393 static inline int tg3_irq_sync(struct tg3 *tp) in tg3_irq_sync() argument
6395 return tp->irq_sync; in tg3_irq_sync()
6398 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) in tg3_rd32_loop() argument
6407 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) in tg3_dump_legacy_regs() argument
6409 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); in tg3_dump_legacy_regs()
6410 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); in tg3_dump_legacy_regs()
6411 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); in tg3_dump_legacy_regs()
6412 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); in tg3_dump_legacy_regs()
6413 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); in tg3_dump_legacy_regs()
6414 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); in tg3_dump_legacy_regs()
6415 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); in tg3_dump_legacy_regs()
6416 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); in tg3_dump_legacy_regs()
6417 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); in tg3_dump_legacy_regs()
6418 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); in tg3_dump_legacy_regs()
6419 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); in tg3_dump_legacy_regs()
6420 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); in tg3_dump_legacy_regs()
6421 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); in tg3_dump_legacy_regs()
6422 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); in tg3_dump_legacy_regs()
6423 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); in tg3_dump_legacy_regs()
6424 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); in tg3_dump_legacy_regs()
6425 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); in tg3_dump_legacy_regs()
6426 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); in tg3_dump_legacy_regs()
6427 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); in tg3_dump_legacy_regs()
6429 if (tg3_flag(tp, SUPPORT_MSIX)) in tg3_dump_legacy_regs()
6430 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); in tg3_dump_legacy_regs()
6432 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); in tg3_dump_legacy_regs()
6433 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); in tg3_dump_legacy_regs()
6434 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); in tg3_dump_legacy_regs()
6435 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); in tg3_dump_legacy_regs()
6436 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); in tg3_dump_legacy_regs()
6437 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); in tg3_dump_legacy_regs()
6438 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); in tg3_dump_legacy_regs()
6439 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); in tg3_dump_legacy_regs()
6441 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_dump_legacy_regs()
6442 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); in tg3_dump_legacy_regs()
6443 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); in tg3_dump_legacy_regs()
6444 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); in tg3_dump_legacy_regs()
6447 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); in tg3_dump_legacy_regs()
6448 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); in tg3_dump_legacy_regs()
6449 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); in tg3_dump_legacy_regs()
6450 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); in tg3_dump_legacy_regs()
6451 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); in tg3_dump_legacy_regs()
6453 if (tg3_flag(tp, NVRAM)) in tg3_dump_legacy_regs()
6454 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); in tg3_dump_legacy_regs()
6457 static void tg3_dump_state(struct tg3 *tp) in tg3_dump_state() argument
6465 if (tp->pdev->error_state != pci_channel_io_normal) { in tg3_dump_state()
6466 netdev_err(tp->dev, "PCI channel ERROR!\n"); in tg3_dump_state()
6474 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_dump_state()
6479 tg3_dump_legacy_regs(tp, regs); in tg3_dump_state()
6486 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", in tg3_dump_state()
6493 for (i = 0; i < tp->irq_cnt; i++) { in tg3_dump_state()
6494 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_dump_state()
6497 netdev_err(tp->dev, in tg3_dump_state()
6508 netdev_err(tp->dev, in tg3_dump_state()
6527 static void tg3_tx_recover(struct tg3 *tp) in tg3_tx_recover() argument
6529 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) || in tg3_tx_recover()
6530 tp->write32_tx_mbox == tg3_write_indirect_mbox); in tg3_tx_recover()
6532 netdev_warn(tp->dev, in tg3_tx_recover()
6538 tg3_flag_set(tp, TX_RECOVERY_PENDING); in tg3_tx_recover()
6555 struct tg3 *tp = tnapi->tp; in tg3_tx() local
6559 int index = tnapi - tp->napi; in tg3_tx()
6562 if (tg3_flag(tp, ENABLE_TSS)) in tg3_tx()
6565 txq = netdev_get_tx_queue(tp->dev, index); in tg3_tx()
6574 tg3_tx_recover(tp); in tg3_tx()
6582 tg3_read_tx_tstamp(tp, &hwclock); in tg3_tx()
6583 if (hwclock != tp->pre_tx_ts) { in tg3_tx()
6584 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp); in tg3_tx()
6586 tp->pre_tx_ts = 0; in tg3_tx()
6588 tp->tx_tstamp_skb = skb; in tg3_tx()
6593 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), in tg3_tx()
6611 dma_unmap_page(&tp->pdev->dev, in tg3_tx()
6631 ptp_schedule_worker(tp->ptp_clock, 0); in tg3_tx()
6634 tg3_tx_recover(tp); in tg3_tx()
6668 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) in tg3_rx_data_free() argument
6670 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) + in tg3_rx_data_free()
6676 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), map_sz, in tg3_rx_data_free()
6694 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, in tg3_alloc_rx_data() argument
6706 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_alloc_rx_data()
6709 data_size = tp->rx_pkt_map_sz; in tg3_alloc_rx_data()
6713 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_alloc_rx_data()
6729 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) + in tg3_alloc_rx_data()
6741 mapping = dma_map_single(&tp->pdev->dev, data + TG3_RX_OFFSET(tp), in tg3_alloc_rx_data()
6743 if (unlikely(dma_mapping_error(&tp->pdev->dev, mapping))) { in tg3_alloc_rx_data()
6766 struct tg3 *tp = tnapi->tp; in tg3_recycle_rx() local
6769 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; in tg3_recycle_rx()
6774 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_recycle_rx()
6782 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_recycle_rx()
6833 struct tg3 *tp = tnapi->tp; in tg3_rx() local
6864 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; in tg3_rx()
6870 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; in tg3_rx()
6889 prefetch(data + TG3_RX_OFFSET(tp)); in tg3_rx()
6901 if (len > TG3_RX_COPY_THRESH(tp)) { in tg3_rx()
6905 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key, in tg3_rx()
6910 dma_unmap_single(&tp->pdev->dev, dma_addr, skb_size, in tg3_rx()
6928 skb_reserve(skb, TG3_RX_OFFSET(tp)); in tg3_rx()
6933 skb = netdev_alloc_skb(tp->dev, in tg3_rx()
6939 dma_sync_single_for_cpu(&tp->pdev->dev, dma_addr, len, in tg3_rx()
6942 data + TG3_RX_OFFSET(tp), in tg3_rx()
6944 dma_sync_single_for_device(&tp->pdev->dev, dma_addr, in tg3_rx()
6950 tg3_hwclock_to_timestamp(tp, tstamp, in tg3_rx()
6953 if ((tp->dev->features & NETIF_F_RXCSUM) && in tg3_rx()
6961 skb->protocol = eth_type_trans(skb, tp->dev); in tg3_rx()
6963 if (len > (tp->dev->mtu + ETH_HLEN) && in tg3_rx()
6971 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) in tg3_rx()
6983 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { in tg3_rx()
6985 tp->rx_std_ring_mask; in tg3_rx()
6993 sw_idx &= tp->rx_ret_ring_mask; in tg3_rx()
7007 if (!tg3_flag(tp, ENABLE_RSS)) { in tg3_rx()
7013 tp->rx_std_ring_mask; in tg3_rx()
7019 tp->rx_jmb_ring_mask; in tg3_rx()
7029 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; in tg3_rx()
7030 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; in tg3_rx()
7032 if (tnapi != &tp->napi[1]) { in tg3_rx()
7033 tp->rx_refill = true; in tg3_rx()
7034 napi_schedule(&tp->napi[1].napi); in tg3_rx()
7041 static void tg3_poll_link(struct tg3 *tp) in tg3_poll_link() argument
7044 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { in tg3_poll_link()
7045 struct tg3_hw_status *sblk = tp->napi[0].hw_status; in tg3_poll_link()
7050 spin_lock(&tp->lock); in tg3_poll_link()
7051 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_poll_link()
7059 tg3_setup_phy(tp, false); in tg3_poll_link()
7060 spin_unlock(&tp->lock); in tg3_poll_link()
7065 static int tg3_rx_prodring_xfer(struct tg3 *tp, in tg3_rx_prodring_xfer() argument
7086 cpycnt = tp->rx_std_ring_mask + 1 - in tg3_rx_prodring_xfer()
7090 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); in tg3_rx_prodring_xfer()
7125 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7127 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7144 cpycnt = tp->rx_jmb_ring_mask + 1 - in tg3_rx_prodring_xfer()
7148 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); in tg3_rx_prodring_xfer()
7183 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7185 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7193 struct tg3 *tp = tnapi->tp; in tg3_poll_work() local
7198 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll_work()
7212 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { in tg3_poll_work()
7213 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; in tg3_poll_work()
7218 tp->rx_refill = false; in tg3_poll_work()
7219 for (i = 1; i <= tp->rxq_cnt; i++) in tg3_poll_work()
7220 err |= tg3_rx_prodring_xfer(tp, dpr, in tg3_poll_work()
7221 &tp->napi[i].prodring); in tg3_poll_work()
7234 tw32_f(HOSTCC_MODE, tp->coal_now); in tg3_poll_work()
7240 static inline void tg3_reset_task_schedule(struct tg3 *tp) in tg3_reset_task_schedule() argument
7242 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_schedule()
7243 schedule_work(&tp->reset_task); in tg3_reset_task_schedule()
7246 static inline void tg3_reset_task_cancel(struct tg3 *tp) in tg3_reset_task_cancel() argument
7248 if (test_and_clear_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_cancel()
7249 cancel_work_sync(&tp->reset_task); in tg3_reset_task_cancel()
7250 tg3_flag_clear(tp, TX_RECOVERY_PENDING); in tg3_reset_task_cancel()
7256 struct tg3 *tp = tnapi->tp; in tg3_poll_msix() local
7263 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll_msix()
7284 if (tnapi == &tp->napi[1] && tp->rx_refill) in tg3_poll_msix()
7294 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) { in tg3_poll_msix()
7295 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_poll_msix()
7303 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1); in tg3_poll_msix()
7309 tg3_reset_task_schedule(tp); in tg3_poll_msix()
7313 static void tg3_process_error(struct tg3 *tp) in tg3_process_error() argument
7318 if (tg3_flag(tp, ERROR_PROCESSED)) in tg3_process_error()
7324 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); in tg3_process_error()
7329 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); in tg3_process_error()
7334 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); in tg3_process_error()
7341 tg3_dump_state(tp); in tg3_process_error()
7343 tg3_flag_set(tp, ERROR_PROCESSED); in tg3_process_error()
7344 tg3_reset_task_schedule(tp); in tg3_process_error()
7350 struct tg3 *tp = tnapi->tp; in tg3_poll() local
7356 tg3_process_error(tp); in tg3_poll()
7358 tg3_poll_link(tp); in tg3_poll()
7362 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll()
7368 if (tg3_flag(tp, TAGGED_STATUS)) { in tg3_poll()
7386 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1); in tg3_poll()
7392 tg3_reset_task_schedule(tp); in tg3_poll()
7396 static void tg3_napi_disable(struct tg3 *tp) in tg3_napi_disable() argument
7400 for (i = tp->irq_cnt - 1; i >= 0; i--) in tg3_napi_disable()
7401 napi_disable(&tp->napi[i].napi); in tg3_napi_disable()
7404 static void tg3_napi_enable(struct tg3 *tp) in tg3_napi_enable() argument
7408 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_enable()
7409 napi_enable(&tp->napi[i].napi); in tg3_napi_enable()
7412 static void tg3_napi_init(struct tg3 *tp) in tg3_napi_init() argument
7416 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll); in tg3_napi_init()
7417 for (i = 1; i < tp->irq_cnt; i++) in tg3_napi_init()
7418 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix); in tg3_napi_init()
7421 static void tg3_napi_fini(struct tg3 *tp) in tg3_napi_fini() argument
7425 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_fini()
7426 netif_napi_del(&tp->napi[i].napi); in tg3_napi_fini()
7429 static inline void tg3_netif_stop(struct tg3 *tp) in tg3_netif_stop() argument
7431 netif_trans_update(tp->dev); /* prevent tx timeout */ in tg3_netif_stop()
7432 tg3_napi_disable(tp); in tg3_netif_stop()
7433 netif_carrier_off(tp->dev); in tg3_netif_stop()
7434 netif_tx_disable(tp->dev); in tg3_netif_stop()
7438 static inline void tg3_netif_start(struct tg3 *tp) in tg3_netif_start() argument
7440 tg3_ptp_resume(tp); in tg3_netif_start()
7446 netif_tx_wake_all_queues(tp->dev); in tg3_netif_start()
7448 if (tp->link_up) in tg3_netif_start()
7449 netif_carrier_on(tp->dev); in tg3_netif_start()
7451 tg3_napi_enable(tp); in tg3_netif_start()
7452 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; in tg3_netif_start()
7453 tg3_enable_ints(tp); in tg3_netif_start()
7456 static void tg3_irq_quiesce(struct tg3 *tp) in tg3_irq_quiesce() argument
7457 __releases(tp->lock) in tg3_irq_quiesce()
7458 __acquires(tp->lock) in tg3_irq_quiesce()
7462 BUG_ON(tp->irq_sync); in tg3_irq_quiesce()
7464 tp->irq_sync = 1; in tg3_irq_quiesce()
7467 spin_unlock_bh(&tp->lock); in tg3_irq_quiesce()
7469 for (i = 0; i < tp->irq_cnt; i++) in tg3_irq_quiesce()
7470 synchronize_irq(tp->napi[i].irq_vec); in tg3_irq_quiesce()
7472 spin_lock_bh(&tp->lock); in tg3_irq_quiesce()
7480 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) in tg3_full_lock() argument
7482 spin_lock_bh(&tp->lock); in tg3_full_lock()
7484 tg3_irq_quiesce(tp); in tg3_full_lock()
7487 static inline void tg3_full_unlock(struct tg3 *tp) in tg3_full_unlock() argument
7489 spin_unlock_bh(&tp->lock); in tg3_full_unlock()
7498 struct tg3 *tp = tnapi->tp; in tg3_msi_1shot() local
7504 if (likely(!tg3_irq_sync(tp))) in tg3_msi_1shot()
7517 struct tg3 *tp = tnapi->tp; in tg3_msi() local
7530 if (likely(!tg3_irq_sync(tp))) in tg3_msi()
7539 struct tg3 *tp = tnapi->tp; in tg3_interrupt() local
7549 if (tg3_flag(tp, CHIP_RESETTING) || in tg3_interrupt()
7568 if (tg3_irq_sync(tp)) in tg3_interrupt()
7588 struct tg3 *tp = tnapi->tp; in tg3_interrupt_tagged() local
7598 if (tg3_flag(tp, CHIP_RESETTING) || in tg3_interrupt_tagged()
7626 if (tg3_irq_sync(tp)) in tg3_interrupt_tagged()
7641 struct tg3 *tp = tnapi->tp; in tg3_test_isr() local
7646 tg3_disable_ints(tp); in tg3_test_isr()
7656 struct tg3 *tp = netdev_priv(dev); in tg3_poll_controller() local
7658 if (tg3_irq_sync(tp)) in tg3_poll_controller()
7661 for (i = 0; i < tp->irq_cnt; i++) in tg3_poll_controller()
7662 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); in tg3_poll_controller()
7668 struct tg3 *tp = netdev_priv(dev); in tg3_tx_timeout() local
7670 if (netif_msg_tx_err(tp)) { in tg3_tx_timeout()
7672 tg3_dump_state(tp); in tg3_tx_timeout()
7675 tg3_reset_task_schedule(tp); in tg3_tx_timeout()
7689 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping, in tg3_4g_tso_overflow_test() argument
7692 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) { in tg3_4g_tso_overflow_test()
7701 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, in tg3_40bit_overflow_test() argument
7705 if (tg3_flag(tp, 40BIT_DMA_BUG)) in tg3_40bit_overflow_test()
7727 struct tg3 *tp = tnapi->tp; in tg3_tx_frag_set() local
7730 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8) in tg3_tx_frag_set()
7736 if (tg3_4g_tso_overflow_test(tp, map, len, mss)) in tg3_tx_frag_set()
7739 if (tg3_40bit_overflow_test(tp, map, len)) in tg3_tx_frag_set()
7742 if (tp->dma_limit) { in tg3_tx_frag_set()
7745 while (len > tp->dma_limit && *budget) { in tg3_tx_frag_set()
7746 u32 frag_len = tp->dma_limit; in tg3_tx_frag_set()
7747 len -= tp->dma_limit; in tg3_tx_frag_set()
7751 len += tp->dma_limit / 2; in tg3_tx_frag_set()
7752 frag_len = tp->dma_limit / 2; in tg3_tx_frag_set()
7795 dma_unmap_single(&tnapi->tp->pdev->dev, dma_unmap_addr(txb, mapping), in tg3_tx_skb_unmap()
7810 dma_unmap_page(&tnapi->tp->pdev->dev, in tg3_tx_skb_unmap()
7828 struct tg3 *tp = tnapi->tp; in tigon3_dma_hwbug_workaround() local
7833 if (tg3_asic_rev(tp) != ASIC_REV_5701) in tigon3_dma_hwbug_workaround()
7847 new_addr = dma_map_single(&tp->pdev->dev, new_skb->data, in tigon3_dma_hwbug_workaround()
7850 if (dma_mapping_error(&tp->pdev->dev, new_addr)) { in tigon3_dma_hwbug_workaround()
7890 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi, in tg3_tso_bug() argument
7912 segs = skb_gso_segment(skb, tp->dev->features & in tg3_tso_bug()
7921 __tg3_start_xmit(seg, tp->dev); in tg3_tso_bug()
7933 struct tg3 *tp = netdev_priv(dev); in __tg3_start_xmit() local
7947 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; in __tg3_start_xmit()
7948 if (tg3_flag(tp, ENABLE_TSS)) in __tg3_start_xmit()
7990 return tg3_tso_bug(tp, tnapi, txq, skb); in __tg3_start_xmit()
7996 tg3_flag(tp, TSO_BUG)) { in __tg3_start_xmit()
7998 return tg3_tso_bug(tp, tnapi, txq, skb); in __tg3_start_xmit()
8013 if (tg3_flag(tp, HW_TSO_1) || in __tg3_start_xmit()
8014 tg3_flag(tp, HW_TSO_2) || in __tg3_start_xmit()
8015 tg3_flag(tp, HW_TSO_3)) { in __tg3_start_xmit()
8023 if (tg3_flag(tp, HW_TSO_3)) { in __tg3_start_xmit()
8028 } else if (tg3_flag(tp, HW_TSO_2)) in __tg3_start_xmit()
8030 else if (tg3_flag(tp, HW_TSO_1) || in __tg3_start_xmit()
8031 tg3_asic_rev(tp) == ASIC_REV_5705) { in __tg3_start_xmit()
8059 if (tg3_flag(tp, USE_JUMBO_BDFLAG) && in __tg3_start_xmit()
8069 tg3_flag(tp, TX_TSTAMP_EN)) { in __tg3_start_xmit()
8070 tg3_full_lock(tp, 0); in __tg3_start_xmit()
8071 if (!tp->pre_tx_ts) { in __tg3_start_xmit()
8074 tg3_read_tx_tstamp(tp, &tp->pre_tx_ts); in __tg3_start_xmit()
8076 tg3_full_unlock(tp); in __tg3_start_xmit()
8081 mapping = dma_map_single(&tp->pdev->dev, skb->data, len, in __tg3_start_xmit()
8083 if (dma_mapping_error(&tp->pdev->dev, mapping)) in __tg3_start_xmit()
8092 if (tg3_flag(tp, 5701_DMA_BUG)) in __tg3_start_xmit()
8102 if (!tg3_flag(tp, HW_TSO_1) && in __tg3_start_xmit()
8103 !tg3_flag(tp, HW_TSO_2) && in __tg3_start_xmit()
8104 !tg3_flag(tp, HW_TSO_3)) in __tg3_start_xmit()
8115 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, in __tg3_start_xmit()
8121 if (dma_mapping_error(&tp->pdev->dev, mapping)) in __tg3_start_xmit()
8147 return tg3_tso_bug(tp, tnapi, txq, skb); in __tg3_start_xmit()
8214 struct tg3 *tp; in tg3_start_xmit() local
8216 tp = netdev_priv(dev); in tg3_start_xmit()
8217 tnapi = &tp->napi[skb_queue_mapping]; in tg3_start_xmit()
8219 if (tg3_flag(tp, ENABLE_TSS)) in tg3_start_xmit()
8228 static void tg3_mac_loopback(struct tg3 *tp, bool enable) in tg3_mac_loopback() argument
8231 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | in tg3_mac_loopback()
8234 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8236 if (!tg3_flag(tp, 5705_PLUS)) in tg3_mac_loopback()
8237 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8239 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_mac_loopback()
8240 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_mac_loopback()
8242 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_mac_loopback()
8244 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8246 if (tg3_flag(tp, 5705_PLUS) || in tg3_mac_loopback()
8247 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || in tg3_mac_loopback()
8248 tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_mac_loopback()
8249 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8252 tw32(MAC_MODE, tp->mac_mode); in tg3_mac_loopback()
8256 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk) in tg3_phy_lpbk_set() argument
8260 tg3_phy_toggle_apd(tp, false); in tg3_phy_lpbk_set()
8261 tg3_phy_toggle_automdix(tp, false); in tg3_phy_lpbk_set()
8263 if (extlpbk && tg3_phy_set_extloopbk(tp)) in tg3_phy_lpbk_set()
8275 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_lpbk_set()
8285 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_phy_lpbk_set()
8286 tg3_readphy(tp, MII_CTRL1000, &val); in tg3_phy_lpbk_set()
8289 tg3_writephy(tp, MII_CTRL1000, val); in tg3_phy_lpbk_set()
8293 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest); in tg3_phy_lpbk_set()
8298 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_lpbk_set()
8301 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_lpbk_set()
8302 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_phy_lpbk_set()
8306 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_phy_lpbk_set()
8307 tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_phy_lpbk_set()
8308 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | in tg3_phy_lpbk_set()
8313 tg3_readphy(tp, MII_TG3_FET_PTEST, &val); in tg3_phy_lpbk_set()
8317 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_lpbk_set()
8318 tg3_flag(tp, 5780_CLASS)) { in tg3_phy_lpbk_set()
8321 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_phy_lpbk_set()
8324 mac_mode = tp->mac_mode & in tg3_phy_lpbk_set()
8331 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_phy_lpbk_set()
8332 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; in tg3_phy_lpbk_set()
8339 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_lpbk_set()
8351 struct tg3 *tp = netdev_priv(dev); in tg3_set_loopback() local
8354 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) in tg3_set_loopback()
8357 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8358 tg3_mac_loopback(tp, true); in tg3_set_loopback()
8359 netif_carrier_on(tp->dev); in tg3_set_loopback()
8360 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8363 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_set_loopback()
8366 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8367 tg3_mac_loopback(tp, false); in tg3_set_loopback()
8369 tg3_setup_phy(tp, true); in tg3_set_loopback()
8370 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8378 struct tg3 *tp = netdev_priv(dev); in tg3_fix_features() local
8380 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) in tg3_fix_features()
8396 static void tg3_rx_prodring_free(struct tg3 *tp, in tg3_rx_prodring_free() argument
8401 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_free()
8403 i = (i + 1) & tp->rx_std_ring_mask) in tg3_rx_prodring_free()
8404 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8405 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8407 if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_rx_prodring_free()
8410 i = (i + 1) & tp->rx_jmb_ring_mask) { in tg3_rx_prodring_free()
8411 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8419 for (i = 0; i <= tp->rx_std_ring_mask; i++) in tg3_rx_prodring_free()
8420 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8421 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8423 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { in tg3_rx_prodring_free()
8424 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) in tg3_rx_prodring_free()
8425 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8437 static int tg3_rx_prodring_alloc(struct tg3 *tp, in tg3_rx_prodring_alloc() argument
8447 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_alloc()
8449 TG3_RX_STD_BUFF_RING_SIZE(tp)); in tg3_rx_prodring_alloc()
8452 TG3_RX_JMB_BUFF_RING_SIZE(tp)); in tg3_rx_prodring_alloc()
8457 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8460 if (tg3_flag(tp, 5780_CLASS) && in tg3_rx_prodring_alloc()
8461 tp->dev->mtu > ETH_DATA_LEN) in tg3_rx_prodring_alloc()
8463 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); in tg3_rx_prodring_alloc()
8469 for (i = 0; i <= tp->rx_std_ring_mask; i++) { in tg3_rx_prodring_alloc()
8480 for (i = 0; i < tp->rx_pending; i++) { in tg3_rx_prodring_alloc()
8483 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i, in tg3_rx_prodring_alloc()
8485 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8488 "successfully\n", i, tp->rx_pending); in tg3_rx_prodring_alloc()
8491 tp->rx_pending = i; in tg3_rx_prodring_alloc()
8496 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) in tg3_rx_prodring_alloc()
8499 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8501 if (!tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_rx_prodring_alloc()
8504 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { in tg3_rx_prodring_alloc()
8515 for (i = 0; i < tp->rx_jumbo_pending; i++) { in tg3_rx_prodring_alloc()
8518 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i, in tg3_rx_prodring_alloc()
8520 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8523 "successfully\n", i, tp->rx_jumbo_pending); in tg3_rx_prodring_alloc()
8526 tp->rx_jumbo_pending = i; in tg3_rx_prodring_alloc()
8535 tg3_rx_prodring_free(tp, tpr); in tg3_rx_prodring_alloc()
8539 static void tg3_rx_prodring_fini(struct tg3 *tp, in tg3_rx_prodring_fini() argument
8547 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_fini()
8552 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_fini()
8558 static int tg3_rx_prodring_init(struct tg3 *tp, in tg3_rx_prodring_init() argument
8561 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8566 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8567 TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_init()
8573 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { in tg3_rx_prodring_init()
8574 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8579 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8580 TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_init()
8590 tg3_rx_prodring_fini(tp, tpr); in tg3_rx_prodring_init()
8601 static void tg3_free_rings(struct tg3 *tp) in tg3_free_rings() argument
8605 for (j = 0; j < tp->irq_cnt; j++) { in tg3_free_rings()
8606 struct tg3_napi *tnapi = &tp->napi[j]; in tg3_free_rings()
8608 tg3_rx_prodring_free(tp, &tnapi->prodring); in tg3_free_rings()
8624 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j)); in tg3_free_rings()
8635 static int tg3_init_rings(struct tg3 *tp) in tg3_init_rings() argument
8640 tg3_free_rings(tp); in tg3_init_rings()
8642 for (i = 0; i < tp->irq_cnt; i++) { in tg3_init_rings()
8643 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_rings()
8658 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); in tg3_init_rings()
8661 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { in tg3_init_rings()
8662 tg3_free_rings(tp); in tg3_init_rings()
8670 static void tg3_mem_tx_release(struct tg3 *tp) in tg3_mem_tx_release() argument
8674 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_tx_release()
8675 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_tx_release()
8678 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, in tg3_mem_tx_release()
8688 static int tg3_mem_tx_acquire(struct tg3 *tp) in tg3_mem_tx_acquire() argument
8691 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_mem_tx_acquire()
8696 if (tg3_flag(tp, ENABLE_TSS)) in tg3_mem_tx_acquire()
8699 for (i = 0; i < tp->txq_cnt; i++, tnapi++) { in tg3_mem_tx_acquire()
8706 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_tx_acquire()
8717 tg3_mem_tx_release(tp); in tg3_mem_tx_acquire()
8721 static void tg3_mem_rx_release(struct tg3 *tp) in tg3_mem_rx_release() argument
8725 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_rx_release()
8726 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_release()
8728 tg3_rx_prodring_fini(tp, &tnapi->prodring); in tg3_mem_rx_release()
8733 dma_free_coherent(&tp->pdev->dev, in tg3_mem_rx_release()
8734 TG3_RX_RCB_RING_BYTES(tp), in tg3_mem_rx_release()
8741 static int tg3_mem_rx_acquire(struct tg3 *tp) in tg3_mem_rx_acquire() argument
8745 limit = tp->rxq_cnt; in tg3_mem_rx_acquire()
8750 if (tg3_flag(tp, ENABLE_RSS)) in tg3_mem_rx_acquire()
8754 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_acquire()
8756 if (tg3_rx_prodring_init(tp, &tnapi->prodring)) in tg3_mem_rx_acquire()
8763 if (!i && tg3_flag(tp, ENABLE_RSS)) in tg3_mem_rx_acquire()
8766 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_rx_acquire()
8767 TG3_RX_RCB_RING_BYTES(tp), in tg3_mem_rx_acquire()
8777 tg3_mem_rx_release(tp); in tg3_mem_rx_acquire()
8785 static void tg3_free_consistent(struct tg3 *tp) in tg3_free_consistent() argument
8789 for (i = 0; i < tp->irq_cnt; i++) { in tg3_free_consistent()
8790 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_free_consistent()
8793 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, in tg3_free_consistent()
8800 tg3_mem_rx_release(tp); in tg3_free_consistent()
8801 tg3_mem_tx_release(tp); in tg3_free_consistent()
8807 if (tp->hw_stats) { in tg3_free_consistent()
8808 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), in tg3_free_consistent()
8809 tp->hw_stats, tp->stats_mapping); in tg3_free_consistent()
8810 tp->hw_stats = NULL; in tg3_free_consistent()
8818 static int tg3_alloc_consistent(struct tg3 *tp) in tg3_alloc_consistent() argument
8822 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8824 &tp->stats_mapping, GFP_KERNEL); in tg3_alloc_consistent()
8825 if (!tp->hw_stats) in tg3_alloc_consistent()
8828 for (i = 0; i < tp->irq_cnt; i++) { in tg3_alloc_consistent()
8829 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_alloc_consistent()
8832 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8841 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_alloc_consistent()
8870 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp)) in tg3_alloc_consistent()
8876 tg3_free_consistent(tp); in tg3_alloc_consistent()
8885 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent) in tg3_stop_block() argument
8890 if (tg3_flag(tp, 5705_PLUS)) { in tg3_stop_block()
8912 if (pci_channel_offline(tp->pdev)) { in tg3_stop_block()
8913 dev_err(&tp->pdev->dev, in tg3_stop_block()
8927 dev_err(&tp->pdev->dev, in tg3_stop_block()
8937 static int tg3_abort_hw(struct tg3 *tp, bool silent) in tg3_abort_hw() argument
8941 tg3_disable_ints(tp); in tg3_abort_hw()
8943 if (pci_channel_offline(tp->pdev)) { in tg3_abort_hw()
8944 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE); in tg3_abort_hw()
8945 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8950 tp->rx_mode &= ~RX_MODE_ENABLE; in tg3_abort_hw()
8951 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_abort_hw()
8954 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8955 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); in tg3_abort_hw()
8956 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); in tg3_abort_hw()
8957 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8958 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); in tg3_abort_hw()
8959 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); in tg3_abort_hw()
8961 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); in tg3_abort_hw()
8962 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8963 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); in tg3_abort_hw()
8964 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8965 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); in tg3_abort_hw()
8966 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8967 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); in tg3_abort_hw()
8969 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8970 tw32_f(MAC_MODE, tp->mac_mode); in tg3_abort_hw()
8973 tp->tx_mode &= ~TX_MODE_ENABLE; in tg3_abort_hw()
8974 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_abort_hw()
8982 dev_err(&tp->pdev->dev, in tg3_abort_hw()
8988 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); in tg3_abort_hw()
8989 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8990 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); in tg3_abort_hw()
8995 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); in tg3_abort_hw()
8996 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); in tg3_abort_hw()
8999 for (i = 0; i < tp->irq_cnt; i++) { in tg3_abort_hw()
9000 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_abort_hw()
9009 static void tg3_save_pci_state(struct tg3 *tp) in tg3_save_pci_state() argument
9011 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); in tg3_save_pci_state()
9015 static void tg3_restore_pci_state(struct tg3 *tp) in tg3_restore_pci_state() argument
9020 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_restore_pci_state()
9021 tp->misc_host_ctrl); in tg3_restore_pci_state()
9025 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 && in tg3_restore_pci_state()
9026 tg3_flag(tp, PCIX_MODE)) in tg3_restore_pci_state()
9029 if (tg3_flag(tp, ENABLE_APE)) in tg3_restore_pci_state()
9033 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); in tg3_restore_pci_state()
9035 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); in tg3_restore_pci_state()
9037 if (!tg3_flag(tp, PCI_EXPRESS)) { in tg3_restore_pci_state()
9038 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_restore_pci_state()
9039 tp->pci_cacheline_sz); in tg3_restore_pci_state()
9040 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_restore_pci_state()
9041 tp->pci_lat_timer); in tg3_restore_pci_state()
9045 if (tg3_flag(tp, PCIX_MODE)) { in tg3_restore_pci_state()
9048 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
9051 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
9055 if (tg3_flag(tp, 5780_CLASS)) { in tg3_restore_pci_state()
9060 if (tg3_flag(tp, USING_MSI)) { in tg3_restore_pci_state()
9063 pci_read_config_word(tp->pdev, in tg3_restore_pci_state()
9064 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9066 pci_write_config_word(tp->pdev, in tg3_restore_pci_state()
9067 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9075 static void tg3_override_clk(struct tg3 *tp) in tg3_override_clk() argument
9079 switch (tg3_asic_rev(tp)) { in tg3_override_clk()
9096 static void tg3_restore_clk(struct tg3 *tp) in tg3_restore_clk() argument
9100 switch (tg3_asic_rev(tp)) { in tg3_restore_clk()
9119 static int tg3_chip_reset(struct tg3 *tp) in tg3_chip_reset() argument
9120 __releases(tp->lock) in tg3_chip_reset()
9121 __acquires(tp->lock) in tg3_chip_reset()
9127 if (!pci_device_is_present(tp->pdev)) in tg3_chip_reset()
9130 tg3_nvram_lock(tp); in tg3_chip_reset()
9132 tg3_ape_lock(tp, TG3_APE_LOCK_GRC); in tg3_chip_reset()
9137 tp->nvram_lock_cnt = 0; in tg3_chip_reset()
9143 tg3_save_pci_state(tp); in tg3_chip_reset()
9145 if (tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_chip_reset()
9146 tg3_flag(tp, 5755_PLUS)) in tg3_chip_reset()
9155 write_op = tp->write32; in tg3_chip_reset()
9157 tp->write32 = tg3_write32; in tg3_chip_reset()
9165 tg3_flag_set(tp, CHIP_RESETTING); in tg3_chip_reset()
9166 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chip_reset()
9167 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chip_reset()
9177 tg3_full_unlock(tp); in tg3_chip_reset()
9179 for (i = 0; i < tp->irq_cnt; i++) in tg3_chip_reset()
9180 synchronize_irq(tp->napi[i].irq_vec); in tg3_chip_reset()
9182 tg3_full_lock(tp, 0); in tg3_chip_reset()
9184 if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_chip_reset()
9192 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_chip_reset()
9194 if (tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_chip_reset()
9195 !tg3_flag(tp, 57765_PLUS) && in tg3_chip_reset()
9200 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) { in tg3_chip_reset()
9206 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_chip_reset()
9217 tg3_override_clk(tp); in tg3_chip_reset()
9220 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT)) in tg3_chip_reset()
9226 tp->write32 = write_op; in tg3_chip_reset()
9249 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); in tg3_chip_reset()
9253 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) { in tg3_chip_reset()
9256 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) { in tg3_chip_reset()
9264 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); in tg3_chip_reset()
9265 pci_write_config_dword(tp->pdev, 0xc4, in tg3_chip_reset()
9275 if (!tg3_flag(tp, CPMU_PRESENT)) in tg3_chip_reset()
9277 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16); in tg3_chip_reset()
9280 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA, in tg3_chip_reset()
9287 tg3_restore_pci_state(tp); in tg3_chip_reset()
9289 tg3_flag_clear(tp, CHIP_RESETTING); in tg3_chip_reset()
9290 tg3_flag_clear(tp, ERROR_PROCESSED); in tg3_chip_reset()
9293 if (tg3_flag(tp, 5780_CLASS)) in tg3_chip_reset()
9297 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) { in tg3_chip_reset()
9298 tg3_stop_fw(tp); in tg3_chip_reset()
9302 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_chip_reset()
9308 tg3_stop_fw(tp); in tg3_chip_reset()
9309 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_chip_reset()
9312 err = tg3_poll_fw(tp); in tg3_chip_reset()
9316 tw32(GRC_MODE, tp->grc_mode); in tg3_chip_reset()
9318 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) { in tg3_chip_reset()
9324 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && in tg3_chip_reset()
9325 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_chip_reset()
9326 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; in tg3_chip_reset()
9327 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) in tg3_chip_reset()
9328 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; in tg3_chip_reset()
9329 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_chip_reset()
9332 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_chip_reset()
9333 tp->mac_mode = MAC_MODE_PORT_MODE_TBI; in tg3_chip_reset()
9334 val = tp->mac_mode; in tg3_chip_reset()
9335 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_chip_reset()
9336 tp->mac_mode = MAC_MODE_PORT_MODE_GMII; in tg3_chip_reset()
9337 val = tp->mac_mode; in tg3_chip_reset()
9344 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); in tg3_chip_reset()
9346 tg3_mdio_start(tp); in tg3_chip_reset()
9348 if (tg3_flag(tp, PCI_EXPRESS) && in tg3_chip_reset()
9349 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 && in tg3_chip_reset()
9350 tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_chip_reset()
9351 !tg3_flag(tp, 57765_PLUS)) { in tg3_chip_reset()
9357 tg3_restore_clk(tp); in tg3_chip_reset()
9362 if (tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_chip_reset()
9369 tg3_flag_clear(tp, ENABLE_ASF); in tg3_chip_reset()
9370 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_chip_reset()
9373 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); in tg3_chip_reset()
9374 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); in tg3_chip_reset()
9378 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); in tg3_chip_reset()
9380 tg3_flag_set(tp, ENABLE_ASF); in tg3_chip_reset()
9381 tp->last_event_jiffies = jiffies; in tg3_chip_reset()
9382 if (tg3_flag(tp, 5750_PLUS)) in tg3_chip_reset()
9383 tg3_flag_set(tp, ASF_NEW_HANDSHAKE); in tg3_chip_reset()
9385 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg); in tg3_chip_reset()
9387 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_chip_reset()
9389 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_chip_reset()
9401 static int tg3_halt(struct tg3 *tp, int kind, bool silent) in tg3_halt() argument
9405 tg3_stop_fw(tp); in tg3_halt()
9407 tg3_write_sig_pre_reset(tp, kind); in tg3_halt()
9409 tg3_abort_hw(tp, silent); in tg3_halt()
9410 err = tg3_chip_reset(tp); in tg3_halt()
9412 __tg3_set_mac_addr(tp, false); in tg3_halt()
9414 tg3_write_sig_legacy(tp, kind); in tg3_halt()
9415 tg3_write_sig_post_reset(tp, kind); in tg3_halt()
9417 if (tp->hw_stats) { in tg3_halt()
9419 tg3_get_nstats(tp, &tp->net_stats_prev); in tg3_halt()
9420 tg3_get_estats(tp, &tp->estats_prev); in tg3_halt()
9423 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); in tg3_halt()
9426 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_halt()
9438 struct tg3 *tp = netdev_priv(dev); in tg3_set_mac_addr() local
9451 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_set_mac_addr()
9464 spin_lock_bh(&tp->lock); in tg3_set_mac_addr()
9465 __tg3_set_mac_addr(tp, skip_mac_1); in tg3_set_mac_addr()
9467 spin_unlock_bh(&tp->lock); in tg3_set_mac_addr()
9473 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, in tg3_set_bdinfo() argument
9477 tg3_write_mem(tp, in tg3_set_bdinfo()
9480 tg3_write_mem(tp, in tg3_set_bdinfo()
9483 tg3_write_mem(tp, in tg3_set_bdinfo()
9487 if (!tg3_flag(tp, 5705_PLUS)) in tg3_set_bdinfo()
9488 tg3_write_mem(tp, in tg3_set_bdinfo()
9494 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec) in tg3_coal_tx_init() argument
9498 if (!tg3_flag(tp, ENABLE_TSS)) { in tg3_coal_tx_init()
9507 for (; i < tp->txq_cnt; i++) { in tg3_coal_tx_init()
9519 for (; i < tp->irq_max - 1; i++) { in tg3_coal_tx_init()
9526 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec) in tg3_coal_rx_init() argument
9529 u32 limit = tp->rxq_cnt; in tg3_coal_rx_init()
9531 if (!tg3_flag(tp, ENABLE_RSS)) { in tg3_coal_rx_init()
9553 for (; i < tp->irq_max - 1; i++) { in tg3_coal_rx_init()
9560 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) in __tg3_set_coalesce() argument
9562 tg3_coal_tx_init(tp, ec); in __tg3_set_coalesce()
9563 tg3_coal_rx_init(tp, ec); in __tg3_set_coalesce()
9565 if (!tg3_flag(tp, 5705_PLUS)) { in __tg3_set_coalesce()
9571 if (!tp->link_up) in __tg3_set_coalesce()
9579 static void tg3_tx_rcbs_disable(struct tg3 *tp) in tg3_tx_rcbs_disable() argument
9584 if (!tg3_flag(tp, 5705_PLUS)) in tg3_tx_rcbs_disable()
9586 else if (tg3_flag(tp, 5717_PLUS)) in tg3_tx_rcbs_disable()
9588 else if (tg3_flag(tp, 57765_CLASS) || in tg3_tx_rcbs_disable()
9589 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_tx_rcbs_disable()
9596 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, in tg3_tx_rcbs_disable()
9601 static void tg3_tx_rcbs_init(struct tg3 *tp) in tg3_tx_rcbs_init() argument
9606 if (tg3_flag(tp, ENABLE_TSS)) in tg3_tx_rcbs_init()
9609 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) { in tg3_tx_rcbs_init()
9610 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_tx_rcbs_init()
9615 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, in tg3_tx_rcbs_init()
9622 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp) in tg3_rx_ret_rcbs_disable() argument
9627 if (tg3_flag(tp, 5717_PLUS)) in tg3_rx_ret_rcbs_disable()
9629 else if (!tg3_flag(tp, 5705_PLUS)) in tg3_rx_ret_rcbs_disable()
9631 else if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_rx_ret_rcbs_disable()
9632 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_rx_ret_rcbs_disable()
9633 tg3_flag(tp, 57765_CLASS)) in tg3_rx_ret_rcbs_disable()
9640 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, in tg3_rx_ret_rcbs_disable()
9645 static void tg3_rx_ret_rcbs_init(struct tg3 *tp) in tg3_rx_ret_rcbs_init() argument
9650 if (tg3_flag(tp, ENABLE_RSS)) in tg3_rx_ret_rcbs_init()
9653 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) { in tg3_rx_ret_rcbs_init()
9654 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_rx_ret_rcbs_init()
9659 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, in tg3_rx_ret_rcbs_init()
9660 (tp->rx_ret_ring_mask + 1) << in tg3_rx_ret_rcbs_init()
9666 static void tg3_rings_reset(struct tg3 *tp) in tg3_rings_reset() argument
9670 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_rings_reset()
9672 tg3_tx_rcbs_disable(tp); in tg3_rings_reset()
9674 tg3_rx_ret_rcbs_disable(tp); in tg3_rings_reset()
9677 tw32_mailbox_f(tp->napi[0].int_mbox, 1); in tg3_rings_reset()
9678 tp->napi[0].chk_msi_cnt = 0; in tg3_rings_reset()
9679 tp->napi[0].last_rx_cons = 0; in tg3_rings_reset()
9680 tp->napi[0].last_tx_cons = 0; in tg3_rings_reset()
9683 if (tg3_flag(tp, SUPPORT_MSIX)) { in tg3_rings_reset()
9684 for (i = 1; i < tp->irq_max; i++) { in tg3_rings_reset()
9685 tp->napi[i].tx_prod = 0; in tg3_rings_reset()
9686 tp->napi[i].tx_cons = 0; in tg3_rings_reset()
9687 if (tg3_flag(tp, ENABLE_TSS)) in tg3_rings_reset()
9688 tw32_mailbox(tp->napi[i].prodmbox, 0); in tg3_rings_reset()
9689 tw32_rx_mbox(tp->napi[i].consmbox, 0); in tg3_rings_reset()
9690 tw32_mailbox_f(tp->napi[i].int_mbox, 1); in tg3_rings_reset()
9691 tp->napi[i].chk_msi_cnt = 0; in tg3_rings_reset()
9692 tp->napi[i].last_rx_cons = 0; in tg3_rings_reset()
9693 tp->napi[i].last_tx_cons = 0; in tg3_rings_reset()
9695 if (!tg3_flag(tp, ENABLE_TSS)) in tg3_rings_reset()
9696 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9698 tp->napi[0].tx_prod = 0; in tg3_rings_reset()
9699 tp->napi[0].tx_cons = 0; in tg3_rings_reset()
9700 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9701 tw32_rx_mbox(tp->napi[0].consmbox, 0); in tg3_rings_reset()
9705 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_rings_reset()
9722 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { in tg3_rings_reset()
9732 tg3_tx_rcbs_init(tp); in tg3_rings_reset()
9733 tg3_rx_ret_rcbs_init(tp); in tg3_rings_reset()
9736 static void tg3_setup_rxbd_thresholds(struct tg3 *tp) in tg3_setup_rxbd_thresholds() argument
9740 if (!tg3_flag(tp, 5750_PLUS) || in tg3_setup_rxbd_thresholds()
9741 tg3_flag(tp, 5780_CLASS) || in tg3_setup_rxbd_thresholds()
9742 tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_setup_rxbd_thresholds()
9743 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_setup_rxbd_thresholds()
9744 tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9746 else if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_setup_rxbd_thresholds()
9747 tg3_asic_rev(tp) == ASIC_REV_5787) in tg3_setup_rxbd_thresholds()
9752 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); in tg3_setup_rxbd_thresholds()
9753 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9758 if (tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9761 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) in tg3_setup_rxbd_thresholds()
9766 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9771 if (tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9799 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) in tg3_set_multi() argument
9810 struct tg3 *tp = netdev_priv(dev); in __tg3_set_rx_mode() local
9813 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | in __tg3_set_rx_mode()
9820 if (!tg3_flag(tp, ENABLE_ASF)) in __tg3_set_rx_mode()
9829 tg3_set_multi(tp, 1); in __tg3_set_rx_mode()
9832 tg3_set_multi(tp, 0); in __tg3_set_rx_mode()
9855 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) { in __tg3_set_rx_mode()
9863 __tg3_set_one_mac_addr(tp, ha->addr, in __tg3_set_rx_mode()
9864 i + TG3_UCAST_ADDR_IDX(tp)); in __tg3_set_rx_mode()
9869 if (rx_mode != tp->rx_mode) { in __tg3_set_rx_mode()
9870 tp->rx_mode = rx_mode; in __tg3_set_rx_mode()
9876 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt) in tg3_rss_init_dflt_indir_tbl() argument
9881 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt); in tg3_rss_init_dflt_indir_tbl()
9884 static void tg3_rss_check_indir_tbl(struct tg3 *tp) in tg3_rss_check_indir_tbl() argument
9888 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_rss_check_indir_tbl()
9891 if (tp->rxq_cnt == 1) { in tg3_rss_check_indir_tbl()
9892 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); in tg3_rss_check_indir_tbl()
9898 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt) in tg3_rss_check_indir_tbl()
9903 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt); in tg3_rss_check_indir_tbl()
9906 static void tg3_rss_write_indir_tbl(struct tg3 *tp) in tg3_rss_write_indir_tbl() argument
9912 u32 val = tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9916 val |= tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9923 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp) in tg3_lso_rd_dma_workaround_bit() argument
9925 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_lso_rd_dma_workaround_bit()
9932 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy) in tg3_reset_hw() argument
9936 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_reset_hw()
9938 tg3_disable_ints(tp); in tg3_reset_hw()
9940 tg3_stop_fw(tp); in tg3_reset_hw()
9942 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); in tg3_reset_hw()
9944 if (tg3_flag(tp, INIT_COMPLETE)) in tg3_reset_hw()
9945 tg3_abort_hw(tp, 1); in tg3_reset_hw()
9947 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_reset_hw()
9948 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) { in tg3_reset_hw()
9949 tg3_phy_pull_config(tp); in tg3_reset_hw()
9950 tg3_eee_pull_config(tp, NULL); in tg3_reset_hw()
9951 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_reset_hw()
9955 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_reset_hw()
9956 tg3_setup_eee(tp); in tg3_reset_hw()
9959 tg3_phy_reset(tp); in tg3_reset_hw()
9961 err = tg3_chip_reset(tp); in tg3_reset_hw()
9965 tg3_write_sig_legacy(tp, RESET_KIND_INIT); in tg3_reset_hw()
9967 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) { in tg3_reset_hw()
9988 if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_reset_hw()
10003 if (tg3_flag(tp, L1PLLPD_EN)) { in tg3_reset_hw()
10017 if (tg3_flag(tp, 57765_CLASS)) { in tg3_reset_hw()
10018 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) { in tg3_reset_hw()
10033 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) { in tg3_reset_hw()
10067 if (!tg3_flag(tp, CPMU_PRESENT)) { in tg3_reset_hw()
10068 if (!tg3_flag(tp, PCI_EXPRESS)) in tg3_reset_hw()
10069 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; in tg3_reset_hw()
10070 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_reset_hw()
10073 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 && in tg3_reset_hw()
10074 tg3_flag(tp, PCIX_MODE)) { in tg3_reset_hw()
10080 if (tg3_flag(tp, ENABLE_APE)) { in tg3_reset_hw()
10091 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) { in tg3_reset_hw()
10103 err = tg3_init_rings(tp); in tg3_reset_hw()
10107 if (tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10110 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) in tg3_reset_hw()
10112 if (!tg3_flag(tp, 57765_CLASS) && in tg3_reset_hw()
10113 tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_reset_hw()
10114 tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_reset_hw()
10116 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); in tg3_reset_hw()
10117 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 && in tg3_reset_hw()
10118 tg3_asic_rev(tp) != ASIC_REV_5761) { in tg3_reset_hw()
10122 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_reset_hw()
10125 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | in tg3_reset_hw()
10129 tp->grc_mode |= GRC_MODE_HOST_SENDBDS; in tg3_reset_hw()
10137 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; in tg3_reset_hw()
10140 if (tp->rxptpctl) in tg3_reset_hw()
10142 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_reset_hw()
10144 if (tg3_flag(tp, PTP_CAPABLE)) in tg3_reset_hw()
10147 tw32(GRC_MODE, tp->grc_mode | val); in tg3_reset_hw()
10153 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_reset_hw()
10154 tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) { in tg3_reset_hw()
10166 if (tg3_flag(tp, 5750_PLUS)) { in tg3_reset_hw()
10168 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) { in tg3_reset_hw()
10170 if (tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_reset_hw()
10176 } else if (tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10179 fw_len = tp->fw_len; in tg3_reset_hw()
10187 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10189 tp->bufmgr_config.mbuf_read_dma_low_water); in tg3_reset_hw()
10191 tp->bufmgr_config.mbuf_mac_rx_low_water); in tg3_reset_hw()
10193 tp->bufmgr_config.mbuf_high_water); in tg3_reset_hw()
10196 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); in tg3_reset_hw()
10198 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); in tg3_reset_hw()
10200 tp->bufmgr_config.mbuf_high_water_jumbo); in tg3_reset_hw()
10203 tp->bufmgr_config.dma_low_water); in tg3_reset_hw()
10205 tp->bufmgr_config.dma_high_water); in tg3_reset_hw()
10208 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_reset_hw()
10210 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_reset_hw()
10211 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_reset_hw()
10212 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10213 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) in tg3_reset_hw()
10222 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); in tg3_reset_hw()
10226 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1) in tg3_reset_hw()
10229 tg3_setup_rxbd_thresholds(tp); in tg3_reset_hw()
10252 if (!tg3_flag(tp, 5717_PLUS)) in tg3_reset_hw()
10257 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10264 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10265 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { in tg3_reset_hw()
10267 if (tg3_flag(tp, JUMBO_RING_ENABLE)) { in tg3_reset_hw()
10272 val = TG3_RX_JMB_RING_SIZE(tp) << in tg3_reset_hw()
10276 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || in tg3_reset_hw()
10277 tg3_flag(tp, 57765_CLASS) || in tg3_reset_hw()
10278 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10286 if (tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10287 val = TG3_RX_STD_RING_SIZE(tp); in tg3_reset_hw()
10297 tpr->rx_std_prod_idx = tp->rx_pending; in tg3_reset_hw()
10301 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; in tg3_reset_hw()
10304 tg3_rings_reset(tp); in tg3_reset_hw()
10307 __tg3_set_mac_addr(tp, false); in tg3_reset_hw()
10311 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); in tg3_reset_hw()
10320 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10321 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10341 if (tg3_asic_rev(tp) == ASIC_REV_5717) in tg3_reset_hw()
10344 if (tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_reset_hw()
10345 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10346 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_reset_hw()
10351 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_reset_hw()
10352 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_reset_hw()
10353 if (tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10356 !tg3_flag(tp, IS_5788)) { in tg3_reset_hw()
10361 if (tg3_flag(tp, PCI_EXPRESS)) in tg3_reset_hw()
10364 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_reset_hw()
10365 tp->dma_limit = 0; in tg3_reset_hw()
10366 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10368 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K; in tg3_reset_hw()
10372 if (tg3_flag(tp, HW_TSO_1) || in tg3_reset_hw()
10373 tg3_flag(tp, HW_TSO_2) || in tg3_reset_hw()
10374 tg3_flag(tp, HW_TSO_3)) in tg3_reset_hw()
10377 if (tg3_flag(tp, 57765_PLUS) || in tg3_reset_hw()
10378 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10379 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_reset_hw()
10382 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10383 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10386 if (tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_reset_hw()
10387 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_reset_hw()
10388 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10389 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_reset_hw()
10390 tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10393 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10399 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10400 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10411 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_reset_hw()
10412 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10413 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10416 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10428 if (tg3_flag(tp, 5750_PLUS)) { in tg3_reset_hw()
10433 tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10454 __tg3_set_coalesce(tp, &tp->coal); in tg3_reset_hw()
10456 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_reset_hw()
10462 ((u64) tp->stats_mapping >> 32)); in tg3_reset_hw()
10464 ((u64) tp->stats_mapping & 0xffffffff)); in tg3_reset_hw()
10473 tg3_write_mem(tp, i, 0); in tg3_reset_hw()
10478 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); in tg3_reset_hw()
10482 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10485 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_reset_hw()
10486 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_reset_hw()
10492 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | in tg3_reset_hw()
10495 if (tg3_flag(tp, ENABLE_APE)) in tg3_reset_hw()
10496 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_reset_hw()
10497 if (!tg3_flag(tp, 5705_PLUS) && in tg3_reset_hw()
10498 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10499 tg3_asic_rev(tp) != ASIC_REV_5700) in tg3_reset_hw()
10500 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_reset_hw()
10501 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); in tg3_reset_hw()
10510 if (!tg3_flag(tp, IS_NIC)) { in tg3_reset_hw()
10517 if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_reset_hw()
10521 if (tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_reset_hw()
10524 tp->grc_local_ctrl &= ~gpio_mask; in tg3_reset_hw()
10525 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
10528 if (tg3_flag(tp, EEPROM_WRITE_PROT)) in tg3_reset_hw()
10529 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_reset_hw()
10532 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10535 if (tg3_flag(tp, USING_MSIX)) { in tg3_reset_hw()
10538 if (tp->irq_cnt > 1) in tg3_reset_hw()
10540 if (!tg3_flag(tp, 1SHOT_MSI)) in tg3_reset_hw()
10545 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_reset_hw()
10556 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_reset_hw()
10557 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_reset_hw()
10558 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_reset_hw()
10559 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 || in tg3_reset_hw()
10560 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) { in tg3_reset_hw()
10563 !tg3_flag(tp, IS_5788)) { in tg3_reset_hw()
10569 if (tg3_flag(tp, 5755_PLUS)) in tg3_reset_hw()
10572 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_reset_hw()
10578 if (tg3_flag(tp, PCIX_MODE)) { in tg3_reset_hw()
10581 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10583 if (tg3_asic_rev(tp) == ASIC_REV_5703) { in tg3_reset_hw()
10586 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_reset_hw()
10590 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10597 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_reset_hw()
10598 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_reset_hw()
10600 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp)) in tg3_reset_hw()
10605 val |= tg3_lso_rd_dma_workaround_bit(tp); in tg3_reset_hw()
10607 tg3_flag_set(tp, 5719_5720_RDMA_BUG); in tg3_reset_hw()
10612 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10615 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_reset_hw()
10624 if (tg3_flag(tp, LRG_PROD_RING_CAP)) in tg3_reset_hw()
10628 if (tg3_flag(tp, HW_TSO_1) || in tg3_reset_hw()
10629 tg3_flag(tp, HW_TSO_2) || in tg3_reset_hw()
10630 tg3_flag(tp, HW_TSO_3)) in tg3_reset_hw()
10633 if (tg3_flag(tp, ENABLE_TSS)) in tg3_reset_hw()
10638 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) { in tg3_reset_hw()
10639 err = tg3_load_5701_a0_firmware_fix(tp); in tg3_reset_hw()
10644 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_reset_hw()
10648 tg3_load_57766_firmware(tp); in tg3_reset_hw()
10651 if (tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10652 err = tg3_load_tso_firmware(tp); in tg3_reset_hw()
10657 tp->tx_mode = TX_MODE_ENABLE; in tg3_reset_hw()
10659 if (tg3_flag(tp, 5755_PLUS) || in tg3_reset_hw()
10660 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_reset_hw()
10661 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; in tg3_reset_hw()
10663 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10664 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10666 tp->tx_mode &= ~val; in tg3_reset_hw()
10667 tp->tx_mode |= tr32(MAC_TX_MODE) & val; in tg3_reset_hw()
10670 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_reset_hw()
10673 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_reset_hw()
10676 tg3_rss_write_indir_tbl(tp); in tg3_reset_hw()
10684 tp->rx_mode = RX_MODE_ENABLE; in tg3_reset_hw()
10685 if (tg3_flag(tp, 5755_PLUS)) in tg3_reset_hw()
10686 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; in tg3_reset_hw()
10688 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10689 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX; in tg3_reset_hw()
10691 if (tg3_flag(tp, ENABLE_RSS)) in tg3_reset_hw()
10692 tp->rx_mode |= RX_MODE_RSS_ENABLE | in tg3_reset_hw()
10699 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10702 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_reset_hw()
10705 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10709 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10712 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10713 if ((tg3_asic_rev(tp) == ASIC_REV_5704) && in tg3_reset_hw()
10714 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { in tg3_reset_hw()
10722 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) in tg3_reset_hw()
10729 if (tg3_flag(tp, 57765_CLASS)) in tg3_reset_hw()
10735 if (tg3_asic_rev(tp) == ASIC_REV_5704 && in tg3_reset_hw()
10736 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_reset_hw()
10738 tg3_flag_set(tp, HW_AUTONEG); in tg3_reset_hw()
10741 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_reset_hw()
10742 tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_reset_hw()
10747 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; in tg3_reset_hw()
10748 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; in tg3_reset_hw()
10749 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10752 if (!tg3_flag(tp, USE_PHYLIB)) { in tg3_reset_hw()
10753 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_reset_hw()
10754 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_reset_hw()
10756 err = tg3_setup_phy(tp, false); in tg3_reset_hw()
10760 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10761 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_reset_hw()
10765 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { in tg3_reset_hw()
10766 tg3_writephy(tp, MII_TG3_TEST1, in tg3_reset_hw()
10768 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); in tg3_reset_hw()
10773 __tg3_set_rx_mode(tp->dev); in tg3_reset_hw()
10781 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) in tg3_reset_hw()
10785 if (tg3_flag(tp, ENABLE_ASF)) in tg3_reset_hw()
10835 if (tg3_flag(tp, ENABLE_APE)) in tg3_reset_hw()
10837 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, in tg3_reset_hw()
10840 tg3_write_sig_post_reset(tp, RESET_KIND_INIT); in tg3_reset_hw()
10848 static int tg3_init_hw(struct tg3 *tp, bool reset_phy) in tg3_init_hw() argument
10854 tg3_enable_register_access(tp); in tg3_init_hw()
10855 tg3_poll_fw(tp); in tg3_init_hw()
10857 tg3_switch_clocks(tp); in tg3_init_hw()
10861 return tg3_reset_hw(tp, reset_phy); in tg3_init_hw()
10865 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir) in tg3_sd_scan_scratchpad() argument
10871 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len); in tg3_sd_scan_scratchpad()
10884 struct tg3 *tp = dev_get_drvdata(dev); in tg3_show_temp() local
10887 spin_lock_bh(&tp->lock); in tg3_show_temp()
10888 tg3_ape_scratchpad_read(tp, &temperature, attr->index, in tg3_show_temp()
10890 spin_unlock_bh(&tp->lock); in tg3_show_temp()
10910 static void tg3_hwmon_close(struct tg3 *tp) in tg3_hwmon_close() argument
10912 if (tp->hwmon_dev) { in tg3_hwmon_close()
10913 hwmon_device_unregister(tp->hwmon_dev); in tg3_hwmon_close()
10914 tp->hwmon_dev = NULL; in tg3_hwmon_close()
10918 static void tg3_hwmon_open(struct tg3 *tp) in tg3_hwmon_open() argument
10922 struct pci_dev *pdev = tp->pdev; in tg3_hwmon_open()
10925 tg3_sd_scan_scratchpad(tp, ocirs); in tg3_hwmon_open()
10938 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3", in tg3_hwmon_open()
10939 tp, tg3_groups); in tg3_hwmon_open()
10940 if (IS_ERR(tp->hwmon_dev)) { in tg3_hwmon_open()
10941 tp->hwmon_dev = NULL; in tg3_hwmon_open()
10946 static inline void tg3_hwmon_close(struct tg3 *tp) { } in tg3_hwmon_close() argument
10947 static inline void tg3_hwmon_open(struct tg3 *tp) { } in tg3_hwmon_open() argument
10958 static void tg3_periodic_fetch_stats(struct tg3 *tp) in tg3_periodic_fetch_stats() argument
10960 struct tg3_hw_stats *sp = tp->hw_stats; in tg3_periodic_fetch_stats()
10962 if (!tp->link_up) in tg3_periodic_fetch_stats()
10978 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) && in tg3_periodic_fetch_stats()
10984 val &= ~tg3_lso_rd_dma_workaround_bit(tp); in tg3_periodic_fetch_stats()
10986 tg3_flag_clear(tp, 5719_5720_RDMA_BUG); in tg3_periodic_fetch_stats()
11005 if (tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_periodic_fetch_stats()
11006 tg3_asic_rev(tp) != ASIC_REV_5762 && in tg3_periodic_fetch_stats()
11007 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 && in tg3_periodic_fetch_stats()
11008 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) { in tg3_periodic_fetch_stats()
11024 static void tg3_chk_missed_msi(struct tg3 *tp) in tg3_chk_missed_msi() argument
11028 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chk_missed_msi()
11029 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chk_missed_msi()
11049 struct tg3 *tp = from_timer(tp, t, timer); in tg3_timer() local
11051 spin_lock(&tp->lock); in tg3_timer()
11053 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) { in tg3_timer()
11054 spin_unlock(&tp->lock); in tg3_timer()
11058 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_timer()
11059 tg3_flag(tp, 57765_CLASS)) in tg3_timer()
11060 tg3_chk_missed_msi(tp); in tg3_timer()
11062 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) { in tg3_timer()
11067 if (!tg3_flag(tp, TAGGED_STATUS)) { in tg3_timer()
11072 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { in tg3_timer()
11074 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_timer()
11076 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_timer()
11081 spin_unlock(&tp->lock); in tg3_timer()
11082 tg3_reset_task_schedule(tp); in tg3_timer()
11088 if (!--tp->timer_counter) { in tg3_timer()
11089 if (tg3_flag(tp, 5705_PLUS)) in tg3_timer()
11090 tg3_periodic_fetch_stats(tp); in tg3_timer()
11092 if (tp->setlpicnt && !--tp->setlpicnt) in tg3_timer()
11093 tg3_phy_eee_enable(tp); in tg3_timer()
11095 if (tg3_flag(tp, USE_LINKCHG_REG)) { in tg3_timer()
11102 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { in tg3_timer()
11109 tg3_setup_phy(tp, false); in tg3_timer()
11110 } else if (tg3_flag(tp, POLL_SERDES)) { in tg3_timer()
11114 if (tp->link_up && in tg3_timer()
11118 if (!tp->link_up && in tg3_timer()
11124 if (!tp->serdes_counter) { in tg3_timer()
11126 (tp->mac_mode & in tg3_timer()
11129 tw32_f(MAC_MODE, tp->mac_mode); in tg3_timer()
11132 tg3_setup_phy(tp, false); in tg3_timer()
11134 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_timer()
11135 tg3_flag(tp, 5780_CLASS)) { in tg3_timer()
11136 tg3_serdes_parallel_detect(tp); in tg3_timer()
11137 } else if (tg3_flag(tp, POLL_CPMU_LINK)) { in tg3_timer()
11142 if (link_up != tp->link_up) in tg3_timer()
11143 tg3_setup_phy(tp, false); in tg3_timer()
11146 tp->timer_counter = tp->timer_multiplier; in tg3_timer()
11166 if (!--tp->asf_counter) { in tg3_timer()
11167 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { in tg3_timer()
11168 tg3_wait_for_event_ack(tp); in tg3_timer()
11170 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, in tg3_timer()
11172 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); in tg3_timer()
11173 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, in tg3_timer()
11176 tg3_generate_fw_event(tp); in tg3_timer()
11178 tp->asf_counter = tp->asf_multiplier; in tg3_timer()
11182 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL); in tg3_timer()
11184 spin_unlock(&tp->lock); in tg3_timer()
11187 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer()
11188 add_timer(&tp->timer); in tg3_timer()
11191 static void tg3_timer_init(struct tg3 *tp) in tg3_timer_init() argument
11193 if (tg3_flag(tp, TAGGED_STATUS) && in tg3_timer_init()
11194 tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_timer_init()
11195 !tg3_flag(tp, 57765_CLASS)) in tg3_timer_init()
11196 tp->timer_offset = HZ; in tg3_timer_init()
11198 tp->timer_offset = HZ / 10; in tg3_timer_init()
11200 BUG_ON(tp->timer_offset > HZ); in tg3_timer_init()
11202 tp->timer_multiplier = (HZ / tp->timer_offset); in tg3_timer_init()
11203 tp->asf_multiplier = (HZ / tp->timer_offset) * in tg3_timer_init()
11206 timer_setup(&tp->timer, tg3_timer, 0); in tg3_timer_init()
11209 static void tg3_timer_start(struct tg3 *tp) in tg3_timer_start() argument
11211 tp->asf_counter = tp->asf_multiplier; in tg3_timer_start()
11212 tp->timer_counter = tp->timer_multiplier; in tg3_timer_start()
11214 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer_start()
11215 add_timer(&tp->timer); in tg3_timer_start()
11218 static void tg3_timer_stop(struct tg3 *tp) in tg3_timer_stop() argument
11220 del_timer_sync(&tp->timer); in tg3_timer_stop()
11226 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy) in tg3_restart_hw() argument
11227 __releases(tp->lock) in tg3_restart_hw()
11228 __acquires(tp->lock) in tg3_restart_hw()
11232 err = tg3_init_hw(tp, reset_phy); in tg3_restart_hw()
11234 netdev_err(tp->dev, in tg3_restart_hw()
11236 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_restart_hw()
11237 tg3_full_unlock(tp); in tg3_restart_hw()
11238 tg3_timer_stop(tp); in tg3_restart_hw()
11239 tp->irq_sync = 0; in tg3_restart_hw()
11240 tg3_napi_enable(tp); in tg3_restart_hw()
11241 dev_close(tp->dev); in tg3_restart_hw()
11242 tg3_full_lock(tp, 0); in tg3_restart_hw()
11249 struct tg3 *tp = container_of(work, struct tg3, reset_task); in tg3_reset_task() local
11253 tg3_full_lock(tp, 0); in tg3_reset_task()
11255 if (tp->pcierr_recovery || !netif_running(tp->dev) || in tg3_reset_task()
11256 tp->pdev->error_state != pci_channel_io_normal) { in tg3_reset_task()
11257 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task()
11258 tg3_full_unlock(tp); in tg3_reset_task()
11263 tg3_full_unlock(tp); in tg3_reset_task()
11265 tg3_phy_stop(tp); in tg3_reset_task()
11267 tg3_netif_stop(tp); in tg3_reset_task()
11269 tg3_full_lock(tp, 1); in tg3_reset_task()
11271 if (tg3_flag(tp, TX_RECOVERY_PENDING)) { in tg3_reset_task()
11272 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_reset_task()
11273 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_reset_task()
11274 tg3_flag_set(tp, MBOX_WRITE_REORDER); in tg3_reset_task()
11275 tg3_flag_clear(tp, TX_RECOVERY_PENDING); in tg3_reset_task()
11278 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); in tg3_reset_task()
11279 err = tg3_init_hw(tp, true); in tg3_reset_task()
11281 tg3_full_unlock(tp); in tg3_reset_task()
11282 tp->irq_sync = 0; in tg3_reset_task()
11283 tg3_napi_enable(tp); in tg3_reset_task()
11287 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task()
11288 dev_close(tp->dev); in tg3_reset_task()
11292 tg3_netif_start(tp); in tg3_reset_task()
11293 tg3_full_unlock(tp); in tg3_reset_task()
11294 tg3_phy_start(tp); in tg3_reset_task()
11295 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task()
11300 static int tg3_request_irq(struct tg3 *tp, int irq_num) in tg3_request_irq() argument
11305 struct tg3_napi *tnapi = &tp->napi[irq_num]; in tg3_request_irq()
11307 if (tp->irq_cnt == 1) in tg3_request_irq()
11308 name = tp->dev->name; in tg3_request_irq()
11313 "%s-txrx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11316 "%s-tx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11319 "%s-rx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11322 "%s-%d", tp->dev->name, irq_num); in tg3_request_irq()
11326 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { in tg3_request_irq()
11328 if (tg3_flag(tp, 1SHOT_MSI)) in tg3_request_irq()
11333 if (tg3_flag(tp, TAGGED_STATUS)) in tg3_request_irq()
11341 static int tg3_test_interrupt(struct tg3 *tp) in tg3_test_interrupt() argument
11343 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_test_interrupt()
11344 struct net_device *dev = tp->dev; in tg3_test_interrupt()
11351 tg3_disable_ints(tp); in tg3_test_interrupt()
11359 if (tg3_flag(tp, 57765_PLUS)) { in tg3_test_interrupt()
11370 tg3_enable_ints(tp); in tg3_test_interrupt()
11372 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_test_interrupt()
11387 if (tg3_flag(tp, 57765_PLUS) && in tg3_test_interrupt()
11394 tg3_disable_ints(tp); in tg3_test_interrupt()
11398 err = tg3_request_irq(tp, 0); in tg3_test_interrupt()
11405 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) { in tg3_test_interrupt()
11418 static int tg3_test_msi(struct tg3 *tp) in tg3_test_msi() argument
11423 if (!tg3_flag(tp, USING_MSI)) in tg3_test_msi()
11429 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_test_msi()
11430 pci_write_config_word(tp->pdev, PCI_COMMAND, in tg3_test_msi()
11433 err = tg3_test_interrupt(tp); in tg3_test_msi()
11435 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_test_msi()
11445 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " in tg3_test_msi()
11449 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11451 pci_disable_msi(tp->pdev); in tg3_test_msi()
11453 tg3_flag_clear(tp, USING_MSI); in tg3_test_msi()
11454 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_test_msi()
11456 err = tg3_request_irq(tp, 0); in tg3_test_msi()
11463 tg3_full_lock(tp, 1); in tg3_test_msi()
11465 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_test_msi()
11466 err = tg3_init_hw(tp, true); in tg3_test_msi()
11468 tg3_full_unlock(tp); in tg3_test_msi()
11471 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11476 static int tg3_request_firmware(struct tg3 *tp) in tg3_request_firmware() argument
11480 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { in tg3_request_firmware()
11481 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", in tg3_request_firmware()
11482 tp->fw_needed); in tg3_request_firmware()
11486 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_request_firmware()
11493 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */ in tg3_request_firmware()
11494 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) { in tg3_request_firmware()
11495 netdev_err(tp->dev, "bogus length %d in \"%s\"\n", in tg3_request_firmware()
11496 tp->fw_len, tp->fw_needed); in tg3_request_firmware()
11497 release_firmware(tp->fw); in tg3_request_firmware()
11498 tp->fw = NULL; in tg3_request_firmware()
11503 tp->fw_needed = NULL; in tg3_request_firmware()
11507 static u32 tg3_irq_count(struct tg3 *tp) in tg3_irq_count() argument
11509 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt); in tg3_irq_count()
11517 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max); in tg3_irq_count()
11523 static bool tg3_enable_msix(struct tg3 *tp) in tg3_enable_msix() argument
11528 tp->txq_cnt = tp->txq_req; in tg3_enable_msix()
11529 tp->rxq_cnt = tp->rxq_req; in tg3_enable_msix()
11530 if (!tp->rxq_cnt) in tg3_enable_msix()
11531 tp->rxq_cnt = netif_get_num_default_rss_queues(); in tg3_enable_msix()
11532 if (tp->rxq_cnt > tp->rxq_max) in tg3_enable_msix()
11533 tp->rxq_cnt = tp->rxq_max; in tg3_enable_msix()
11539 if (!tp->txq_req) in tg3_enable_msix()
11540 tp->txq_cnt = 1; in tg3_enable_msix()
11542 tp->irq_cnt = tg3_irq_count(tp); in tg3_enable_msix()
11544 for (i = 0; i < tp->irq_max; i++) { in tg3_enable_msix()
11549 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt); in tg3_enable_msix()
11552 } else if (rc < tp->irq_cnt) { in tg3_enable_msix()
11553 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", in tg3_enable_msix()
11554 tp->irq_cnt, rc); in tg3_enable_msix()
11555 tp->irq_cnt = rc; in tg3_enable_msix()
11556 tp->rxq_cnt = max(rc - 1, 1); in tg3_enable_msix()
11557 if (tp->txq_cnt) in tg3_enable_msix()
11558 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max); in tg3_enable_msix()
11561 for (i = 0; i < tp->irq_max; i++) in tg3_enable_msix()
11562 tp->napi[i].irq_vec = msix_ent[i].vector; in tg3_enable_msix()
11564 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) { in tg3_enable_msix()
11565 pci_disable_msix(tp->pdev); in tg3_enable_msix()
11569 if (tp->irq_cnt == 1) in tg3_enable_msix()
11572 tg3_flag_set(tp, ENABLE_RSS); in tg3_enable_msix()
11574 if (tp->txq_cnt > 1) in tg3_enable_msix()
11575 tg3_flag_set(tp, ENABLE_TSS); in tg3_enable_msix()
11577 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt); in tg3_enable_msix()
11582 static void tg3_ints_init(struct tg3 *tp) in tg3_ints_init() argument
11584 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) && in tg3_ints_init()
11585 !tg3_flag(tp, TAGGED_STATUS)) { in tg3_ints_init()
11589 netdev_warn(tp->dev, in tg3_ints_init()
11594 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp)) in tg3_ints_init()
11595 tg3_flag_set(tp, USING_MSIX); in tg3_ints_init()
11596 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) in tg3_ints_init()
11597 tg3_flag_set(tp, USING_MSI); in tg3_ints_init()
11599 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { in tg3_ints_init()
11601 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) in tg3_ints_init()
11603 if (!tg3_flag(tp, 1SHOT_MSI)) in tg3_ints_init()
11608 if (!tg3_flag(tp, USING_MSIX)) { in tg3_ints_init()
11609 tp->irq_cnt = 1; in tg3_ints_init()
11610 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_ints_init()
11613 if (tp->irq_cnt == 1) { in tg3_ints_init()
11614 tp->txq_cnt = 1; in tg3_ints_init()
11615 tp->rxq_cnt = 1; in tg3_ints_init()
11616 netif_set_real_num_tx_queues(tp->dev, 1); in tg3_ints_init()
11617 netif_set_real_num_rx_queues(tp->dev, 1); in tg3_ints_init()
11621 static void tg3_ints_fini(struct tg3 *tp) in tg3_ints_fini() argument
11623 if (tg3_flag(tp, USING_MSIX)) in tg3_ints_fini()
11624 pci_disable_msix(tp->pdev); in tg3_ints_fini()
11625 else if (tg3_flag(tp, USING_MSI)) in tg3_ints_fini()
11626 pci_disable_msi(tp->pdev); in tg3_ints_fini()
11627 tg3_flag_clear(tp, USING_MSI); in tg3_ints_fini()
11628 tg3_flag_clear(tp, USING_MSIX); in tg3_ints_fini()
11629 tg3_flag_clear(tp, ENABLE_RSS); in tg3_ints_fini()
11630 tg3_flag_clear(tp, ENABLE_TSS); in tg3_ints_fini()
11633 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq, in tg3_start() argument
11636 struct net_device *dev = tp->dev; in tg3_start()
11643 tg3_ints_init(tp); in tg3_start()
11645 tg3_rss_check_indir_tbl(tp); in tg3_start()
11650 err = tg3_alloc_consistent(tp); in tg3_start()
11654 tg3_napi_init(tp); in tg3_start()
11656 tg3_napi_enable(tp); in tg3_start()
11658 for (i = 0; i < tp->irq_cnt; i++) { in tg3_start()
11659 err = tg3_request_irq(tp, i); in tg3_start()
11662 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11670 tg3_full_lock(tp, 0); in tg3_start()
11673 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_start()
11675 err = tg3_init_hw(tp, reset_phy); in tg3_start()
11677 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_start()
11678 tg3_free_rings(tp); in tg3_start()
11681 tg3_full_unlock(tp); in tg3_start()
11686 if (test_irq && tg3_flag(tp, USING_MSI)) { in tg3_start()
11687 err = tg3_test_msi(tp); in tg3_start()
11690 tg3_full_lock(tp, 0); in tg3_start()
11691 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_start()
11692 tg3_free_rings(tp); in tg3_start()
11693 tg3_full_unlock(tp); in tg3_start()
11698 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { in tg3_start()
11706 tg3_phy_start(tp); in tg3_start()
11708 tg3_hwmon_open(tp); in tg3_start()
11710 tg3_full_lock(tp, 0); in tg3_start()
11712 tg3_timer_start(tp); in tg3_start()
11713 tg3_flag_set(tp, INIT_COMPLETE); in tg3_start()
11714 tg3_enable_ints(tp); in tg3_start()
11716 tg3_ptp_resume(tp); in tg3_start()
11718 tg3_full_unlock(tp); in tg3_start()
11732 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_start()
11733 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11738 tg3_napi_disable(tp); in tg3_start()
11739 tg3_napi_fini(tp); in tg3_start()
11740 tg3_free_consistent(tp); in tg3_start()
11743 tg3_ints_fini(tp); in tg3_start()
11748 static void tg3_stop(struct tg3 *tp) in tg3_stop() argument
11752 tg3_reset_task_cancel(tp); in tg3_stop()
11753 tg3_netif_stop(tp); in tg3_stop()
11755 tg3_timer_stop(tp); in tg3_stop()
11757 tg3_hwmon_close(tp); in tg3_stop()
11759 tg3_phy_stop(tp); in tg3_stop()
11761 tg3_full_lock(tp, 1); in tg3_stop()
11763 tg3_disable_ints(tp); in tg3_stop()
11765 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_stop()
11766 tg3_free_rings(tp); in tg3_stop()
11767 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_stop()
11769 tg3_full_unlock(tp); in tg3_stop()
11771 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_stop()
11772 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_stop()
11776 tg3_ints_fini(tp); in tg3_stop()
11778 tg3_napi_fini(tp); in tg3_stop()
11780 tg3_free_consistent(tp); in tg3_stop()
11785 struct tg3 *tp = netdev_priv(dev); in tg3_open() local
11788 if (tp->pcierr_recovery) { in tg3_open()
11794 if (tp->fw_needed) { in tg3_open()
11795 err = tg3_request_firmware(tp); in tg3_open()
11796 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_open()
11798 netdev_warn(tp->dev, "EEE capability disabled\n"); in tg3_open()
11799 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_open()
11800 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_open()
11801 netdev_warn(tp->dev, "EEE capability restored\n"); in tg3_open()
11802 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_open()
11804 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) { in tg3_open()
11808 netdev_warn(tp->dev, "TSO capability disabled\n"); in tg3_open()
11809 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_open()
11810 } else if (!tg3_flag(tp, TSO_CAPABLE)) { in tg3_open()
11811 netdev_notice(tp->dev, "TSO capability restored\n"); in tg3_open()
11812 tg3_flag_set(tp, TSO_CAPABLE); in tg3_open()
11816 tg3_carrier_off(tp); in tg3_open()
11818 err = tg3_power_up(tp); in tg3_open()
11822 tg3_full_lock(tp, 0); in tg3_open()
11824 tg3_disable_ints(tp); in tg3_open()
11825 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_open()
11827 tg3_full_unlock(tp); in tg3_open()
11829 err = tg3_start(tp, in tg3_open()
11830 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN), in tg3_open()
11833 tg3_frob_aux_power(tp, false); in tg3_open()
11834 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_open()
11842 struct tg3 *tp = netdev_priv(dev); in tg3_close() local
11844 if (tp->pcierr_recovery) { in tg3_close()
11850 tg3_stop(tp); in tg3_close()
11852 if (pci_device_is_present(tp->pdev)) { in tg3_close()
11853 tg3_power_down_prepare(tp); in tg3_close()
11855 tg3_carrier_off(tp); in tg3_close()
11865 static u64 tg3_calc_crc_errors(struct tg3 *tp) in tg3_calc_crc_errors() argument
11867 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_calc_crc_errors()
11869 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_calc_crc_errors()
11870 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_calc_crc_errors()
11871 tg3_asic_rev(tp) == ASIC_REV_5701)) { in tg3_calc_crc_errors()
11874 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { in tg3_calc_crc_errors()
11875 tg3_writephy(tp, MII_TG3_TEST1, in tg3_calc_crc_errors()
11877 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); in tg3_calc_crc_errors()
11881 tp->phy_crc_errors += val; in tg3_calc_crc_errors()
11883 return tp->phy_crc_errors; in tg3_calc_crc_errors()
11893 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats) in tg3_get_estats() argument
11895 struct tg3_ethtool_stats *old_estats = &tp->estats_prev; in tg3_get_estats()
11896 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_estats()
11977 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats) in tg3_get_nstats() argument
11979 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; in tg3_get_nstats()
11980 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_nstats()
12025 tg3_calc_crc_errors(tp); in tg3_get_nstats()
12041 for (i = 0; i < tp->irq_cnt; i++) { in tg3_get_nstats()
12042 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_get_nstats()
12060 struct tg3 *tp = netdev_priv(dev); in tg3_get_regs() local
12066 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_get_regs()
12069 tg3_full_lock(tp, 0); in tg3_get_regs()
12071 tg3_dump_legacy_regs(tp, (u32 *)_p); in tg3_get_regs()
12073 tg3_full_unlock(tp); in tg3_get_regs()
12078 struct tg3 *tp = netdev_priv(dev); in tg3_get_eeprom_len() local
12080 return tp->nvram_size; in tg3_get_eeprom_len()
12085 struct tg3 *tp = netdev_priv(dev); in tg3_get_eeprom() local
12091 if (tg3_flag(tp, NO_NVRAM)) in tg3_get_eeprom()
12101 if (tg3_flag(tp, CPMU_PRESENT)) { in tg3_get_eeprom()
12111 tg3_override_clk(tp); in tg3_get_eeprom()
12121 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); in tg3_get_eeprom()
12133 ret = tg3_nvram_read_be32(tp, offset + i, &val); in tg3_get_eeprom()
12157 ret = tg3_nvram_read_be32(tp, b_offset, &val); in tg3_get_eeprom()
12167 tg3_restore_clk(tp); in tg3_get_eeprom()
12176 struct tg3 *tp = netdev_priv(dev); in tg3_set_eeprom() local
12182 if (tg3_flag(tp, NO_NVRAM) || in tg3_set_eeprom()
12191 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); in tg3_set_eeprom()
12205 ret = tg3_nvram_read_be32(tp, offset+len-4, &end); in tg3_set_eeprom()
12222 ret = tg3_nvram_write_block(tp, offset, len, buf); in tg3_set_eeprom()
12233 struct tg3 *tp = netdev_priv(dev); in tg3_get_link_ksettings() local
12236 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_get_link_ksettings()
12238 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_get_link_ksettings()
12240 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_get_link_ksettings()
12248 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_get_link_ksettings()
12252 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12266 advertising = tp->link_config.advertising; in tg3_get_link_ksettings()
12267 if (tg3_flag(tp, PAUSE_AUTONEG)) { in tg3_get_link_ksettings()
12268 if (tp->link_config.flowctrl & FLOW_CTRL_RX) { in tg3_get_link_ksettings()
12269 if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12275 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12282 if (netif_running(dev) && tp->link_up) { in tg3_get_link_ksettings()
12283 cmd->base.speed = tp->link_config.active_speed; in tg3_get_link_ksettings()
12284 cmd->base.duplex = tp->link_config.active_duplex; in tg3_get_link_ksettings()
12287 tp->link_config.rmt_adv); in tg3_get_link_ksettings()
12289 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12290 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) in tg3_get_link_ksettings()
12300 cmd->base.phy_address = tp->phy_addr; in tg3_get_link_ksettings()
12301 cmd->base.autoneg = tp->link_config.autoneg; in tg3_get_link_ksettings()
12308 struct tg3 *tp = netdev_priv(dev); in tg3_set_link_ksettings() local
12312 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_set_link_ksettings()
12314 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_set_link_ksettings()
12316 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_link_ksettings()
12337 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_set_link_ksettings()
12341 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_set_link_ksettings()
12362 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { in tg3_set_link_ksettings()
12375 tg3_full_lock(tp, 0); in tg3_set_link_ksettings()
12377 tp->link_config.autoneg = cmd->base.autoneg; in tg3_set_link_ksettings()
12379 tp->link_config.advertising = (advertising | in tg3_set_link_ksettings()
12381 tp->link_config.speed = SPEED_UNKNOWN; in tg3_set_link_ksettings()
12382 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_set_link_ksettings()
12384 tp->link_config.advertising = 0; in tg3_set_link_ksettings()
12385 tp->link_config.speed = speed; in tg3_set_link_ksettings()
12386 tp->link_config.duplex = cmd->base.duplex; in tg3_set_link_ksettings()
12389 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_link_ksettings()
12391 tg3_warn_mgmt_link_flap(tp); in tg3_set_link_ksettings()
12394 tg3_setup_phy(tp, true); in tg3_set_link_ksettings()
12396 tg3_full_unlock(tp); in tg3_set_link_ksettings()
12403 struct tg3 *tp = netdev_priv(dev); in tg3_get_drvinfo() local
12406 strscpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); in tg3_get_drvinfo()
12407 strscpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); in tg3_get_drvinfo()
12412 struct tg3 *tp = netdev_priv(dev); in tg3_get_wol() local
12414 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12419 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12426 struct tg3 *tp = netdev_priv(dev); in tg3_set_wol() local
12427 struct device *dp = &tp->pdev->dev; in tg3_set_wol()
12432 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) in tg3_set_wol()
12438 tg3_flag_set(tp, WOL_ENABLE); in tg3_set_wol()
12440 tg3_flag_clear(tp, WOL_ENABLE); in tg3_set_wol()
12447 struct tg3 *tp = netdev_priv(dev); in tg3_get_msglevel() local
12448 return tp->msg_enable; in tg3_get_msglevel()
12453 struct tg3 *tp = netdev_priv(dev); in tg3_set_msglevel() local
12454 tp->msg_enable = value; in tg3_set_msglevel()
12459 struct tg3 *tp = netdev_priv(dev); in tg3_nway_reset() local
12465 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_nway_reset()
12468 tg3_warn_mgmt_link_flap(tp); in tg3_nway_reset()
12470 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_nway_reset()
12471 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_nway_reset()
12473 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_nway_reset()
12477 spin_lock_bh(&tp->lock); in tg3_nway_reset()
12479 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_nway_reset()
12480 if (!tg3_readphy(tp, MII_BMCR, &bmcr) && in tg3_nway_reset()
12482 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { in tg3_nway_reset()
12483 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | in tg3_nway_reset()
12487 spin_unlock_bh(&tp->lock); in tg3_nway_reset()
12498 struct tg3 *tp = netdev_priv(dev); in tg3_get_ringparam() local
12500 ering->rx_max_pending = tp->rx_std_ring_mask; in tg3_get_ringparam()
12501 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_get_ringparam()
12502 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; in tg3_get_ringparam()
12508 ering->rx_pending = tp->rx_pending; in tg3_get_ringparam()
12509 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_get_ringparam()
12510 ering->rx_jumbo_pending = tp->rx_jumbo_pending; in tg3_get_ringparam()
12514 ering->tx_pending = tp->napi[0].tx_pending; in tg3_get_ringparam()
12522 struct tg3 *tp = netdev_priv(dev); in tg3_set_ringparam() local
12526 if ((ering->rx_pending > tp->rx_std_ring_mask) || in tg3_set_ringparam()
12527 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || in tg3_set_ringparam()
12530 (tg3_flag(tp, TSO_BUG) && in tg3_set_ringparam()
12535 tg3_phy_stop(tp); in tg3_set_ringparam()
12536 tg3_netif_stop(tp); in tg3_set_ringparam()
12540 tg3_full_lock(tp, irq_sync); in tg3_set_ringparam()
12542 tp->rx_pending = ering->rx_pending; in tg3_set_ringparam()
12544 if (tg3_flag(tp, MAX_RXPEND_64) && in tg3_set_ringparam()
12545 tp->rx_pending > 63) in tg3_set_ringparam()
12546 tp->rx_pending = 63; in tg3_set_ringparam()
12548 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_set_ringparam()
12549 tp->rx_jumbo_pending = ering->rx_jumbo_pending; in tg3_set_ringparam()
12551 for (i = 0; i < tp->irq_max; i++) in tg3_set_ringparam()
12552 tp->napi[i].tx_pending = ering->tx_pending; in tg3_set_ringparam()
12555 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_set_ringparam()
12557 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_ringparam()
12558 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_set_ringparam()
12559 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_set_ringparam()
12562 err = tg3_restart_hw(tp, reset_phy); in tg3_set_ringparam()
12564 tg3_netif_start(tp); in tg3_set_ringparam()
12567 tg3_full_unlock(tp); in tg3_set_ringparam()
12570 tg3_phy_start(tp); in tg3_set_ringparam()
12577 struct tg3 *tp = netdev_priv(dev); in tg3_get_pauseparam() local
12579 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); in tg3_get_pauseparam()
12581 if (tp->link_config.flowctrl & FLOW_CTRL_RX) in tg3_get_pauseparam()
12586 if (tp->link_config.flowctrl & FLOW_CTRL_TX) in tg3_get_pauseparam()
12594 struct tg3 *tp = netdev_priv(dev); in tg3_set_pauseparam() local
12598 if (tp->link_config.autoneg == AUTONEG_ENABLE) in tg3_set_pauseparam()
12599 tg3_warn_mgmt_link_flap(tp); in tg3_set_pauseparam()
12601 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_set_pauseparam()
12604 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_pauseparam()
12609 tp->link_config.flowctrl = 0; in tg3_set_pauseparam()
12612 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12615 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12618 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12622 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12624 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12626 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_set_pauseparam()
12639 tg3_setup_flow_control(tp, 0, 0); in tg3_set_pauseparam()
12645 tg3_netif_stop(tp); in tg3_set_pauseparam()
12649 tg3_full_lock(tp, irq_sync); in tg3_set_pauseparam()
12652 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12654 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12656 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12658 tp->link_config.flowctrl &= ~FLOW_CTRL_RX; in tg3_set_pauseparam()
12660 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12662 tp->link_config.flowctrl &= ~FLOW_CTRL_TX; in tg3_set_pauseparam()
12665 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_set_pauseparam()
12667 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_pauseparam()
12668 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_set_pauseparam()
12669 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_set_pauseparam()
12672 err = tg3_restart_hw(tp, reset_phy); in tg3_set_pauseparam()
12674 tg3_netif_start(tp); in tg3_set_pauseparam()
12677 tg3_full_unlock(tp); in tg3_set_pauseparam()
12680 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_pauseparam()
12700 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxnfc() local
12702 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_get_rxnfc()
12707 if (netif_running(tp->dev)) in tg3_get_rxnfc()
12708 info->data = tp->rxq_cnt; in tg3_get_rxnfc()
12725 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxfh_indir_size() local
12727 if (tg3_flag(tp, SUPPORT_MSIX)) in tg3_get_rxfh_indir_size()
12735 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxfh() local
12743 rxfh->indir[i] = tp->rss_ind_tbl[i]; in tg3_get_rxfh()
12751 struct tg3 *tp = netdev_priv(dev); in tg3_set_rxfh() local
12766 tp->rss_ind_tbl[i] = rxfh->indir[i]; in tg3_set_rxfh()
12768 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS)) in tg3_set_rxfh()
12774 tg3_full_lock(tp, 0); in tg3_set_rxfh()
12775 tg3_rss_write_indir_tbl(tp); in tg3_set_rxfh()
12776 tg3_full_unlock(tp); in tg3_set_rxfh()
12784 struct tg3 *tp = netdev_priv(dev); in tg3_get_channels() local
12787 channel->max_rx = tp->rxq_max; in tg3_get_channels()
12788 channel->max_tx = tp->txq_max; in tg3_get_channels()
12791 channel->rx_count = tp->rxq_cnt; in tg3_get_channels()
12792 channel->tx_count = tp->txq_cnt; in tg3_get_channels()
12794 if (tp->rxq_req) in tg3_get_channels()
12795 channel->rx_count = tp->rxq_req; in tg3_get_channels()
12797 channel->rx_count = min(deflt_qs, tp->rxq_max); in tg3_get_channels()
12799 if (tp->txq_req) in tg3_get_channels()
12800 channel->tx_count = tp->txq_req; in tg3_get_channels()
12802 channel->tx_count = min(deflt_qs, tp->txq_max); in tg3_get_channels()
12809 struct tg3 *tp = netdev_priv(dev); in tg3_set_channels() local
12811 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_set_channels()
12814 if (channel->rx_count > tp->rxq_max || in tg3_set_channels()
12815 channel->tx_count > tp->txq_max) in tg3_set_channels()
12818 tp->rxq_req = channel->rx_count; in tg3_set_channels()
12819 tp->txq_req = channel->tx_count; in tg3_set_channels()
12824 tg3_stop(tp); in tg3_set_channels()
12826 tg3_carrier_off(tp); in tg3_set_channels()
12828 tg3_start(tp, true, false, false); in tg3_set_channels()
12851 struct tg3 *tp = netdev_priv(dev); in tg3_set_phys_id() local
12873 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_set_phys_id()
12883 struct tg3 *tp = netdev_priv(dev); in tg3_get_ethtool_stats() local
12885 if (tp->hw_stats) in tg3_get_ethtool_stats()
12886 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats); in tg3_get_ethtool_stats()
12891 static __be32 *tg3_vpd_readblock(struct tg3 *tp, unsigned int *vpdlen) in tg3_vpd_readblock() argument
12898 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) in tg3_vpd_readblock()
12905 if (tg3_nvram_read(tp, offset, &val)) in tg3_vpd_readblock()
12915 if (tg3_nvram_read(tp, offset + 4, &offset)) in tg3_vpd_readblock()
12918 offset = tg3_nvram_logical_addr(tp, offset); in tg3_vpd_readblock()
12935 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) in tg3_vpd_readblock()
12940 buf = pci_vpd_alloc(tp->pdev, vpdlen); in tg3_vpd_readblock()
12962 static int tg3_test_nvram(struct tg3 *tp) in tg3_test_nvram() argument
12969 if (tg3_flag(tp, NO_NVRAM)) in tg3_test_nvram()
12972 if (tg3_nvram_read(tp, 0, &magic) != 0) in tg3_test_nvram()
13015 err = tg3_nvram_read_be32(tp, i, &buf[j]); in tg3_test_nvram()
13106 buf = tg3_vpd_readblock(tp, &len); in tg3_test_nvram()
13122 static int tg3_test_link(struct tg3 *tp) in tg3_test_link() argument
13126 if (!netif_running(tp->dev)) in tg3_test_link()
13129 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_test_link()
13135 if (tp->link_up) in tg3_test_link()
13146 static int tg3_test_registers(struct tg3 *tp) in tg3_test_registers() argument
13296 if (tg3_flag(tp, 5705_PLUS)) { in tg3_test_registers()
13298 if (tg3_flag(tp, 5750_PLUS)) in tg3_test_registers()
13309 if (tg3_flag(tp, IS_5788) && in tg3_test_registers()
13359 if (netif_msg_hw(tp)) in tg3_test_registers()
13360 netdev_err(tp->dev, in tg3_test_registers()
13366 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) in tg3_do_mem_test() argument
13376 tg3_write_mem(tp, offset + j, test_pattern[i]); in tg3_do_mem_test()
13377 tg3_read_mem(tp, offset + j, &val); in tg3_do_mem_test()
13385 static int tg3_test_memory(struct tg3 *tp) in tg3_test_memory() argument
13432 if (tg3_flag(tp, 5717_PLUS)) in tg3_test_memory()
13434 else if (tg3_flag(tp, 57765_CLASS) || in tg3_test_memory()
13435 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_test_memory()
13437 else if (tg3_flag(tp, 5755_PLUS)) in tg3_test_memory()
13439 else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_test_memory()
13441 else if (tg3_flag(tp, 5705_PLUS)) in tg3_test_memory()
13447 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); in tg3_test_memory()
13478 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback) in tg3_run_loopback() argument
13489 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_run_loopback()
13491 tnapi = &tp->napi[0]; in tg3_run_loopback()
13492 rnapi = &tp->napi[0]; in tg3_run_loopback()
13493 if (tp->irq_cnt > 1) { in tg3_run_loopback()
13494 if (tg3_flag(tp, ENABLE_RSS)) in tg3_run_loopback()
13495 rnapi = &tp->napi[1]; in tg3_run_loopback()
13496 if (tg3_flag(tp, ENABLE_TSS)) in tg3_run_loopback()
13497 tnapi = &tp->napi[1]; in tg3_run_loopback()
13504 skb = netdev_alloc_skb(tp->dev, tx_len); in tg3_run_loopback()
13509 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN); in tg3_run_loopback()
13533 if (tg3_flag(tp, HW_TSO_1) || in tg3_run_loopback()
13534 tg3_flag(tp, HW_TSO_2) || in tg3_run_loopback()
13535 tg3_flag(tp, HW_TSO_3)) { in tg3_run_loopback()
13543 if (tg3_flag(tp, HW_TSO_3)) { in tg3_run_loopback()
13548 } else if (tg3_flag(tp, HW_TSO_2)) in tg3_run_loopback()
13550 else if (tg3_flag(tp, HW_TSO_1) || in tg3_run_loopback()
13551 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_run_loopback()
13562 if (tg3_flag(tp, USE_JUMBO_BDFLAG) && in tg3_run_loopback()
13570 map = dma_map_single(&tp->pdev->dev, skb->data, tx_len, DMA_TO_DEVICE); in tg3_run_loopback()
13571 if (dma_mapping_error(&tp->pdev->dev, map)) { in tg3_run_loopback()
13580 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13607 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13669 dma_sync_single_for_cpu(&tp->pdev->dev, map, rx_len, in tg3_run_loopback()
13672 rx_data += TG3_RX_OFFSET(tp); in tg3_run_loopback()
13694 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk) in tg3_test_loopback() argument
13700 if (tp->dma_limit) in tg3_test_loopback()
13701 jmb_pkt_sz = tp->dma_limit - ETH_HLEN; in tg3_test_loopback()
13703 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13704 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13706 if (!netif_running(tp->dev)) { in tg3_test_loopback()
13714 err = tg3_reset_hw(tp, true); in tg3_test_loopback()
13723 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_test_loopback()
13737 if (tg3_asic_rev(tp) != ASIC_REV_5780 && in tg3_test_loopback()
13738 !tg3_flag(tp, CPMU_PRESENT)) { in tg3_test_loopback()
13739 tg3_mac_loopback(tp, true); in tg3_test_loopback()
13741 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13744 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13745 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13748 tg3_mac_loopback(tp, false); in tg3_test_loopback()
13751 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_test_loopback()
13752 !tg3_flag(tp, USE_PHYLIB)) { in tg3_test_loopback()
13755 tg3_phy_lpbk_set(tp, 0, false); in tg3_test_loopback()
13764 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13766 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_test_loopback()
13767 tg3_run_loopback(tp, ETH_FRAME_LEN, true)) in tg3_test_loopback()
13769 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13770 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13774 tg3_phy_lpbk_set(tp, 0, true); in tg3_test_loopback()
13782 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13785 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_test_loopback()
13786 tg3_run_loopback(tp, ETH_FRAME_LEN, true)) in tg3_test_loopback()
13789 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13790 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13796 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_test_loopback()
13797 tg3_phy_toggle_apd(tp, true); in tg3_test_loopback()
13804 tp->phy_flags |= eee_cap; in tg3_test_loopback()
13812 struct tg3 *tp = netdev_priv(dev); in tg3_self_test() local
13815 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_self_test()
13816 if (tg3_power_up(tp)) { in tg3_self_test()
13821 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_self_test()
13826 if (tg3_test_nvram(tp) != 0) { in tg3_self_test()
13830 if (!doextlpbk && tg3_test_link(tp)) { in tg3_self_test()
13838 tg3_phy_stop(tp); in tg3_self_test()
13839 tg3_netif_stop(tp); in tg3_self_test()
13843 tg3_full_lock(tp, irq_sync); in tg3_self_test()
13844 tg3_halt(tp, RESET_KIND_SUSPEND, 1); in tg3_self_test()
13845 err = tg3_nvram_lock(tp); in tg3_self_test()
13846 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_self_test()
13847 if (!tg3_flag(tp, 5705_PLUS)) in tg3_self_test()
13848 tg3_halt_cpu(tp, TX_CPU_BASE); in tg3_self_test()
13850 tg3_nvram_unlock(tp); in tg3_self_test()
13852 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_self_test()
13853 tg3_phy_reset(tp); in tg3_self_test()
13855 if (tg3_test_registers(tp) != 0) { in tg3_self_test()
13860 if (tg3_test_memory(tp) != 0) { in tg3_self_test()
13868 if (tg3_test_loopback(tp, data, doextlpbk)) in tg3_self_test()
13871 tg3_full_unlock(tp); in tg3_self_test()
13873 if (tg3_test_interrupt(tp) != 0) { in tg3_self_test()
13878 tg3_full_lock(tp, 0); in tg3_self_test()
13880 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_self_test()
13882 tg3_flag_set(tp, INIT_COMPLETE); in tg3_self_test()
13883 err2 = tg3_restart_hw(tp, true); in tg3_self_test()
13885 tg3_netif_start(tp); in tg3_self_test()
13888 tg3_full_unlock(tp); in tg3_self_test()
13891 tg3_phy_start(tp); in tg3_self_test()
13893 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_self_test()
13894 tg3_power_down_prepare(tp); in tg3_self_test()
13900 struct tg3 *tp = netdev_priv(dev); in tg3_hwtstamp_set() local
13903 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_hwtstamp_set()
13915 tp->rxptpctl = 0; in tg3_hwtstamp_set()
13918 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13922 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13926 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13930 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13934 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13938 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13942 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13946 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13950 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13954 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13958 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13962 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13969 if (netif_running(dev) && tp->rxptpctl) in tg3_hwtstamp_set()
13971 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_hwtstamp_set()
13974 tg3_flag_set(tp, TX_TSTAMP_EN); in tg3_hwtstamp_set()
13976 tg3_flag_clear(tp, TX_TSTAMP_EN); in tg3_hwtstamp_set()
13984 struct tg3 *tp = netdev_priv(dev); in tg3_hwtstamp_get() local
13987 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_hwtstamp_get()
13991 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ? in tg3_hwtstamp_get()
13994 switch (tp->rxptpctl) { in tg3_hwtstamp_get()
14046 struct tg3 *tp = netdev_priv(dev); in tg3_ioctl() local
14049 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_ioctl()
14051 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_ioctl()
14053 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_ioctl()
14059 data->phy_id = tp->phy_addr; in tg3_ioctl()
14065 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14071 spin_lock_bh(&tp->lock); in tg3_ioctl()
14072 err = __tg3_readphy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14074 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14082 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14088 spin_lock_bh(&tp->lock); in tg3_ioctl()
14089 err = __tg3_writephy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14091 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14113 struct tg3 *tp = netdev_priv(dev); in tg3_get_coalesce() local
14115 memcpy(ec, &tp->coal, sizeof(*ec)); in tg3_get_coalesce()
14124 struct tg3 *tp = netdev_priv(dev); in tg3_set_coalesce() local
14128 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_set_coalesce()
14150 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; in tg3_set_coalesce()
14151 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; in tg3_set_coalesce()
14152 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; in tg3_set_coalesce()
14153 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; in tg3_set_coalesce()
14154 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; in tg3_set_coalesce()
14155 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; in tg3_set_coalesce()
14156 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; in tg3_set_coalesce()
14157 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; in tg3_set_coalesce()
14158 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; in tg3_set_coalesce()
14161 tg3_full_lock(tp, 0); in tg3_set_coalesce()
14162 __tg3_set_coalesce(tp, &tp->coal); in tg3_set_coalesce()
14163 tg3_full_unlock(tp); in tg3_set_coalesce()
14170 struct tg3 *tp = netdev_priv(dev); in tg3_set_eee() local
14172 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_set_eee()
14173 netdev_warn(tp->dev, "Board does not support EEE!\n"); in tg3_set_eee()
14177 if (!linkmode_equal(edata->advertised, tp->eee.advertised)) { in tg3_set_eee()
14178 netdev_warn(tp->dev, in tg3_set_eee()
14184 netdev_warn(tp->dev, in tg3_set_eee()
14190 tp->eee.eee_enabled = edata->eee_enabled; in tg3_set_eee()
14191 tp->eee.tx_lpi_enabled = edata->tx_lpi_enabled; in tg3_set_eee()
14192 tp->eee.tx_lpi_timer = edata->tx_lpi_timer; in tg3_set_eee()
14194 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_eee()
14195 tg3_warn_mgmt_link_flap(tp); in tg3_set_eee()
14197 if (netif_running(tp->dev)) { in tg3_set_eee()
14198 tg3_full_lock(tp, 0); in tg3_set_eee()
14199 tg3_setup_eee(tp); in tg3_set_eee()
14200 tg3_phy_reset(tp); in tg3_set_eee()
14201 tg3_full_unlock(tp); in tg3_set_eee()
14209 struct tg3 *tp = netdev_priv(dev); in tg3_get_eee() local
14211 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_get_eee()
14212 netdev_warn(tp->dev, in tg3_get_eee()
14217 *edata = tp->eee; in tg3_get_eee()
14266 struct tg3 *tp = netdev_priv(dev); in tg3_get_stats64() local
14268 spin_lock_bh(&tp->lock); in tg3_get_stats64()
14269 if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) { in tg3_get_stats64()
14270 *stats = tp->net_stats_prev; in tg3_get_stats64()
14271 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14275 tg3_get_nstats(tp, stats); in tg3_get_stats64()
14276 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14281 struct tg3 *tp = netdev_priv(dev); in tg3_set_rx_mode() local
14286 tg3_full_lock(tp, 0); in tg3_set_rx_mode()
14288 tg3_full_unlock(tp); in tg3_set_rx_mode()
14291 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, in tg3_set_mtu() argument
14297 if (tg3_flag(tp, 5780_CLASS)) { in tg3_set_mtu()
14299 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_set_mtu()
14301 tg3_flag_set(tp, JUMBO_RING_ENABLE); in tg3_set_mtu()
14304 if (tg3_flag(tp, 5780_CLASS)) { in tg3_set_mtu()
14305 tg3_flag_set(tp, TSO_CAPABLE); in tg3_set_mtu()
14308 tg3_flag_clear(tp, JUMBO_RING_ENABLE); in tg3_set_mtu()
14314 struct tg3 *tp = netdev_priv(dev); in tg3_change_mtu() local
14322 tg3_set_mtu(dev, tp, new_mtu); in tg3_change_mtu()
14326 tg3_phy_stop(tp); in tg3_change_mtu()
14328 tg3_netif_stop(tp); in tg3_change_mtu()
14330 tg3_set_mtu(dev, tp, new_mtu); in tg3_change_mtu()
14332 tg3_full_lock(tp, 1); in tg3_change_mtu()
14334 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_change_mtu()
14339 if (tg3_asic_rev(tp) == ASIC_REV_57766 || in tg3_change_mtu()
14340 tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_change_mtu()
14341 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_change_mtu()
14342 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_change_mtu()
14345 err = tg3_restart_hw(tp, reset_phy); in tg3_change_mtu()
14348 tg3_netif_start(tp); in tg3_change_mtu()
14350 tg3_full_unlock(tp); in tg3_change_mtu()
14353 tg3_phy_start(tp); in tg3_change_mtu()
14376 static void tg3_get_eeprom_size(struct tg3 *tp) in tg3_get_eeprom_size() argument
14380 tp->nvram_size = EEPROM_CHIP_SIZE; in tg3_get_eeprom_size()
14382 if (tg3_nvram_read(tp, 0, &magic) != 0) in tg3_get_eeprom_size()
14397 while (cursize < tp->nvram_size) { in tg3_get_eeprom_size()
14398 if (tg3_nvram_read(tp, cursize, &val) != 0) in tg3_get_eeprom_size()
14407 tp->nvram_size = cursize; in tg3_get_eeprom_size()
14410 static void tg3_get_nvram_size(struct tg3 *tp) in tg3_get_nvram_size() argument
14414 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) in tg3_get_nvram_size()
14419 tg3_get_eeprom_size(tp); in tg3_get_nvram_size()
14423 if (tg3_nvram_read(tp, 0xf0, &val) == 0) { in tg3_get_nvram_size()
14436 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; in tg3_get_nvram_size()
14440 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_nvram_size()
14443 static void tg3_get_nvram_info(struct tg3 *tp) in tg3_get_nvram_info() argument
14449 tg3_flag_set(tp, FLASH); in tg3_get_nvram_info()
14455 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_get_nvram_info()
14456 tg3_flag(tp, 5780_CLASS)) { in tg3_get_nvram_info()
14459 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14460 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14461 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14464 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14465 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; in tg3_get_nvram_info()
14468 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14469 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_nvram_info()
14470 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14473 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_nvram_info()
14474 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; in tg3_get_nvram_info()
14475 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14478 tp->nvram_jedecnum = JEDEC_SAIFUN; in tg3_get_nvram_info()
14479 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; in tg3_get_nvram_info()
14483 tp->nvram_jedecnum = JEDEC_SST; in tg3_get_nvram_info()
14484 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; in tg3_get_nvram_info()
14488 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14489 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14490 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14494 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) in tg3_nvram_get_pagesize() argument
14498 tp->nvram_pagesize = 256; in tg3_nvram_get_pagesize()
14501 tp->nvram_pagesize = 512; in tg3_nvram_get_pagesize()
14504 tp->nvram_pagesize = 1024; in tg3_nvram_get_pagesize()
14507 tp->nvram_pagesize = 2048; in tg3_nvram_get_pagesize()
14510 tp->nvram_pagesize = 4096; in tg3_nvram_get_pagesize()
14513 tp->nvram_pagesize = 264; in tg3_nvram_get_pagesize()
14516 tp->nvram_pagesize = 528; in tg3_nvram_get_pagesize()
14521 static void tg3_get_5752_nvram_info(struct tg3 *tp) in tg3_get_5752_nvram_info() argument
14529 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5752_nvram_info()
14534 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14535 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14538 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14539 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14540 tg3_flag_set(tp, FLASH); in tg3_get_5752_nvram_info()
14545 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5752_nvram_info()
14546 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14547 tg3_flag_set(tp, FLASH); in tg3_get_5752_nvram_info()
14551 if (tg3_flag(tp, FLASH)) { in tg3_get_5752_nvram_info()
14552 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5752_nvram_info()
14555 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5752_nvram_info()
14562 static void tg3_get_5755_nvram_info(struct tg3 *tp) in tg3_get_5755_nvram_info() argument
14570 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5755_nvram_info()
14580 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5755_nvram_info()
14581 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5755_nvram_info()
14582 tg3_flag_set(tp, FLASH); in tg3_get_5755_nvram_info()
14583 tp->nvram_pagesize = 264; in tg3_get_5755_nvram_info()
14586 tp->nvram_size = (protect ? 0x3e200 : in tg3_get_5755_nvram_info()
14589 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14592 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14598 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5755_nvram_info()
14599 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5755_nvram_info()
14600 tg3_flag_set(tp, FLASH); in tg3_get_5755_nvram_info()
14601 tp->nvram_pagesize = 256; in tg3_get_5755_nvram_info()
14603 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14607 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14611 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14618 static void tg3_get_5787_nvram_info(struct tg3 *tp) in tg3_get_5787_nvram_info() argument
14629 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14630 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14631 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5787_nvram_info()
14640 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14641 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14642 tg3_flag_set(tp, FLASH); in tg3_get_5787_nvram_info()
14643 tp->nvram_pagesize = 264; in tg3_get_5787_nvram_info()
14648 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5787_nvram_info()
14649 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14650 tg3_flag_set(tp, FLASH); in tg3_get_5787_nvram_info()
14651 tp->nvram_pagesize = 256; in tg3_get_5787_nvram_info()
14656 static void tg3_get_5761_nvram_info(struct tg3 *tp) in tg3_get_5761_nvram_info() argument
14664 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5761_nvram_info()
14678 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5761_nvram_info()
14679 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5761_nvram_info()
14680 tg3_flag_set(tp, FLASH); in tg3_get_5761_nvram_info()
14681 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5761_nvram_info()
14682 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14692 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5761_nvram_info()
14693 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5761_nvram_info()
14694 tg3_flag_set(tp, FLASH); in tg3_get_5761_nvram_info()
14695 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14700 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
14707 tp->nvram_size = TG3_NVRAM_SIZE_2MB; in tg3_get_5761_nvram_info()
14713 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5761_nvram_info()
14719 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5761_nvram_info()
14725 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5761_nvram_info()
14731 static void tg3_get_5906_nvram_info(struct tg3 *tp) in tg3_get_5906_nvram_info() argument
14733 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5906_nvram_info()
14734 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5906_nvram_info()
14735 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5906_nvram_info()
14738 static void tg3_get_57780_nvram_info(struct tg3 *tp) in tg3_get_57780_nvram_info() argument
14747 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14748 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14749 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_57780_nvram_info()
14761 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14762 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14763 tg3_flag_set(tp, FLASH); in tg3_get_57780_nvram_info()
14769 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14773 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14777 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14784 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_57780_nvram_info()
14785 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14786 tg3_flag_set(tp, FLASH); in tg3_get_57780_nvram_info()
14790 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14793 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14796 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14801 tg3_flag_set(tp, NO_NVRAM); in tg3_get_57780_nvram_info()
14805 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_57780_nvram_info()
14806 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_57780_nvram_info()
14807 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_57780_nvram_info()
14811 static void tg3_get_5717_nvram_info(struct tg3 *tp) in tg3_get_5717_nvram_info() argument
14820 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14821 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14822 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5717_nvram_info()
14834 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14835 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14836 tg3_flag_set(tp, FLASH); in tg3_get_5717_nvram_info()
14844 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14847 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14861 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5717_nvram_info()
14862 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14863 tg3_flag_set(tp, FLASH); in tg3_get_5717_nvram_info()
14872 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14875 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14880 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5717_nvram_info()
14884 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5717_nvram_info()
14885 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5717_nvram_info()
14886 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5717_nvram_info()
14889 static void tg3_get_5720_nvram_info(struct tg3 *tp) in tg3_get_5720_nvram_info() argument
14896 if (tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_get_5720_nvram_info()
14898 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
14908 tp->nvram_pagesize = 4096; in tg3_get_5720_nvram_info()
14909 tp->nvram_jedecnum = JEDEC_MACRONIX; in tg3_get_5720_nvram_info()
14910 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14911 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5720_nvram_info()
14912 tg3_flag_set(tp, FLASH); in tg3_get_5720_nvram_info()
14914 tp->nvram_size = in tg3_get_5720_nvram_info()
14938 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14939 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14944 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5720_nvram_info()
14946 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; in tg3_get_5720_nvram_info()
14960 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14961 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14962 tg3_flag_set(tp, FLASH); in tg3_get_5720_nvram_info()
14968 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14973 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14977 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14980 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_get_5720_nvram_info()
14981 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
15003 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5720_nvram_info()
15004 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
15005 tg3_flag_set(tp, FLASH); in tg3_get_5720_nvram_info()
15012 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
15018 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
15024 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
15027 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_get_5720_nvram_info()
15028 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
15033 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
15037 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5720_nvram_info()
15038 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5720_nvram_info()
15039 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5720_nvram_info()
15041 if (tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_get_5720_nvram_info()
15044 if (tg3_nvram_read(tp, 0, &val)) in tg3_get_5720_nvram_info()
15049 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
15054 static void tg3_nvram_init(struct tg3 *tp) in tg3_nvram_init() argument
15056 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_nvram_init()
15058 tg3_flag_clear(tp, NVRAM); in tg3_nvram_init()
15059 tg3_flag_clear(tp, NVRAM_BUFFERED); in tg3_nvram_init()
15060 tg3_flag_set(tp, NO_NVRAM); in tg3_nvram_init()
15076 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_nvram_init()
15077 tg3_asic_rev(tp) != ASIC_REV_5701) { in tg3_nvram_init()
15078 tg3_flag_set(tp, NVRAM); in tg3_nvram_init()
15080 if (tg3_nvram_lock(tp)) { in tg3_nvram_init()
15081 netdev_warn(tp->dev, in tg3_nvram_init()
15086 tg3_enable_nvram_access(tp); in tg3_nvram_init()
15088 tp->nvram_size = 0; in tg3_nvram_init()
15090 if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_nvram_init()
15091 tg3_get_5752_nvram_info(tp); in tg3_nvram_init()
15092 else if (tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_nvram_init()
15093 tg3_get_5755_nvram_info(tp); in tg3_nvram_init()
15094 else if (tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_nvram_init()
15095 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_nvram_init()
15096 tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_nvram_init()
15097 tg3_get_5787_nvram_info(tp); in tg3_nvram_init()
15098 else if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_nvram_init()
15099 tg3_get_5761_nvram_info(tp); in tg3_nvram_init()
15100 else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_nvram_init()
15101 tg3_get_5906_nvram_info(tp); in tg3_nvram_init()
15102 else if (tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_nvram_init()
15103 tg3_flag(tp, 57765_CLASS)) in tg3_nvram_init()
15104 tg3_get_57780_nvram_info(tp); in tg3_nvram_init()
15105 else if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_nvram_init()
15106 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_nvram_init()
15107 tg3_get_5717_nvram_info(tp); in tg3_nvram_init()
15108 else if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_nvram_init()
15109 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_nvram_init()
15110 tg3_get_5720_nvram_info(tp); in tg3_nvram_init()
15112 tg3_get_nvram_info(tp); in tg3_nvram_init()
15114 if (tp->nvram_size == 0) in tg3_nvram_init()
15115 tg3_get_nvram_size(tp); in tg3_nvram_init()
15117 tg3_disable_nvram_access(tp); in tg3_nvram_init()
15118 tg3_nvram_unlock(tp); in tg3_nvram_init()
15121 tg3_flag_clear(tp, NVRAM); in tg3_nvram_init()
15122 tg3_flag_clear(tp, NVRAM_BUFFERED); in tg3_nvram_init()
15124 tg3_get_eeprom_size(tp); in tg3_nvram_init()
15197 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp) in tg3_lookup_by_subsys() argument
15203 tp->pdev->subsystem_vendor) && in tg3_lookup_by_subsys()
15205 tp->pdev->subsystem_device)) in tg3_lookup_by_subsys()
15211 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp) in tg3_get_eeprom_hw_cfg() argument
15215 tp->phy_id = TG3_PHY_ID_INVALID; in tg3_get_eeprom_hw_cfg()
15216 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15219 tg3_flag_set(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15220 tg3_flag_set(tp, WOL_CAP); in tg3_get_eeprom_hw_cfg()
15222 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_eeprom_hw_cfg()
15224 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15225 tg3_flag_set(tp, IS_NIC); in tg3_get_eeprom_hw_cfg()
15229 tg3_flag_set(tp, ASPM_WORKAROUND); in tg3_get_eeprom_hw_cfg()
15232 tg3_flag_set(tp, WOL_ENABLE); in tg3_get_eeprom_hw_cfg()
15233 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15238 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); in tg3_get_eeprom_hw_cfg()
15245 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); in tg3_get_eeprom_hw_cfg()
15246 tp->nic_sram_data_cfg = nic_cfg; in tg3_get_eeprom_hw_cfg()
15248 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); in tg3_get_eeprom_hw_cfg()
15250 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_get_eeprom_hw_cfg()
15251 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_get_eeprom_hw_cfg()
15252 tg3_asic_rev(tp) != ASIC_REV_5703 && in tg3_get_eeprom_hw_cfg()
15254 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); in tg3_get_eeprom_hw_cfg()
15256 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_get_eeprom_hw_cfg()
15257 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); in tg3_get_eeprom_hw_cfg()
15259 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_eeprom_hw_cfg()
15260 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_eeprom_hw_cfg()
15261 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_get_eeprom_hw_cfg()
15262 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5); in tg3_get_eeprom_hw_cfg()
15268 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); in tg3_get_eeprom_hw_cfg()
15279 tp->phy_id = eeprom_phy_id; in tg3_get_eeprom_hw_cfg()
15281 if (!tg3_flag(tp, 5705_PLUS)) in tg3_get_eeprom_hw_cfg()
15282 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_get_eeprom_hw_cfg()
15284 tp->phy_flags |= TG3_PHYFLG_MII_SERDES; in tg3_get_eeprom_hw_cfg()
15287 if (tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15296 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15300 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15304 tp->led_ctrl = LED_CTRL_MODE_MAC; in tg3_get_eeprom_hw_cfg()
15309 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_eeprom_hw_cfg()
15310 tg3_asic_rev(tp) == ASIC_REV_5701) in tg3_get_eeprom_hw_cfg()
15311 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15316 tp->led_ctrl = LED_CTRL_MODE_SHARED; in tg3_get_eeprom_hw_cfg()
15317 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 && in tg3_get_eeprom_hw_cfg()
15318 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1) in tg3_get_eeprom_hw_cfg()
15319 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15322 if (tg3_flag(tp, 5717_PLUS) || in tg3_get_eeprom_hw_cfg()
15323 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_eeprom_hw_cfg()
15324 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE | in tg3_get_eeprom_hw_cfg()
15330 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; in tg3_get_eeprom_hw_cfg()
15334 tp->led_ctrl = LED_CTRL_MODE_COMBO; in tg3_get_eeprom_hw_cfg()
15335 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) in tg3_get_eeprom_hw_cfg()
15336 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15342 if ((tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_eeprom_hw_cfg()
15343 tg3_asic_rev(tp) == ASIC_REV_5701) && in tg3_get_eeprom_hw_cfg()
15344 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) in tg3_get_eeprom_hw_cfg()
15345 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15347 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) in tg3_get_eeprom_hw_cfg()
15348 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15351 tg3_flag_set(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15352 if ((tp->pdev->subsystem_vendor == in tg3_get_eeprom_hw_cfg()
15354 (tp->pdev->subsystem_device == 0x205a || in tg3_get_eeprom_hw_cfg()
15355 tp->pdev->subsystem_device == 0x2063)) in tg3_get_eeprom_hw_cfg()
15356 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15358 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15359 tg3_flag_set(tp, IS_NIC); in tg3_get_eeprom_hw_cfg()
15363 tg3_flag_set(tp, ENABLE_ASF); in tg3_get_eeprom_hw_cfg()
15364 if (tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15365 tg3_flag_set(tp, ASF_NEW_HANDSHAKE); in tg3_get_eeprom_hw_cfg()
15369 tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15370 tg3_flag_set(tp, ENABLE_APE); in tg3_get_eeprom_hw_cfg()
15372 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && in tg3_get_eeprom_hw_cfg()
15374 tg3_flag_clear(tp, WOL_CAP); in tg3_get_eeprom_hw_cfg()
15376 if (tg3_flag(tp, WOL_CAP) && in tg3_get_eeprom_hw_cfg()
15378 tg3_flag_set(tp, WOL_ENABLE); in tg3_get_eeprom_hw_cfg()
15379 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15383 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; in tg3_get_eeprom_hw_cfg()
15388 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; in tg3_get_eeprom_hw_cfg()
15390 if ((tg3_flag(tp, 57765_PLUS) || in tg3_get_eeprom_hw_cfg()
15391 (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_get_eeprom_hw_cfg()
15392 tg3_chip_rev(tp) != CHIPREV_5784_AX)) && in tg3_get_eeprom_hw_cfg()
15394 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; in tg3_get_eeprom_hw_cfg()
15396 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_get_eeprom_hw_cfg()
15399 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); in tg3_get_eeprom_hw_cfg()
15400 if (tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_get_eeprom_hw_cfg()
15401 !tg3_flag(tp, 57765_PLUS) && in tg3_get_eeprom_hw_cfg()
15403 tg3_flag_set(tp, ASPM_WORKAROUND); in tg3_get_eeprom_hw_cfg()
15405 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_get_eeprom_hw_cfg()
15407 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_get_eeprom_hw_cfg()
15411 tg3_flag_set(tp, RGMII_INBAND_DISABLE); in tg3_get_eeprom_hw_cfg()
15413 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN); in tg3_get_eeprom_hw_cfg()
15415 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN); in tg3_get_eeprom_hw_cfg()
15418 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV; in tg3_get_eeprom_hw_cfg()
15421 if (tg3_flag(tp, WOL_CAP)) in tg3_get_eeprom_hw_cfg()
15422 device_set_wakeup_enable(&tp->pdev->dev, in tg3_get_eeprom_hw_cfg()
15423 tg3_flag(tp, WOL_ENABLE)); in tg3_get_eeprom_hw_cfg()
15425 device_set_wakeup_capable(&tp->pdev->dev, false); in tg3_get_eeprom_hw_cfg()
15428 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val) in tg3_ape_otp_read() argument
15433 err = tg3_nvram_lock(tp); in tg3_ape_otp_read()
15437 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE); in tg3_ape_otp_read()
15438 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN | in tg3_ape_otp_read()
15440 tg3_ape_read32(tp, TG3_APE_OTP_CTRL); in tg3_ape_otp_read()
15444 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS); in tg3_ape_otp_read()
15446 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA); in tg3_ape_otp_read()
15452 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0); in tg3_ape_otp_read()
15454 tg3_nvram_unlock(tp); in tg3_ape_otp_read()
15461 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd) in tg3_issue_otp_command() argument
15484 static u32 tg3_read_otp_phycfg(struct tg3 *tp) in tg3_read_otp_phycfg() argument
15490 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) in tg3_read_otp_phycfg()
15495 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) in tg3_read_otp_phycfg()
15502 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) in tg3_read_otp_phycfg()
15510 static void tg3_phy_init_link_config(struct tg3 *tp) in tg3_phy_init_link_config() argument
15514 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init_link_config()
15515 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV)) in tg3_phy_init_link_config()
15520 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_init_link_config()
15529 tp->link_config.advertising = adv; in tg3_phy_init_link_config()
15530 tp->link_config.speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15531 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15532 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_init_link_config()
15533 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15534 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15536 tp->old_link = -1; in tg3_phy_init_link_config()
15539 static int tg3_phy_probe(struct tg3 *tp) in tg3_phy_probe() argument
15546 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_phy_probe()
15547 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; in tg3_phy_probe()
15549 if (tg3_flag(tp, ENABLE_APE)) { in tg3_phy_probe()
15550 switch (tp->pci_fn) { in tg3_phy_probe()
15552 tp->phy_ape_lock = TG3_APE_LOCK_PHY0; in tg3_phy_probe()
15555 tp->phy_ape_lock = TG3_APE_LOCK_PHY1; in tg3_phy_probe()
15558 tp->phy_ape_lock = TG3_APE_LOCK_PHY2; in tg3_phy_probe()
15561 tp->phy_ape_lock = TG3_APE_LOCK_PHY3; in tg3_phy_probe()
15566 if (!tg3_flag(tp, ENABLE_ASF) && in tg3_phy_probe()
15567 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15568 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_phy_probe()
15569 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_phy_probe()
15572 if (tg3_flag(tp, USE_PHYLIB)) in tg3_phy_probe()
15573 return tg3_phy_init(tp); in tg3_phy_probe()
15579 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) { in tg3_phy_probe()
15587 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); in tg3_phy_probe()
15588 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); in tg3_phy_probe()
15598 tp->phy_id = hw_phy_id; in tg3_phy_probe()
15600 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15602 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15604 if (tp->phy_id != TG3_PHY_ID_INVALID) { in tg3_phy_probe()
15614 p = tg3_lookup_by_subsys(tp); in tg3_phy_probe()
15616 tp->phy_id = p->phy_id; in tg3_phy_probe()
15617 } else if (!tg3_flag(tp, IS_SSB_CORE)) { in tg3_phy_probe()
15628 if (!tp->phy_id || in tg3_phy_probe()
15629 tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_phy_probe()
15630 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15634 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15635 (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_phy_probe()
15636 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_phy_probe()
15637 tg3_asic_rev(tp) == ASIC_REV_57766 || in tg3_phy_probe()
15638 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_phy_probe()
15639 (tg3_asic_rev(tp) == ASIC_REV_5717 && in tg3_phy_probe()
15640 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) || in tg3_phy_probe()
15641 (tg3_asic_rev(tp) == ASIC_REV_57765 && in tg3_phy_probe()
15642 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) { in tg3_phy_probe()
15643 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_phy_probe()
15645 linkmode_zero(tp->eee.supported); in tg3_phy_probe()
15647 tp->eee.supported); in tg3_phy_probe()
15649 tp->eee.supported); in tg3_phy_probe()
15650 linkmode_copy(tp->eee.advertised, tp->eee.supported); in tg3_phy_probe()
15652 tp->eee.eee_enabled = 1; in tg3_phy_probe()
15653 tp->eee.tx_lpi_enabled = 1; in tg3_phy_probe()
15654 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US; in tg3_phy_probe()
15657 tg3_phy_init_link_config(tp); in tg3_phy_probe()
15659 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_phy_probe()
15660 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15661 !tg3_flag(tp, ENABLE_APE) && in tg3_phy_probe()
15662 !tg3_flag(tp, ENABLE_ASF)) { in tg3_phy_probe()
15665 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_phy_probe()
15666 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_phy_probe()
15670 err = tg3_phy_reset(tp); in tg3_phy_probe()
15674 tg3_phy_set_wirespeed(tp); in tg3_phy_probe()
15676 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) { in tg3_phy_probe()
15677 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, in tg3_phy_probe()
15678 tp->link_config.flowctrl); in tg3_phy_probe()
15680 tg3_writephy(tp, MII_BMCR, in tg3_phy_probe()
15686 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_probe()
15687 err = tg3_init_5401phy_dsp(tp); in tg3_phy_probe()
15691 err = tg3_init_5401phy_dsp(tp); in tg3_phy_probe()
15697 static void tg3_read_vpd(struct tg3 *tp) in tg3_read_vpd() argument
15703 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen); in tg3_read_vpd()
15720 memset(tp->fw_ver, 0, sizeof(tp->fw_ver)); in tg3_read_vpd()
15721 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, vpd_data + i); in tg3_read_vpd()
15732 memcpy(tp->board_part_number, &vpd_data[i], len); in tg3_read_vpd()
15736 if (tp->board_part_number[0]) in tg3_read_vpd()
15740 if (tg3_asic_rev(tp) == ASIC_REV_5717) { in tg3_read_vpd()
15741 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_read_vpd()
15742 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C) in tg3_read_vpd()
15743 strcpy(tp->board_part_number, "BCM5717"); in tg3_read_vpd()
15744 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) in tg3_read_vpd()
15745 strcpy(tp->board_part_number, "BCM5718"); in tg3_read_vpd()
15748 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_read_vpd()
15749 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) in tg3_read_vpd()
15750 strcpy(tp->board_part_number, "BCM57780"); in tg3_read_vpd()
15751 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) in tg3_read_vpd()
15752 strcpy(tp->board_part_number, "BCM57760"); in tg3_read_vpd()
15753 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) in tg3_read_vpd()
15754 strcpy(tp->board_part_number, "BCM57790"); in tg3_read_vpd()
15755 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) in tg3_read_vpd()
15756 strcpy(tp->board_part_number, "BCM57788"); in tg3_read_vpd()
15759 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) { in tg3_read_vpd()
15760 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) in tg3_read_vpd()
15761 strcpy(tp->board_part_number, "BCM57761"); in tg3_read_vpd()
15762 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) in tg3_read_vpd()
15763 strcpy(tp->board_part_number, "BCM57765"); in tg3_read_vpd()
15764 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) in tg3_read_vpd()
15765 strcpy(tp->board_part_number, "BCM57781"); in tg3_read_vpd()
15766 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) in tg3_read_vpd()
15767 strcpy(tp->board_part_number, "BCM57785"); in tg3_read_vpd()
15768 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) in tg3_read_vpd()
15769 strcpy(tp->board_part_number, "BCM57791"); in tg3_read_vpd()
15770 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) in tg3_read_vpd()
15771 strcpy(tp->board_part_number, "BCM57795"); in tg3_read_vpd()
15774 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_read_vpd()
15775 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) in tg3_read_vpd()
15776 strcpy(tp->board_part_number, "BCM57762"); in tg3_read_vpd()
15777 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) in tg3_read_vpd()
15778 strcpy(tp->board_part_number, "BCM57766"); in tg3_read_vpd()
15779 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) in tg3_read_vpd()
15780 strcpy(tp->board_part_number, "BCM57782"); in tg3_read_vpd()
15781 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_read_vpd()
15782 strcpy(tp->board_part_number, "BCM57786"); in tg3_read_vpd()
15785 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_read_vpd()
15786 strcpy(tp->board_part_number, "BCM95906"); in tg3_read_vpd()
15789 strcpy(tp->board_part_number, "none"); in tg3_read_vpd()
15793 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) in tg3_fw_img_is_valid() argument
15797 if (tg3_nvram_read(tp, offset, &val) || in tg3_fw_img_is_valid()
15799 tg3_nvram_read(tp, offset + 4, &val) || in tg3_fw_img_is_valid()
15806 static void tg3_read_bc_ver(struct tg3 *tp) in tg3_read_bc_ver() argument
15812 if (tg3_nvram_read(tp, 0xc, &offset) || in tg3_read_bc_ver()
15813 tg3_nvram_read(tp, 0x4, &start)) in tg3_read_bc_ver()
15816 offset = tg3_nvram_logical_addr(tp, offset); in tg3_read_bc_ver()
15818 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_bc_ver()
15822 if (tg3_nvram_read(tp, offset + 4, &val)) in tg3_read_bc_ver()
15829 dst_off = strlen(tp->fw_ver); in tg3_read_bc_ver()
15833 tg3_nvram_read(tp, offset + 8, &ver_offset)) in tg3_read_bc_ver()
15839 if (tg3_nvram_read_be32(tp, offset + i, &v)) in tg3_read_bc_ver()
15842 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); in tg3_read_bc_ver()
15847 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) in tg3_read_bc_ver()
15853 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, in tg3_read_bc_ver()
15858 static void tg3_read_hwsb_ver(struct tg3 *tp) in tg3_read_hwsb_ver() argument
15863 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) in tg3_read_hwsb_ver()
15871 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); in tg3_read_hwsb_ver()
15874 static void tg3_read_sb_ver(struct tg3 *tp, u32 val) in tg3_read_sb_ver() argument
15878 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); in tg3_read_sb_ver()
15906 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_sb_ver()
15918 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15919 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, in tg3_read_sb_ver()
15923 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15925 tp->fw_ver[offset] = 'a' + build - 1; in tg3_read_sb_ver()
15929 static void tg3_read_mgmtfw_ver(struct tg3 *tp) in tg3_read_mgmtfw_ver() argument
15937 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_mgmtfw_ver()
15947 if (!tg3_flag(tp, 5705_PLUS)) in tg3_read_mgmtfw_ver()
15949 else if (tg3_nvram_read(tp, offset - 4, &start)) in tg3_read_mgmtfw_ver()
15952 if (tg3_nvram_read(tp, offset + 4, &offset) || in tg3_read_mgmtfw_ver()
15953 !tg3_fw_img_is_valid(tp, offset) || in tg3_read_mgmtfw_ver()
15954 tg3_nvram_read(tp, offset + 8, &val)) in tg3_read_mgmtfw_ver()
15959 vlen = strlen(tp->fw_ver); in tg3_read_mgmtfw_ver()
15961 tp->fw_ver[vlen++] = ','; in tg3_read_mgmtfw_ver()
15962 tp->fw_ver[vlen++] = ' '; in tg3_read_mgmtfw_ver()
15966 if (tg3_nvram_read_be32(tp, offset, &v)) in tg3_read_mgmtfw_ver()
15972 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); in tg3_read_mgmtfw_ver()
15976 memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); in tg3_read_mgmtfw_ver()
15981 static void tg3_probe_ncsi(struct tg3 *tp) in tg3_probe_ncsi() argument
15985 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_probe_ncsi()
15989 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_probe_ncsi()
15993 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) in tg3_probe_ncsi()
15994 tg3_flag_set(tp, APE_HAS_NCSI); in tg3_probe_ncsi()
15997 static void tg3_read_dash_ver(struct tg3 *tp) in tg3_read_dash_ver() argument
16003 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); in tg3_read_dash_ver()
16005 if (tg3_flag(tp, APE_HAS_NCSI)) in tg3_read_dash_ver()
16007 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725) in tg3_read_dash_ver()
16012 vlen = strlen(tp->fw_ver); in tg3_read_dash_ver()
16014 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", in tg3_read_dash_ver()
16022 static void tg3_read_otp_ver(struct tg3 *tp) in tg3_read_otp_ver() argument
16026 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_read_otp_ver()
16029 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) && in tg3_read_otp_ver()
16030 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) && in tg3_read_otp_ver()
16042 vlen = strlen(tp->fw_ver); in tg3_read_otp_ver()
16043 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver); in tg3_read_otp_ver()
16047 static void tg3_read_fw_ver(struct tg3 *tp) in tg3_read_fw_ver() argument
16052 if (tp->fw_ver[0] != 0) in tg3_read_fw_ver()
16055 if (tg3_flag(tp, NO_NVRAM)) { in tg3_read_fw_ver()
16056 strcat(tp->fw_ver, "sb"); in tg3_read_fw_ver()
16057 tg3_read_otp_ver(tp); in tg3_read_fw_ver()
16061 if (tg3_nvram_read(tp, 0, &val)) in tg3_read_fw_ver()
16065 tg3_read_bc_ver(tp); in tg3_read_fw_ver()
16067 tg3_read_sb_ver(tp, val); in tg3_read_fw_ver()
16069 tg3_read_hwsb_ver(tp); in tg3_read_fw_ver()
16071 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_read_fw_ver()
16072 if (tg3_flag(tp, ENABLE_APE)) { in tg3_read_fw_ver()
16073 tg3_probe_ncsi(tp); in tg3_read_fw_ver()
16075 tg3_read_dash_ver(tp); in tg3_read_fw_ver()
16077 tg3_read_mgmtfw_ver(tp); in tg3_read_fw_ver()
16081 tp->fw_ver[TG3_VER_SIZE - 1] = 0; in tg3_read_fw_ver()
16084 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) in tg3_rx_ret_ring_size() argument
16086 if (tg3_flag(tp, LRG_PROD_RING_CAP)) in tg3_rx_ret_ring_size()
16088 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) in tg3_rx_ret_ring_size()
16101 static struct pci_dev *tg3_find_peer(struct tg3 *tp) in tg3_find_peer() argument
16104 unsigned int func, devnr = tp->pdev->devfn & ~7; in tg3_find_peer()
16107 peer = pci_get_slot(tp->pdev->bus, devnr | func); in tg3_find_peer()
16108 if (peer && peer != tp->pdev) in tg3_find_peer()
16116 peer = tp->pdev; in tg3_find_peer()
16129 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg) in tg3_detect_asic_rev() argument
16131 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; in tg3_detect_asic_rev()
16132 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) { in tg3_detect_asic_rev()
16138 tg3_flag_set(tp, CPMU_PRESENT); in tg3_detect_asic_rev()
16140 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_detect_asic_rev()
16141 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_detect_asic_rev()
16142 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_detect_asic_rev()
16143 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_detect_asic_rev()
16144 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_detect_asic_rev()
16145 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_detect_asic_rev()
16146 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_detect_asic_rev()
16147 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_detect_asic_rev()
16148 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_detect_asic_rev()
16149 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_detect_asic_rev()
16150 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) in tg3_detect_asic_rev()
16152 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || in tg3_detect_asic_rev()
16153 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || in tg3_detect_asic_rev()
16154 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || in tg3_detect_asic_rev()
16155 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || in tg3_detect_asic_rev()
16156 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || in tg3_detect_asic_rev()
16157 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || in tg3_detect_asic_rev()
16158 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || in tg3_detect_asic_rev()
16159 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || in tg3_detect_asic_rev()
16160 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || in tg3_detect_asic_rev()
16161 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_detect_asic_rev()
16166 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id); in tg3_detect_asic_rev()
16172 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW) in tg3_detect_asic_rev()
16173 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; in tg3_detect_asic_rev()
16175 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0) in tg3_detect_asic_rev()
16176 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0; in tg3_detect_asic_rev()
16178 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_detect_asic_rev()
16179 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_detect_asic_rev()
16180 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_detect_asic_rev()
16181 tg3_flag_set(tp, 5717_PLUS); in tg3_detect_asic_rev()
16183 if (tg3_asic_rev(tp) == ASIC_REV_57765 || in tg3_detect_asic_rev()
16184 tg3_asic_rev(tp) == ASIC_REV_57766) in tg3_detect_asic_rev()
16185 tg3_flag_set(tp, 57765_CLASS); in tg3_detect_asic_rev()
16187 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) || in tg3_detect_asic_rev()
16188 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_detect_asic_rev()
16189 tg3_flag_set(tp, 57765_PLUS); in tg3_detect_asic_rev()
16192 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_detect_asic_rev()
16193 tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_detect_asic_rev()
16194 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_detect_asic_rev()
16195 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_detect_asic_rev()
16196 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_detect_asic_rev()
16197 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_detect_asic_rev()
16198 tg3_flag(tp, 57765_PLUS)) in tg3_detect_asic_rev()
16199 tg3_flag_set(tp, 5755_PLUS); in tg3_detect_asic_rev()
16201 if (tg3_asic_rev(tp) == ASIC_REV_5780 || in tg3_detect_asic_rev()
16202 tg3_asic_rev(tp) == ASIC_REV_5714) in tg3_detect_asic_rev()
16203 tg3_flag_set(tp, 5780_CLASS); in tg3_detect_asic_rev()
16205 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_detect_asic_rev()
16206 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_detect_asic_rev()
16207 tg3_asic_rev(tp) == ASIC_REV_5906 || in tg3_detect_asic_rev()
16208 tg3_flag(tp, 5755_PLUS) || in tg3_detect_asic_rev()
16209 tg3_flag(tp, 5780_CLASS)) in tg3_detect_asic_rev()
16210 tg3_flag_set(tp, 5750_PLUS); in tg3_detect_asic_rev()
16212 if (tg3_asic_rev(tp) == ASIC_REV_5705 || in tg3_detect_asic_rev()
16213 tg3_flag(tp, 5750_PLUS)) in tg3_detect_asic_rev()
16214 tg3_flag_set(tp, 5705_PLUS); in tg3_detect_asic_rev()
16217 static bool tg3_10_100_only_device(struct tg3 *tp, in tg3_10_100_only_device() argument
16222 if ((tg3_asic_rev(tp) == ASIC_REV_5703 && in tg3_10_100_only_device()
16224 (tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_10_100_only_device()
16228 if (tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_10_100_only_device()
16239 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) in tg3_get_invariants() argument
16254 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16256 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16263 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16265 tp->misc_host_ctrl |= (misc_ctrl_reg & in tg3_get_invariants()
16267 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16268 tp->misc_host_ctrl); in tg3_get_invariants()
16270 tg3_detect_asic_rev(tp, misc_ctrl_reg); in tg3_get_invariants()
16289 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) || in tg3_get_invariants()
16290 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) { in tg3_get_invariants()
16322 tp->pdev->bus->number)) { in tg3_get_invariants()
16323 tg3_flag_set(tp, ICH_WORKAROUND); in tg3_get_invariants()
16330 if (tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_get_invariants()
16352 tp->pdev->bus->number) && in tg3_get_invariants()
16354 tp->pdev->bus->number)) { in tg3_get_invariants()
16355 tg3_flag_set(tp, 5701_DMA_BUG); in tg3_get_invariants()
16368 if (tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16369 tg3_flag_set(tp, 40BIT_DMA_BUG); in tg3_get_invariants()
16370 tp->msi_cap = tp->pdev->msi_cap; in tg3_get_invariants()
16380 tp->pdev->bus->number) && in tg3_get_invariants()
16382 tp->pdev->bus->number)) { in tg3_get_invariants()
16383 tg3_flag_set(tp, 40BIT_DMA_BUG); in tg3_get_invariants()
16390 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_invariants()
16391 tg3_asic_rev(tp) == ASIC_REV_5714) in tg3_get_invariants()
16392 tp->pdev_peer = tg3_find_peer(tp); in tg3_get_invariants()
16395 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0) in tg3_get_invariants()
16397 else if (tg3_flag(tp, 57765_PLUS)) in tg3_get_invariants()
16398 tg3_flag_set(tp, HW_TSO_3); in tg3_get_invariants()
16399 else if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16400 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16401 tg3_flag_set(tp, HW_TSO_2); in tg3_get_invariants()
16402 else if (tg3_flag(tp, 5750_PLUS)) { in tg3_get_invariants()
16403 tg3_flag_set(tp, HW_TSO_1); in tg3_get_invariants()
16404 tg3_flag_set(tp, TSO_BUG); in tg3_get_invariants()
16405 if (tg3_asic_rev(tp) == ASIC_REV_5750 && in tg3_get_invariants()
16406 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2) in tg3_get_invariants()
16407 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16408 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_get_invariants()
16409 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_get_invariants()
16410 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_get_invariants()
16411 tg3_flag_set(tp, FW_TSO); in tg3_get_invariants()
16412 tg3_flag_set(tp, TSO_BUG); in tg3_get_invariants()
16413 if (tg3_asic_rev(tp) == ASIC_REV_5705) in tg3_get_invariants()
16414 tp->fw_needed = FIRMWARE_TG3TSO5; in tg3_get_invariants()
16416 tp->fw_needed = FIRMWARE_TG3TSO; in tg3_get_invariants()
16420 if (tg3_flag(tp, HW_TSO_1) || in tg3_get_invariants()
16421 tg3_flag(tp, HW_TSO_2) || in tg3_get_invariants()
16422 tg3_flag(tp, HW_TSO_3) || in tg3_get_invariants()
16423 tg3_flag(tp, FW_TSO)) { in tg3_get_invariants()
16428 tg3_flag_set(tp, TSO_CAPABLE); in tg3_get_invariants()
16430 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16431 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16432 tp->fw_needed = NULL; in tg3_get_invariants()
16435 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) in tg3_get_invariants()
16436 tp->fw_needed = FIRMWARE_TG3; in tg3_get_invariants()
16438 if (tg3_asic_rev(tp) == ASIC_REV_57766) in tg3_get_invariants()
16439 tp->fw_needed = FIRMWARE_TG357766; in tg3_get_invariants()
16441 tp->irq_max = 1; in tg3_get_invariants()
16443 if (tg3_flag(tp, 5750_PLUS)) { in tg3_get_invariants()
16444 tg3_flag_set(tp, SUPPORT_MSI); in tg3_get_invariants()
16445 if (tg3_chip_rev(tp) == CHIPREV_5750_AX || in tg3_get_invariants()
16446 tg3_chip_rev(tp) == CHIPREV_5750_BX || in tg3_get_invariants()
16447 (tg3_asic_rev(tp) == ASIC_REV_5714 && in tg3_get_invariants()
16448 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 && in tg3_get_invariants()
16449 tp->pdev_peer == tp->pdev)) in tg3_get_invariants()
16450 tg3_flag_clear(tp, SUPPORT_MSI); in tg3_get_invariants()
16452 if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16453 tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16454 tg3_flag_set(tp, 1SHOT_MSI); in tg3_get_invariants()
16457 if (tg3_flag(tp, 57765_PLUS)) { in tg3_get_invariants()
16458 tg3_flag_set(tp, SUPPORT_MSIX); in tg3_get_invariants()
16459 tp->irq_max = TG3_IRQ_MAX_VECS; in tg3_get_invariants()
16463 tp->txq_max = 1; in tg3_get_invariants()
16464 tp->rxq_max = 1; in tg3_get_invariants()
16465 if (tp->irq_max > 1) { in tg3_get_invariants()
16466 tp->rxq_max = TG3_RSS_MAX_NUM_QS; in tg3_get_invariants()
16467 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS); in tg3_get_invariants()
16469 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16470 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_get_invariants()
16471 tp->txq_max = tp->irq_max - 1; in tg3_get_invariants()
16474 if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16475 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16476 tg3_flag_set(tp, SHORT_DMA_BUG); in tg3_get_invariants()
16478 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_get_invariants()
16479 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; in tg3_get_invariants()
16481 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16482 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16483 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_get_invariants()
16484 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16485 tg3_flag_set(tp, LRG_PROD_RING_CAP); in tg3_get_invariants()
16487 if (tg3_flag(tp, 57765_PLUS) && in tg3_get_invariants()
16488 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0) in tg3_get_invariants()
16489 tg3_flag_set(tp, USE_JUMBO_BDFLAG); in tg3_get_invariants()
16491 if (!tg3_flag(tp, 5705_PLUS) || in tg3_get_invariants()
16492 tg3_flag(tp, 5780_CLASS) || in tg3_get_invariants()
16493 tg3_flag(tp, USE_JUMBO_BDFLAG)) in tg3_get_invariants()
16494 tg3_flag_set(tp, JUMBO_CAPABLE); in tg3_get_invariants()
16496 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16499 if (pci_is_pcie(tp->pdev)) { in tg3_get_invariants()
16502 tg3_flag_set(tp, PCI_EXPRESS); in tg3_get_invariants()
16504 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); in tg3_get_invariants()
16506 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16507 tg3_flag_clear(tp, HW_TSO_2); in tg3_get_invariants()
16508 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16510 if (tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_get_invariants()
16511 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_get_invariants()
16512 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 || in tg3_get_invariants()
16513 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1) in tg3_get_invariants()
16514 tg3_flag_set(tp, CLKREQ_BUG); in tg3_get_invariants()
16515 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) { in tg3_get_invariants()
16516 tg3_flag_set(tp, L1PLLPD_EN); in tg3_get_invariants()
16518 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_get_invariants()
16523 tg3_flag_set(tp, PCI_EXPRESS); in tg3_get_invariants()
16524 } else if (!tg3_flag(tp, 5705_PLUS) || in tg3_get_invariants()
16525 tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16526 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); in tg3_get_invariants()
16527 if (!tp->pcix_cap) { in tg3_get_invariants()
16528 dev_err(&tp->pdev->dev, in tg3_get_invariants()
16534 tg3_flag_set(tp, PCIX_MODE); in tg3_get_invariants()
16544 !tg3_flag(tp, PCI_EXPRESS)) in tg3_get_invariants()
16545 tg3_flag_set(tp, MBOX_WRITE_REORDER); in tg3_get_invariants()
16547 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_get_invariants()
16548 &tp->pci_cacheline_sz); in tg3_get_invariants()
16549 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16550 &tp->pci_lat_timer); in tg3_get_invariants()
16551 if (tg3_asic_rev(tp) == ASIC_REV_5703 && in tg3_get_invariants()
16552 tp->pci_lat_timer < 64) { in tg3_get_invariants()
16553 tp->pci_lat_timer = 64; in tg3_get_invariants()
16554 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16555 tp->pci_lat_timer); in tg3_get_invariants()
16561 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) { in tg3_get_invariants()
16565 tg3_flag_set(tp, TXD_MBOX_HWBUG); in tg3_get_invariants()
16572 if (tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16575 tg3_flag_set(tp, PCIX_TARGET_HWBUG); in tg3_get_invariants()
16581 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16582 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16586 pci_write_config_dword(tp->pdev, in tg3_get_invariants()
16587 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16591 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16593 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16598 tg3_flag_set(tp, PCI_HIGH_SPEED); in tg3_get_invariants()
16600 tg3_flag_set(tp, PCI_32BIT); in tg3_get_invariants()
16603 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) && in tg3_get_invariants()
16606 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); in tg3_get_invariants()
16610 tp->read32 = tg3_read32; in tg3_get_invariants()
16611 tp->write32 = tg3_write32; in tg3_get_invariants()
16612 tp->read32_mbox = tg3_read32; in tg3_get_invariants()
16613 tp->write32_mbox = tg3_write32; in tg3_get_invariants()
16614 tp->write32_tx_mbox = tg3_write32; in tg3_get_invariants()
16615 tp->write32_rx_mbox = tg3_write32; in tg3_get_invariants()
16618 if (tg3_flag(tp, PCIX_TARGET_HWBUG)) in tg3_get_invariants()
16619 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16620 else if (tg3_asic_rev(tp) == ASIC_REV_5701 || in tg3_get_invariants()
16621 (tg3_flag(tp, PCI_EXPRESS) && in tg3_get_invariants()
16622 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) { in tg3_get_invariants()
16630 tp->write32 = tg3_write_flush_reg32; in tg3_get_invariants()
16633 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) { in tg3_get_invariants()
16634 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_get_invariants()
16635 if (tg3_flag(tp, MBOX_WRITE_REORDER)) in tg3_get_invariants()
16636 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16639 if (tg3_flag(tp, ICH_WORKAROUND)) { in tg3_get_invariants()
16640 tp->read32 = tg3_read_indirect_reg32; in tg3_get_invariants()
16641 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16642 tp->read32_mbox = tg3_read_indirect_mbox; in tg3_get_invariants()
16643 tp->write32_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16644 tp->write32_tx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16645 tp->write32_rx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16647 iounmap(tp->regs); in tg3_get_invariants()
16648 tp->regs = NULL; in tg3_get_invariants()
16650 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16652 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16654 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16655 tp->read32_mbox = tg3_read32_mbox_5906; in tg3_get_invariants()
16656 tp->write32_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16657 tp->write32_tx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16658 tp->write32_rx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16661 if (tp->write32 == tg3_write_indirect_reg32 || in tg3_get_invariants()
16662 (tg3_flag(tp, PCIX_MODE) && in tg3_get_invariants()
16663 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16664 tg3_asic_rev(tp) == ASIC_REV_5701))) in tg3_get_invariants()
16665 tg3_flag_set(tp, SRAM_USE_CONFIG); in tg3_get_invariants()
16675 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; in tg3_get_invariants()
16676 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_invariants()
16677 tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16678 if (tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16679 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16680 tp->pcix_cap + PCI_X_STATUS, in tg3_get_invariants()
16682 tp->pci_fn = val & 0x7; in tg3_get_invariants()
16684 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16685 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16686 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_get_invariants()
16687 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); in tg3_get_invariants()
16691 if (tg3_asic_rev(tp) == ASIC_REV_5717) in tg3_get_invariants()
16692 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0; in tg3_get_invariants()
16694 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> in tg3_get_invariants()
16698 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) { in tg3_get_invariants()
16699 tp->write32_tx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16700 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16711 tg3_get_eeprom_hw_cfg(tp); in tg3_get_invariants()
16713 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) { in tg3_get_invariants()
16714 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16715 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16716 tp->fw_needed = NULL; in tg3_get_invariants()
16719 if (tg3_flag(tp, ENABLE_APE)) { in tg3_get_invariants()
16726 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16729 tg3_ape_lock_init(tp); in tg3_get_invariants()
16730 tp->ape_hb_interval = in tg3_get_invariants()
16739 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; in tg3_get_invariants()
16740 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16741 tg3_flag(tp, EEPROM_WRITE_PROT)) in tg3_get_invariants()
16742 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_get_invariants()
16747 else if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_get_invariants()
16748 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; in tg3_get_invariants()
16750 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_get_invariants()
16751 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_get_invariants()
16752 tg3_flag(tp, 57765_CLASS)) in tg3_get_invariants()
16753 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16755 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_get_invariants()
16756 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_get_invariants()
16758 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16759 if (tg3_flag(tp, IS_NIC)) in tg3_get_invariants()
16761 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | in tg3_get_invariants()
16765 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16766 tp->grc_local_ctrl |= in tg3_get_invariants()
16770 tg3_pwrsrc_switch_to_vmain(tp); in tg3_get_invariants()
16775 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) in tg3_get_invariants()
16776 tg3_flag_set(tp, JUMBO_RING_ENABLE); in tg3_get_invariants()
16779 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16780 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_get_invariants()
16781 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 || in tg3_get_invariants()
16782 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) { in tg3_get_invariants()
16783 tg3_flag_clear(tp, WOL_SPEED_100MB); in tg3_get_invariants()
16785 tg3_flag_set(tp, WOL_SPEED_100MB); in tg3_get_invariants()
16788 if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16789 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_get_invariants()
16792 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16793 (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_get_invariants()
16794 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) && in tg3_get_invariants()
16795 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) || in tg3_get_invariants()
16796 (tp->phy_flags & TG3_PHYFLG_IS_FET) || in tg3_get_invariants()
16797 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_get_invariants()
16798 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; in tg3_get_invariants()
16800 if (tg3_chip_rev(tp) == CHIPREV_5703_AX || in tg3_get_invariants()
16801 tg3_chip_rev(tp) == CHIPREV_5704_AX) in tg3_get_invariants()
16802 tp->phy_flags |= TG3_PHYFLG_ADC_BUG; in tg3_get_invariants()
16803 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) in tg3_get_invariants()
16804 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; in tg3_get_invariants()
16806 if (tg3_flag(tp, 5705_PLUS) && in tg3_get_invariants()
16807 !(tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_get_invariants()
16808 tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_get_invariants()
16809 tg3_asic_rev(tp) != ASIC_REV_57780 && in tg3_get_invariants()
16810 !tg3_flag(tp, 57765_PLUS)) { in tg3_get_invariants()
16811 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_get_invariants()
16812 tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_get_invariants()
16813 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_get_invariants()
16814 tg3_asic_rev(tp) == ASIC_REV_5761) { in tg3_get_invariants()
16815 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && in tg3_get_invariants()
16816 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) in tg3_get_invariants()
16817 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; in tg3_get_invariants()
16818 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) in tg3_get_invariants()
16819 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; in tg3_get_invariants()
16821 tp->phy_flags |= TG3_PHYFLG_BER_BUG; in tg3_get_invariants()
16824 if (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_get_invariants()
16825 tg3_chip_rev(tp) != CHIPREV_5784_AX) { in tg3_get_invariants()
16826 tp->phy_otp = tg3_read_otp_phycfg(tp); in tg3_get_invariants()
16827 if (tp->phy_otp == 0) in tg3_get_invariants()
16828 tp->phy_otp = TG3_OTP_DEFAULT; in tg3_get_invariants()
16831 if (tg3_flag(tp, CPMU_PRESENT)) in tg3_get_invariants()
16832 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; in tg3_get_invariants()
16834 tp->mi_mode = MAC_MI_MODE_BASE; in tg3_get_invariants()
16836 tp->coalesce_mode = 0; in tg3_get_invariants()
16837 if (tg3_chip_rev(tp) != CHIPREV_5700_AX && in tg3_get_invariants()
16838 tg3_chip_rev(tp) != CHIPREV_5700_BX) in tg3_get_invariants()
16839 tp->coalesce_mode |= HOSTCC_MODE_32BYTE; in tg3_get_invariants()
16842 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16843 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_get_invariants()
16844 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_get_invariants()
16845 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) { in tg3_get_invariants()
16846 tp->coalesce_mode |= HOSTCC_MODE_ATTN; in tg3_get_invariants()
16847 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; in tg3_get_invariants()
16850 if (tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_get_invariants()
16851 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_get_invariants()
16852 tg3_flag_set(tp, USE_PHYLIB); in tg3_get_invariants()
16854 err = tg3_mdio_init(tp); in tg3_get_invariants()
16860 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_get_invariants()
16861 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16870 tw32(GRC_MODE, val | tp->grc_mode); in tg3_get_invariants()
16872 tg3_switch_clocks(tp); in tg3_get_invariants()
16880 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16883 !tg3_flag(tp, PCIX_TARGET_HWBUG)) { in tg3_get_invariants()
16884 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_get_invariants()
16885 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 || in tg3_get_invariants()
16886 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 || in tg3_get_invariants()
16887 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) { in tg3_get_invariants()
16894 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; in tg3_get_invariants()
16900 tg3_flag_set(tp, PCIX_TARGET_HWBUG); in tg3_get_invariants()
16905 tg3_nvram_init(tp); in tg3_get_invariants()
16908 if (tg3_asic_rev(tp) == ASIC_REV_57766 && in tg3_get_invariants()
16909 !tg3_flag(tp, NO_NVRAM)) in tg3_get_invariants()
16910 tp->fw_needed = NULL; in tg3_get_invariants()
16915 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_get_invariants()
16918 tg3_flag_set(tp, IS_5788); in tg3_get_invariants()
16920 if (!tg3_flag(tp, IS_5788) && in tg3_get_invariants()
16921 tg3_asic_rev(tp) != ASIC_REV_5700) in tg3_get_invariants()
16922 tg3_flag_set(tp, TAGGED_STATUS); in tg3_get_invariants()
16923 if (tg3_flag(tp, TAGGED_STATUS)) { in tg3_get_invariants()
16924 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | in tg3_get_invariants()
16927 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; in tg3_get_invariants()
16928 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16929 tp->misc_host_ctrl); in tg3_get_invariants()
16933 if (tg3_flag(tp, ENABLE_APE)) in tg3_get_invariants()
16934 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_get_invariants()
16936 tp->mac_mode = 0; in tg3_get_invariants()
16938 if (tg3_10_100_only_device(tp, ent)) in tg3_get_invariants()
16939 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; in tg3_get_invariants()
16941 err = tg3_phy_probe(tp); in tg3_get_invariants()
16943 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); in tg3_get_invariants()
16945 tg3_mdio_fini(tp); in tg3_get_invariants()
16948 tg3_read_vpd(tp); in tg3_get_invariants()
16949 tg3_read_fw_ver(tp); in tg3_get_invariants()
16951 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_get_invariants()
16952 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16954 if (tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_get_invariants()
16955 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16957 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16964 if (tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_get_invariants()
16965 tg3_flag_set(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16967 tg3_flag_clear(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16973 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_get_invariants()
16974 tg3_asic_rev(tp) == ASIC_REV_5701 && in tg3_get_invariants()
16975 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_get_invariants()
16976 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16977 tg3_flag_set(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16981 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_get_invariants()
16982 tg3_flag_set(tp, POLL_SERDES); in tg3_get_invariants()
16984 tg3_flag_clear(tp, POLL_SERDES); in tg3_get_invariants()
16986 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF)) in tg3_get_invariants()
16987 tg3_flag_set(tp, POLL_CPMU_LINK); in tg3_get_invariants()
16989 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; in tg3_get_invariants()
16990 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; in tg3_get_invariants()
16991 if (tg3_asic_rev(tp) == ASIC_REV_5701 && in tg3_get_invariants()
16992 tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16993 tp->rx_offset = NET_SKB_PAD; in tg3_get_invariants()
16995 tp->rx_copy_thresh = ~(u16)0; in tg3_get_invariants()
16999 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; in tg3_get_invariants()
17000 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; in tg3_get_invariants()
17001 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; in tg3_get_invariants()
17003 tp->rx_std_max_post = tp->rx_std_ring_mask + 1; in tg3_get_invariants()
17008 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_get_invariants()
17009 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_get_invariants()
17010 tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_get_invariants()
17011 tp->rx_std_max_post = 8; in tg3_get_invariants()
17013 if (tg3_flag(tp, ASPM_WORKAROUND)) in tg3_get_invariants()
17014 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
17020 static int tg3_get_device_address(struct tg3 *tp, u8 *addr) in tg3_get_device_address() argument
17026 if (!eth_platform_get_mac_address(&tp->pdev->dev, addr)) in tg3_get_device_address()
17029 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_get_device_address()
17030 err = ssb_gige_get_macaddr(tp->pdev, addr); in tg3_get_device_address()
17036 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_device_address()
17037 tg3_flag(tp, 5780_CLASS)) { in tg3_get_device_address()
17040 if (tg3_nvram_lock(tp)) in tg3_get_device_address()
17043 tg3_nvram_unlock(tp); in tg3_get_device_address()
17044 } else if (tg3_flag(tp, 5717_PLUS)) { in tg3_get_device_address()
17045 if (tp->pci_fn & 1) in tg3_get_device_address()
17047 if (tp->pci_fn > 1) in tg3_get_device_address()
17049 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_device_address()
17053 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); in tg3_get_device_address()
17058 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); in tg3_get_device_address()
17069 if (!tg3_flag(tp, NO_NVRAM) && in tg3_get_device_address()
17070 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && in tg3_get_device_address()
17071 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { in tg3_get_device_address()
17097 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val) in tg3_calc_dma_bndry() argument
17103 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); in tg3_calc_dma_bndry()
17112 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_calc_dma_bndry()
17113 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_calc_dma_bndry()
17114 !tg3_flag(tp, PCI_EXPRESS)) in tg3_calc_dma_bndry()
17127 if (tg3_flag(tp, 57765_PLUS)) { in tg3_calc_dma_bndry()
17146 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { in tg3_calc_dma_bndry()
17171 } else if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_calc_dma_bndry()
17238 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, in tg3_do_test_dma() argument
17289 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, in tg3_do_test_dma()
17291 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_do_test_dma()
17293 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_do_test_dma()
17326 static int tg3_test_dma(struct tg3 *tp) in tg3_test_dma() argument
17332 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, in tg3_test_dma()
17339 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | in tg3_test_dma()
17342 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); in tg3_test_dma()
17344 if (tg3_flag(tp, 57765_PLUS)) in tg3_test_dma()
17347 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_test_dma()
17349 tp->dma_rwctrl |= 0x00180000; in tg3_test_dma()
17350 } else if (!tg3_flag(tp, PCIX_MODE)) { in tg3_test_dma()
17351 if (tg3_asic_rev(tp) == ASIC_REV_5705 || in tg3_test_dma()
17352 tg3_asic_rev(tp) == ASIC_REV_5750) in tg3_test_dma()
17353 tp->dma_rwctrl |= 0x003f0000; in tg3_test_dma()
17355 tp->dma_rwctrl |= 0x003f000f; in tg3_test_dma()
17357 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_test_dma()
17358 tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_test_dma()
17366 if (tg3_flag(tp, 40BIT_DMA_BUG) && in tg3_test_dma()
17367 tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_test_dma()
17368 tp->dma_rwctrl |= 0x8000; in tg3_test_dma()
17370 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17372 if (tg3_asic_rev(tp) == ASIC_REV_5703) in tg3_test_dma()
17375 tp->dma_rwctrl |= in tg3_test_dma()
17379 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) { in tg3_test_dma()
17381 tp->dma_rwctrl |= 0x00144000; in tg3_test_dma()
17382 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_test_dma()
17384 tp->dma_rwctrl |= 0x00148000; in tg3_test_dma()
17386 tp->dma_rwctrl |= 0x001b000f; in tg3_test_dma()
17389 if (tg3_flag(tp, ONE_DMA_AT_ONCE)) in tg3_test_dma()
17390 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17392 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_test_dma()
17393 tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_test_dma()
17394 tp->dma_rwctrl &= 0xfffffff0; in tg3_test_dma()
17396 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_test_dma()
17397 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_test_dma()
17399 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; in tg3_test_dma()
17411 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; in tg3_test_dma()
17414 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17417 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_test_dma()
17418 tg3_asic_rev(tp) != ASIC_REV_5701) in tg3_test_dma()
17424 saved_dma_rwctrl = tp->dma_rwctrl; in tg3_test_dma()
17425 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17426 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17435 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true); in tg3_test_dma()
17437 dev_err(&tp->pdev->dev, in tg3_test_dma()
17444 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false); in tg3_test_dma()
17446 dev_err(&tp->pdev->dev, "%s: Buffer read failed. " in tg3_test_dma()
17456 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17458 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17459 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17460 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17463 dev_err(&tp->pdev->dev, in tg3_test_dma()
17477 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17484 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17485 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17488 tp->dma_rwctrl = saved_dma_rwctrl; in tg3_test_dma()
17491 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17495 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); in tg3_test_dma()
17500 static void tg3_init_bufmgr_config(struct tg3 *tp) in tg3_init_bufmgr_config() argument
17502 if (tg3_flag(tp, 57765_PLUS)) { in tg3_init_bufmgr_config()
17503 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17505 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17507 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17510 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17512 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17514 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17516 } else if (tg3_flag(tp, 5705_PLUS)) { in tg3_init_bufmgr_config()
17517 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17519 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17521 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17523 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_init_bufmgr_config()
17524 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17526 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17530 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17532 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17534 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17537 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17539 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17541 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17544 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17546 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17548 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17552 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; in tg3_init_bufmgr_config()
17553 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; in tg3_init_bufmgr_config()
17556 static char *tg3_phy_string(struct tg3 *tp) in tg3_phy_string() argument
17558 switch (tp->phy_id & TG3_PHY_ID_MASK) { in tg3_phy_string()
17588 static char *tg3_bus_string(struct tg3 *tp, char *str) in tg3_bus_string() argument
17590 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_bus_string()
17593 } else if (tg3_flag(tp, PCIX_MODE)) { in tg3_bus_string()
17612 if (tg3_flag(tp, PCI_HIGH_SPEED)) in tg3_bus_string()
17617 if (tg3_flag(tp, PCI_32BIT)) in tg3_bus_string()
17624 static void tg3_init_coal(struct tg3 *tp) in tg3_init_coal() argument
17626 struct ethtool_coalesce *ec = &tp->coal; in tg3_init_coal()
17640 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | in tg3_init_coal()
17648 if (tg3_flag(tp, 5705_PLUS)) { in tg3_init_coal()
17659 struct tg3 *tp; in tg3_init_one() local
17681 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); in tg3_init_one()
17689 tp = netdev_priv(dev); in tg3_init_one()
17690 tp->pdev = pdev; in tg3_init_one()
17691 tp->dev = dev; in tg3_init_one()
17692 tp->rx_mode = TG3_DEF_RX_MODE; in tg3_init_one()
17693 tp->tx_mode = TG3_DEF_TX_MODE; in tg3_init_one()
17694 tp->irq_sync = 1; in tg3_init_one()
17695 tp->pcierr_recovery = false; in tg3_init_one()
17698 tp->msg_enable = tg3_debug; in tg3_init_one()
17700 tp->msg_enable = TG3_DEF_MSG_ENABLE; in tg3_init_one()
17703 tg3_flag_set(tp, IS_SSB_CORE); in tg3_init_one()
17705 tg3_flag_set(tp, FLUSH_POSTED_WRITES); in tg3_init_one()
17707 tg3_flag_set(tp, ONE_DMA_AT_ONCE); in tg3_init_one()
17709 tg3_flag_set(tp, USE_PHYLIB); in tg3_init_one()
17710 tg3_flag_set(tp, ROBOSWITCH); in tg3_init_one()
17713 tg3_flag_set(tp, RGMII_MODE); in tg3_init_one()
17720 tp->misc_host_ctrl = in tg3_init_one()
17732 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | in tg3_init_one()
17735 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; in tg3_init_one()
17737 spin_lock_init(&tp->lock); in tg3_init_one()
17738 spin_lock_init(&tp->indirect_lock); in tg3_init_one()
17739 INIT_WORK(&tp->reset_task, tg3_reset_task); in tg3_init_one()
17741 tp->regs = pci_ioremap_bar(pdev, BAR_0); in tg3_init_one()
17742 if (!tp->regs) { in tg3_init_one()
17748 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_init_one()
17749 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || in tg3_init_one()
17750 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || in tg3_init_one()
17751 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || in tg3_init_one()
17752 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_init_one()
17753 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_init_one()
17754 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_init_one()
17755 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_init_one()
17756 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_init_one()
17757 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_init_one()
17758 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_init_one()
17759 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_init_one()
17760 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_init_one()
17761 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_init_one()
17762 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) { in tg3_init_one()
17763 tg3_flag_set(tp, ENABLE_APE); in tg3_init_one()
17764 tp->aperegs = pci_ioremap_bar(pdev, BAR_2); in tg3_init_one()
17765 if (!tp->aperegs) { in tg3_init_one()
17773 tp->rx_pending = TG3_DEF_RX_RING_PENDING; in tg3_init_one()
17774 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; in tg3_init_one()
17781 err = tg3_get_invariants(tp, ent); in tg3_init_one()
17794 if (tg3_flag(tp, IS_5788)) in tg3_init_one()
17796 else if (tg3_flag(tp, 40BIT_DMA_BUG)) { in tg3_init_one()
17827 tg3_init_bufmgr_config(tp); in tg3_init_one()
17832 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) { in tg3_init_one()
17835 if (tg3_flag(tp, 5755_PLUS)) in tg3_init_one()
17843 if ((tg3_flag(tp, HW_TSO_1) || in tg3_init_one()
17844 tg3_flag(tp, HW_TSO_2) || in tg3_init_one()
17845 tg3_flag(tp, HW_TSO_3)) && in tg3_init_one()
17848 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { in tg3_init_one()
17851 if (tg3_flag(tp, HW_TSO_3) || in tg3_init_one()
17852 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_init_one()
17853 (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_init_one()
17854 tg3_chip_rev(tp) != CHIPREV_5784_AX) || in tg3_init_one()
17855 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_init_one()
17856 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_init_one()
17869 if (tg3_asic_rev(tp) != ASIC_REV_5780 && in tg3_init_one()
17870 !tg3_flag(tp, CPMU_PRESENT)) in tg3_init_one()
17879 dev->max_mtu = TG3_MAX_MTU(tp); in tg3_init_one()
17881 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 && in tg3_init_one()
17882 !tg3_flag(tp, TSO_CAPABLE) && in tg3_init_one()
17884 tg3_flag_set(tp, MAX_RXPEND_64); in tg3_init_one()
17885 tp->rx_pending = 63; in tg3_init_one()
17888 err = tg3_get_device_address(tp, addr); in tg3_init_one()
17899 for (i = 0; i < tp->irq_max; i++) { in tg3_init_one()
17900 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_one()
17902 tnapi->tp = tp; in tg3_init_one()
17916 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_init_one()
17944 tg3_full_lock(tp, 0); in tg3_init_one()
17946 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_init_one()
17947 tg3_full_unlock(tp); in tg3_init_one()
17950 err = tg3_test_dma(tp); in tg3_init_one()
17956 tg3_init_coal(tp); in tg3_init_one()
17960 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_init_one()
17961 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_init_one()
17962 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_init_one()
17963 tg3_flag_set(tp, PTP_CAPABLE); in tg3_init_one()
17965 tg3_timer_init(tp); in tg3_init_one()
17967 tg3_carrier_off(tp); in tg3_init_one()
17975 if (tg3_flag(tp, PTP_CAPABLE)) { in tg3_init_one()
17976 tg3_ptp_init(tp); in tg3_init_one()
17977 tp->ptp_clock = ptp_clock_register(&tp->ptp_info, in tg3_init_one()
17978 &tp->pdev->dev); in tg3_init_one()
17979 if (IS_ERR(tp->ptp_clock)) in tg3_init_one()
17980 tp->ptp_clock = NULL; in tg3_init_one()
17984 tp->board_part_number, in tg3_init_one()
17985 tg3_chip_rev_id(tp), in tg3_init_one()
17986 tg3_bus_string(tp, str), in tg3_init_one()
17989 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) { in tg3_init_one()
17992 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_init_one()
17994 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_init_one()
18001 tg3_phy_string(tp), ethtype, in tg3_init_one()
18002 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, in tg3_init_one()
18003 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); in tg3_init_one()
18008 tg3_flag(tp, USE_LINKCHG_REG) != 0, in tg3_init_one()
18009 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, in tg3_init_one()
18010 tg3_flag(tp, ENABLE_ASF) != 0, in tg3_init_one()
18011 tg3_flag(tp, TSO_CAPABLE) != 0); in tg3_init_one()
18013 tp->dma_rwctrl, in tg3_init_one()
18022 if (tp->aperegs) { in tg3_init_one()
18023 iounmap(tp->aperegs); in tg3_init_one()
18024 tp->aperegs = NULL; in tg3_init_one()
18028 if (tp->regs) { in tg3_init_one()
18029 iounmap(tp->regs); in tg3_init_one()
18030 tp->regs = NULL; in tg3_init_one()
18050 struct tg3 *tp = netdev_priv(dev); in tg3_remove_one() local
18052 tg3_ptp_fini(tp); in tg3_remove_one()
18054 release_firmware(tp->fw); in tg3_remove_one()
18056 tg3_reset_task_cancel(tp); in tg3_remove_one()
18058 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_remove_one()
18059 tg3_phy_fini(tp); in tg3_remove_one()
18060 tg3_mdio_fini(tp); in tg3_remove_one()
18064 if (tp->aperegs) { in tg3_remove_one()
18065 iounmap(tp->aperegs); in tg3_remove_one()
18066 tp->aperegs = NULL; in tg3_remove_one()
18068 if (tp->regs) { in tg3_remove_one()
18069 iounmap(tp->regs); in tg3_remove_one()
18070 tp->regs = NULL; in tg3_remove_one()
18082 struct tg3 *tp = netdev_priv(dev); in tg3_suspend() local
18089 tg3_reset_task_cancel(tp); in tg3_suspend()
18090 tg3_phy_stop(tp); in tg3_suspend()
18091 tg3_netif_stop(tp); in tg3_suspend()
18093 tg3_timer_stop(tp); in tg3_suspend()
18095 tg3_full_lock(tp, 1); in tg3_suspend()
18096 tg3_disable_ints(tp); in tg3_suspend()
18097 tg3_full_unlock(tp); in tg3_suspend()
18101 tg3_full_lock(tp, 0); in tg3_suspend()
18102 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_suspend()
18103 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_suspend()
18104 tg3_full_unlock(tp); in tg3_suspend()
18106 tg3_power_down_prepare(tp); in tg3_suspend()
18116 struct tg3 *tp = netdev_priv(dev); in tg3_resume() local
18126 tg3_full_lock(tp, 0); in tg3_resume()
18128 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_resume()
18130 tg3_flag_set(tp, INIT_COMPLETE); in tg3_resume()
18131 err = tg3_restart_hw(tp, in tg3_resume()
18132 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)); in tg3_resume()
18136 tg3_timer_start(tp); in tg3_resume()
18138 tg3_netif_start(tp); in tg3_resume()
18141 tg3_full_unlock(tp); in tg3_resume()
18144 tg3_phy_start(tp); in tg3_resume()
18157 struct tg3 *tp = netdev_priv(dev); in tg3_shutdown() local
18159 tg3_reset_task_cancel(tp); in tg3_shutdown()
18169 tg3_power_down(tp); in tg3_shutdown()
18188 struct tg3 *tp = netdev_priv(netdev); in tg3_io_error_detected() local
18194 tg3_reset_task_cancel(tp); in tg3_io_error_detected()
18199 if (!netdev || tp->pcierr_recovery || !netif_running(netdev)) in tg3_io_error_detected()
18204 tp->pcierr_recovery = true; in tg3_io_error_detected()
18206 tg3_phy_stop(tp); in tg3_io_error_detected()
18208 tg3_netif_stop(tp); in tg3_io_error_detected()
18210 tg3_timer_stop(tp); in tg3_io_error_detected()
18215 tg3_full_lock(tp, 0); in tg3_io_error_detected()
18216 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); in tg3_io_error_detected()
18217 tg3_full_unlock(tp); in tg3_io_error_detected()
18222 tg3_napi_enable(tp); in tg3_io_error_detected()
18247 struct tg3 *tp = netdev_priv(netdev); in tg3_io_slot_reset() local
18268 err = tg3_power_up(tp); in tg3_io_slot_reset()
18276 tg3_napi_enable(tp); in tg3_io_slot_reset()
18294 struct tg3 *tp = netdev_priv(netdev); in tg3_io_resume() local
18302 tg3_full_lock(tp, 0); in tg3_io_resume()
18303 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_io_resume()
18304 tg3_flag_set(tp, INIT_COMPLETE); in tg3_io_resume()
18305 err = tg3_restart_hw(tp, true); in tg3_io_resume()
18307 tg3_full_unlock(tp); in tg3_io_resume()
18314 tg3_timer_start(tp); in tg3_io_resume()
18316 tg3_netif_start(tp); in tg3_io_resume()
18318 tg3_full_unlock(tp); in tg3_io_resume()
18320 tg3_phy_start(tp); in tg3_io_resume()
18323 tp->pcierr_recovery = false; in tg3_io_resume()