Lines Matching refs:TG3_BDINFO_SIZE
9585 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; in tg3_tx_rcbs_disable()
9587 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; in tg3_tx_rcbs_disable()
9590 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; in tg3_tx_rcbs_disable()
9592 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_tx_rcbs_disable()
9594 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_tx_rcbs_disable()
9595 txrcb < limit; txrcb += TG3_BDINFO_SIZE) in tg3_tx_rcbs_disable()
9609 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) { in tg3_tx_rcbs_init()
9628 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; in tg3_rx_ret_rcbs_disable()
9630 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; in tg3_rx_ret_rcbs_disable()
9634 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; in tg3_rx_ret_rcbs_disable()
9636 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rx_ret_rcbs_disable()
9638 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rx_ret_rcbs_disable()
9639 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) in tg3_rx_ret_rcbs_disable()
9653 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) { in tg3_rx_ret_rcbs_init()