Lines Matching refs:TG3_64BIT_REG_LOW
522 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { in tg3_write_indirect_mbox()
524 TG3_64BIT_REG_LOW, val); in tg3_write_indirect_mbox()
529 TG3_64BIT_REG_LOW, val); in tg3_write_indirect_mbox()
541 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && in tg3_write_indirect_mbox()
7567 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); in tg3_interrupt()
7578 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, in tg3_interrupt()
7616 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); in tg3_interrupt_tagged()
9481 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), in tg3_set_bdinfo()
9706 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; in tg3_rings_reset()
9717 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_rings_reset()
9725 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); in tg3_rings_reset()
10250 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_reset_hw()
10270 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_reset_hw()
10463 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_reset_hw()
17896 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; in tg3_init_one()
17897 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; in tg3_init_one()
17898 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; in tg3_init_one()