Lines Matching +full:0 +full:x260000
43 #define TX_BD_TYPE (0x3f << 0)
44 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
45 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
48 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
52 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
57 #define TX_BD_LEN (0xffff << 16)
64 #define TX_OPAQUE_IDX_MASK 0x0000ffff
65 #define TX_OPAQUE_BDS_MASK 0x00ff0000
67 #define TX_OPAQUE_RING_MASK 0xff000000
84 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
92 #define TX_BD_HSIZE (0xff << 16)
97 #define TX_BD_CFA_ACTION (0xffff << 16)
101 #define TX_BD_CFA_META_MASK 0xfffffff
102 #define TX_BD_CFA_META_VID_MASK 0xfff
103 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
107 #define TX_BD_CFA_META_KEY (0xf << 28)
116 #define RX_BD_TYPE (0x3f << 0)
117 #define RX_BD_TYPE_RX_PACKET_BD 0x4
118 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
119 #define RX_BD_TYPE_RX_AGG_BD 0x6
120 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
127 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
131 #define RX_BD_LEN (0xffff << 16)
140 #define CMP_TYPE (0x3f << 0)
141 #define CMP_TYPE_TX_L2_CMP 0
155 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
156 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
157 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
158 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
159 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
166 #define TX_CMP_V (1 << 0)
168 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
178 #define TX_CMP_SQ_CONS_IDX_MASK 0x00ffffff
188 #define TX_TS_CMP_FLAGS_TS_TYPE_PM (0 << 7)
191 #define TX_TS_CMP_TS_SUB_NS (0xf << 12)
192 #define TX_TS_CMP_TS_NS_MID (0xffff << 16)
196 #define TX_TS_CMP_V (1 << 0)
212 #define RX_CMP_CMP_TYPE (0x3f << 0)
218 #define RX_CMP_FLAGS_ITYPES_MASK 0xf000
219 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
227 #define RX_CMP_LEN (0xffff << 16)
232 #define RX_CMP_V1 (1 << 0)
233 #define RX_CMP_AGG_BUFS (0x1f << 1)
235 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
237 #define RX_CMP_V3_RSS_EXT_OP_LEGACY (0xf << 12)
239 #define RX_CMP_V3_RSS_EXT_OP_NEW (0xf << 8)
241 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
243 #define RX_CMP_SUB_NS_TS (0xf << 16)
245 #define RX_CMP_METADATA1 (0xf << 28)
247 #define RX_CMP_METADATA1_TPID_SEL (0x7 << 28)
248 #define RX_CMP_METADATA1_TPID_8021Q (0x1 << 28)
249 #define RX_CMP_METADATA1_TPID_8021AD (0x0 << 28)
250 #define RX_CMP_METADATA1_VALID (0x8 << 28)
264 #define RSS_PROFILE_ID_MASK 0x1f
283 #define EXT_OP_INNER_4 0x0
284 #define EXT_OP_OUTER_4 0x2
285 #define EXT_OP_INNFL_3 0x8
286 #define EXT_OP_OUTFL_3 0xa
296 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
297 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
298 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
299 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
300 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
302 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff
303 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
304 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
307 #define RX_CMP_V (1 << 0)
308 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
310 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
311 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
312 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
313 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
314 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
315 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
316 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
317 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
318 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
319 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
320 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
321 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
322 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
323 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
324 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
325 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
326 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
327 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
328 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
329 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
330 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
331 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
332 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
333 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
334 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
335 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
336 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
337 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
339 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
341 #define RX_CMPL_METADATA0_TCI_MASK (0xffff << 16)
342 #define RX_CMPL_METADATA0_VID_MASK (0x0fff << 16)
375 #define RX_AGG_CMP_TYPE (0x3f << 0)
376 #define RX_AGG_CMP_LEN (0xffff << 16)
380 #define RX_AGG_CMP_V (1 << 0)
381 #define RX_AGG_CMP_AGG_ID (0xffff << 16)
392 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
393 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
395 #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6)
396 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
398 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
399 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
400 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
401 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
402 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
403 #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11)
404 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
406 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
407 #define RX_TPA_START_CMP_LEN (0xffff << 16)
412 #define RX_TPA_START_CMP_V1 (0x1 << 0)
413 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
415 #define RX_TPA_START_CMP_V3_RSS_HASH_TYPE (0x1ff << 7)
417 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
419 #define RX_TPA_START_CMP_AGG_ID_P5 (0xffff << 16)
421 #define RX_TPA_START_CMP_METADATA1 (0xf << 28)
423 #define RX_TPA_START_METADATA1_TPID_SEL (0x7 << 28)
424 #define RX_TPA_START_METADATA1_TPID_8021Q (0x1 << 28)
425 #define RX_TPA_START_METADATA1_TPID_8021AD (0x0 << 28)
426 #define RX_TPA_START_METADATA1_VALID (0x8 << 28)
467 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
468 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
469 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
470 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
471 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
472 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9)
473 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10)
475 #define RX_TPA_START_CMP_V3_FLAGS2_T_IP_TYPE (0x1 << 10)
476 #define RX_TPA_START_CMP_V3_FLAGS2_AGG_GRO (0x1 << 11)
477 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16)
482 #define RX_TPA_START_CMP_V2 (0x1 << 0)
483 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
485 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
486 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
487 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
488 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
490 #define RX_TPA_START_CMP_METADATA0_TCI_MASK (0xffff << 16)
491 #define RX_TPA_START_CMP_METADATA0_VID_MASK (0x0fff << 16)
516 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
517 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
519 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
521 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
522 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
523 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
524 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
525 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
526 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
528 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
529 #define RX_TPA_END_CMP_LEN (0xffff << 16)
534 #define RX_TPA_END_CMP_V1 (0x1 << 0)
535 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
537 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
539 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
541 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
543 #define RX_TPA_END_CMP_AGG_ID_P5 (0xffff << 16)
547 #define RX_TPA_END_GRO_TS (0x1 << 31)
584 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
585 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16)
587 #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24)
591 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
594 #define RX_TPA_END_CMP_V2 (0x1 << 0)
595 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
596 #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1)
598 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
599 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
600 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
601 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1)
602 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
654 #define NQ_CN_TYPE_MASK 0x3fUL
655 #define NQ_CN_TYPE_SFT 0
656 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
658 #define NQ_CN_TOGGLE_MASK 0xc0UL
663 #define NQ_CN_V 0x1UL
667 #define BNXT_NQ_HDL_IDX_MASK 0x00ffffff
668 #define BNXT_NQ_HDL_TYPE_MASK 0xff000000
670 #define BNXT_NQ_HDL_TYPE_RX 0x00
671 #define BNXT_NQ_HDL_TYPE_TX 0x01
684 #define DB_IDX_MASK 0xffffff
685 #define DB_IDX_VALID (0x1 << 26)
686 #define DB_IRQ_DIS (0x1 << 27)
687 #define DB_KEY_TX (0x0 << 28)
688 #define DB_KEY_RX (0x1 << 28)
689 #define DB_KEY_CP (0x2 << 28)
690 #define DB_KEY_ST (0x3 << 28)
691 #define DB_KEY_TX_PUSH (0x4 << 28)
692 #define DB_LONG_TX_PUSH (0x2 << 24)
698 #define DBR_INDEX_MASK 0x0000000000ffffffULL
699 #define DBR_EPOCH_MASK 0x01000000UL
701 #define DBR_TOGGLE_MASK 0x06000000UL
703 #define DBR_XID_MASK 0x000fffff00000000ULL
705 #define DBR_PATH_L2 (0x1ULL << 56)
706 #define DBR_VALID (0x1ULL << 58)
707 #define DBR_TYPE_SQ (0x0ULL << 60)
708 #define DBR_TYPE_RQ (0x1ULL << 60)
709 #define DBR_TYPE_SRQ (0x2ULL << 60)
710 #define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
711 #define DBR_TYPE_CQ (0x4ULL << 60)
712 #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
713 #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
714 #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
715 #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
716 #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
717 #define DBR_TYPE_NQ (0xaULL << 60)
718 #define DBR_TYPE_NQ_ARM (0xbULL << 60)
719 #define DBR_TYPE_NQ_MASK (0xeULL << 60)
720 #define DBR_TYPE_NULL (0xfULL << 60)
722 #define DB_PF_OFFSET_P5 0x10000
723 #define DB_VF_OFFSET_P5 0x4000
775 #define MAX_TPA_SEGS_P5 0x3f
867 #define BNXT_TX_CMP_EVENT 0x10
983 #define BNXT_DEV_STATE_CLOSING 0x1
1052 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
1055 (((hdr_info) >> 18) & 0x1ff)
1058 (((hdr_info) >> 9) & 0x1ff)
1061 ((hdr_info) & 0x1ff)
1196 for (iter = 0, txr = (bnapi)->tx_ring[0]; txr; \
1215 #define BNXT_NAPI_FLAG_XDP 0x1
1232 #define HWRM_RING_ALLOC_TX 0x1
1233 #define HWRM_RING_ALLOC_RX 0x2
1234 #define HWRM_RING_ALLOC_AGG 0x4
1235 #define HWRM_RING_ALLOC_CMPL 0x8
1236 #define HWRM_RING_ALLOC_NQ 0x10
1248 #define BNXT_VNIC_DEFAULT 0
1259 /* index 0 always dev_addr */
1290 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
1291 #define BNXT_VNIC_NTUPLE_FLAG 0x20
1292 #define BNXT_VNIC_RSSCTX_FLAG 0x40
1303 #define BNXT_VNIC_ID_INVALID 0xffffffff
1362 #define BNXT_VF_SPOOFCHK 0x2
1363 #define BNXT_VF_LINK_FORCED 0x4
1364 #define BNXT_VF_LINK_UP 0x8
1365 #define BNXT_VF_TRUST 0x10
1386 #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
1406 #define BNXT_ACT_RSS_CTX 0x10
1412 #define BNXT_FLTR_VALID 0
1528 #define BNXT_PHY_STATE_ENABLED 0
1532 #define BNXT_LINK_STATE_UNKNOWN 0
1708 (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1718 (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1756 ((bp->flags & BNXT_FLAG_CHIP_P5_PLUS) ? 0x80000000 : 0xb1000000)
1758 #define BNXT_GRCPF_REG_CHIMP_COMM 0x0
1759 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
1760 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
1762 #define BNXT_GRC_REG_STATUS_P5 0x520
1764 #define BNXT_GRCPF_REG_KONG_COMM 0xA00
1765 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
1767 #define BNXT_GRC_REG_CHIP_NUM 0x48
1768 #define BNXT_GRC_REG_BASE 0x260000
1770 #define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c
1771 #define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810
1773 #define BNXT_GRC_BASE_MASK 0xfffff000
1774 #define BNXT_GRC_OFFSET_MASK 0x00000ffc
1845 #define PTU_PTE_VALID 0x1UL
1846 #define PTU_PTE_LAST 0x2UL
1847 #define PTU_PTE_NEXT_TO_LAST 0x4UL
1870 if (BNXT_PAGE_SIZE == 0x2000) \
1872 else if (BNXT_PAGE_SIZE == 0x10000) \
1876 } while (0)
1887 #define BNXT_CTX_INIT_INVALID_OFFSET 0xffff
1911 #define BNXT_CTX_MRAV_AV_SPLIT_ENTRY 0
1943 #define BNXT_CTX_FLAG_INITED 0x01
1948 SEVERITY_NORMAL = 0,
1971 #define BNXT_FW_HEALTH_REG 0
2003 #define BNXT_FW_HEALTH_REG_TYPE_CFG 0
2011 #define BNXT_FW_HEALTH_WIN_BASE 0x3000
2017 #define BNXT_FW_STATUS_HEALTH_MSK 0xffff
2018 #define BNXT_FW_STATUS_HEALTHY 0x8000
2019 #define BNXT_FW_STATUS_SHUTDOWN 0x100000
2020 #define BNXT_FW_STATUS_RECOVERING 0x400000
2104 #define CHIP_NUM_57301 0x16c8
2105 #define CHIP_NUM_57302 0x16c9
2106 #define CHIP_NUM_57304 0x16ca
2107 #define CHIP_NUM_58700 0x16cd
2108 #define CHIP_NUM_57402 0x16d0
2109 #define CHIP_NUM_57404 0x16d1
2110 #define CHIP_NUM_57406 0x16d2
2111 #define CHIP_NUM_57407 0x16d5
2113 #define CHIP_NUM_57311 0x16ce
2114 #define CHIP_NUM_57312 0x16cf
2115 #define CHIP_NUM_57314 0x16df
2116 #define CHIP_NUM_57317 0x16e0
2117 #define CHIP_NUM_57412 0x16d6
2118 #define CHIP_NUM_57414 0x16d7
2119 #define CHIP_NUM_57416 0x16d8
2120 #define CHIP_NUM_57417 0x16d9
2121 #define CHIP_NUM_57412L 0x16da
2122 #define CHIP_NUM_57414L 0x16db
2124 #define CHIP_NUM_5745X 0xd730
2125 #define CHIP_NUM_57452 0xc452
2126 #define CHIP_NUM_57454 0xc454
2128 #define CHIP_NUM_57508 0x1750
2129 #define CHIP_NUM_57504 0x1751
2130 #define CHIP_NUM_57502 0x1752
2132 #define CHIP_NUM_57608 0x1760
2134 #define CHIP_NUM_58802 0xd802
2135 #define CHIP_NUM_58804 0xd804
2136 #define CHIP_NUM_58808 0xd808
2189 #define BNXT_FLAG_CHIP_P5_PLUS 0x1
2190 #define BNXT_FLAG_VF 0x2
2191 #define BNXT_FLAG_LRO 0x4
2193 #define BNXT_FLAG_GRO 0x8
2196 #define BNXT_FLAG_GRO 0x0
2199 #define BNXT_FLAG_JUMBO 0x10
2200 #define BNXT_FLAG_STRIP_VLAN 0x20
2203 #define BNXT_FLAG_RFS 0x100
2204 #define BNXT_FLAG_SHARED_RINGS 0x200
2205 #define BNXT_FLAG_PORT_STATS 0x400
2206 #define BNXT_FLAG_WOL_CAP 0x4000
2207 #define BNXT_FLAG_ROCEV1_CAP 0x8000
2208 #define BNXT_FLAG_ROCEV2_CAP 0x10000
2211 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
2212 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
2213 #define BNXT_FLAG_CHIP_P7 0x80000
2214 #define BNXT_FLAG_MULTI_HOST 0x100000
2215 #define BNXT_FLAG_DSN_VALID 0x200000
2216 #define BNXT_FLAG_DOUBLE_DB 0x400000
2217 #define BNXT_FLAG_UDP_GSO_CAP 0x800000
2218 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
2219 #define BNXT_FLAG_DIM 0x2000000
2220 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
2221 #define BNXT_FLAG_TX_COAL_CMPL 0x8000000
2222 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000
2337 #define BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA BIT(0)
2367 #define BNXT_STATE_OPEN 0
2404 #define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0)
2490 #define BNXT_FW_BLD(bp) (((bp)->fw_ver_code >> 16) & 0xffff)
2513 #define BNXT_RX_MASK_SP_EVENT 0
2623 #define BNXT_DUMP_LIVE 0
2705 #define I2C_DEV_ADDR_A0 0xa0
2706 #define I2C_DEV_ADDR_A2 0xa2
2707 #define SFF_DIAG_SUPPORT_OFFSET 0x5c
2708 #define SFF_MODULE_ID_SFP 0x3
2709 #define SFF_MODULE_ID_QSFP 0xc
2710 #define SFF_MODULE_ID_QSFP_PLUS 0xd
2711 #define SFF_MODULE_ID_QSFP28 0x11