Lines Matching +full:0 +full:x10600
145 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
146 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
147 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
148 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
149 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
150 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
151 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
152 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
153 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
154 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
155 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
156 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
157 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
158 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
159 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
160 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
161 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
162 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
163 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
164 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
165 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
166 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
167 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
168 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
169 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
170 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
171 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
172 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
173 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
174 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
175 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
176 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
177 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
178 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
179 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
180 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
181 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
182 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 },
183 { PCI_VDEVICE(BROADCOM, 0x1760), .driver_data = BCM57608 },
184 { PCI_VDEVICE(BROADCOM, 0x1761), .driver_data = BCM57604 },
185 { PCI_VDEVICE(BROADCOM, 0x1762), .driver_data = BCM57602 },
186 { PCI_VDEVICE(BROADCOM, 0x1763), .driver_data = BCM57601 },
187 { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57502_NPAR },
188 { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR },
189 { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57508_NPAR },
190 { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57502_NPAR },
191 { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR },
192 { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57508_NPAR },
193 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
194 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
196 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
197 { PCI_VDEVICE(BROADCOM, 0x1607), .driver_data = NETXTREME_E_VF_HV },
198 { PCI_VDEVICE(BROADCOM, 0x1608), .driver_data = NETXTREME_E_VF_HV },
199 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
200 { PCI_VDEVICE(BROADCOM, 0x16bd), .driver_data = NETXTREME_E_VF_HV },
201 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
202 { PCI_VDEVICE(BROADCOM, 0x16c2), .driver_data = NETXTREME_C_VF_HV },
203 { PCI_VDEVICE(BROADCOM, 0x16c3), .driver_data = NETXTREME_C_VF_HV },
204 { PCI_VDEVICE(BROADCOM, 0x16c4), .driver_data = NETXTREME_E_VF_HV },
205 { PCI_VDEVICE(BROADCOM, 0x16c5), .driver_data = NETXTREME_E_VF_HV },
206 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
207 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
208 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
209 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
210 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
211 { PCI_VDEVICE(BROADCOM, 0x16e6), .driver_data = NETXTREME_C_VF_HV },
212 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF },
213 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
214 { PCI_VDEVICE(BROADCOM, 0x1808), .driver_data = NETXTREME_E_P5_VF_HV },
215 { PCI_VDEVICE(BROADCOM, 0x1809), .driver_data = NETXTREME_E_P5_VF_HV },
216 { PCI_VDEVICE(BROADCOM, 0x1819), .driver_data = NETXTREME_E_P7_VF },
217 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
219 { 0 }
252 #define BNXT_IPV6_MASK_ALL {{{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
253 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }}}
254 #define BNXT_IPV6_MASK_NONE {{{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}}
258 .src = 0,
259 .dst = 0,
271 .src = cpu_to_be16(0xffff),
272 .dst = cpu_to_be16(0xffff),
284 .src = cpu_to_be16(0xffff),
285 .dst = cpu_to_be16(0xffff),
289 .src = cpu_to_be32(0xffffffff),
290 .dst = cpu_to_be32(0xffffffff),
386 rxr->rx_next_cons = 0xffff;
432 return 0;
443 txr->kick_pending = 0;
454 unsigned int length, pad = 0;
461 __le32 lflags = 0;
498 vlan_tag_flags = 0;
559 tx_push1->tx_bd_hsize_lflags = 0;
567 *end = 0;
571 for (j = 0; j < last_frag; j++) {
664 txbd1->tx_bd_mss = 0;
671 i = 0;
681 for (i = 0; i < last_frag; i++) {
688 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
749 for (i = 0; i < last_frag; i++) {
761 txr->tx_buf_ring[txr->tx_prod].is_ts_pkt = 0;
781 unsigned int tx_bytes = 0;
783 int tx_pkts = 0;
810 tx_buf->is_ts_pkt = 0;
813 tx_buf->is_push = 0;
821 for (j = 0; j < last; j++) {
879 *offset = 0;
942 return 0;
986 unsigned int offset = 0;
1005 return 0;
1043 for (i = 0; i < agg_bufs; i++) {
1092 unsigned int len = offset_and_len & 0xffff;
1125 unsigned int len = offset_and_len & 0xffff;
1152 skb_add_rx_frag(skb, 0, page, off, len, BNXT_RX_PAGE_SIZE);
1156 frag = &skb_shinfo(skb)->frags[0];
1190 skb_put(skb, offset_and_len & 0xffff);
1204 u32 i, total_frag_len = 0;
1210 for (i = 0; i < agg_bufs; i++) {
1243 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
1252 return 0;
1271 u32 total_frag_len = 0;
1293 u32 total_frag_len = 0;
1296 shinfo->nr_frags = 0;
1359 unsigned int metasize = 0;
1384 u8 cmp_type, agg_bufs = 0;
1396 return 0;
1406 return 0;
1442 tpa_info->vlan_valid = 0;
1454 tpa_info->vlan_valid = 0;
1520 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1528 tpa_info->gso_type = 0;
1537 tpa_info->agg_count = 0;
1552 bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true);
1626 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1633 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1684 int len, nw_off, tcp_opt_len = 0;
1699 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1710 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1777 u16 idx = 0, agg_id;
1784 if (rc < 0)
1799 tpa_info->agg_count = 0;
2013 * 0 - successful TPA_START, packet not completed yet
2038 int rc = 0;
2094 /* 0xffff is forced error, don't print it */
2095 if (rxr->rx_next_cons != 0xffff)
2126 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs,
2174 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0,
2187 payload = 0;
2217 /* RSS profiles 1 and 3 with extract code 0 for inner
2262 memset(skb_hwtstamps(skb), 0,
2342 u32 reg_type, reg_off, val = 0;
2369 for (i = 0; i < bp->rx_nr_rings; i++) {
2583 netdev_dbg(bp->dev, "hwrm event 0x%x {0x%x, 0x%x}\n",
2596 (data1 & 0x20000)) {
2660 "%s firmware reset event, data1: 0x%x, data2: 0x%x, min wait %u ms, max wait %u ms\n",
2694 "Driver recovery watchdog, role: %s, firmware status: 0x%x (%s), resets: %u\n",
2708 "Received firmware debug notification, data1: 0x%x, data2: 0x%x\n",
2718 netdev_warn(bp->dev, "Ring monitor event, ring type %lu id 0x%x\n",
2725 netdev_warn(bp->dev, "Unknown RX agg ring id 0x%x\n",
2737 "Received firmware echo request, data1: 0x%x, data2: 0x%x\n",
2779 u16 seq_id = le32_to_cpu(cmpl->event_data2) & 0xffff;
2789 return 0;
2828 return 0;
2861 int rx_pkts = 0;
2862 u8 event = 0;
2865 cpr->has_more_work = 0;
2913 if (likely(rc >= 0))
2943 struct bnxt_tx_ring_info *txr = bnapi->tx_ring[0];
3007 u32 rx_pkts = 0;
3008 u8 event = 0;
3023 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
3077 int work_done = 0;
3081 return 0;
3113 int i, work_done = 0;
3115 for (i = 0; i < cpr->cp_ring_count; i++) {
3133 for (i = 0; i < cpr->cp_ring_count; i++) {
3138 u32 tgl = 0;
3141 cpr2->had_nqe_notify = 0;
3149 cpr2->had_work_done = 0;
3163 int work_done = 0;
3168 return 0;
3171 cpr->has_more_work = 0;
3227 cpr_rx = &cpr->cp_ring_arr[0];
3250 for (i = 0; i < bp->tx_nr_rings; i++) {
3257 for (j = 0; j < max_idx;) {
3269 tx_buf->action = 0;
3296 for (k = 0; k < last; k++, j++) {
3319 for (i = 0; i < max_idx; i++) {
3345 for (i = 0; i < max_idx; i++) {
3369 for (i = 0; i < bp->max_tpa; i++) {
3400 memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap));
3410 for (i = 0; i < bp->rx_nr_rings; i++)
3433 for (i = 0; i < len; i += ctxm->entry_size)
3445 for (i = 0; i < rmem->nr_pages; i++) {
3473 u64 valid_bit = 0;
3478 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
3490 for (i = 0; i < rmem->nr_pages; i++) {
3503 if (rmem->nr_pages > 1 || rmem->depth > 0) {
3520 return 0;
3527 for (i = 0; i < bp->rx_nr_rings; i++) {
3533 for (j = 0; j < bp->max_tpa; j++) {
3550 return 0;
3554 for (i = 0; i < bp->rx_nr_rings; i++) {
3565 for (j = 0; j < bp->max_tpa; j++) {
3576 return 0;
3587 for (i = 0; i < bp->rx_nr_rings; i++) {
3615 struct page_pool_params pp = { 0 };
3635 return 0;
3641 int i, rc = 0, agg_rings = 0, cpu;
3649 for (i = 0; i < bp->rx_nr_rings; i++) {
3664 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i, 0);
3665 if (rc < 0)
3710 for (i = 0; i < bp->tx_nr_rings; i++) {
3740 bp->tx_push_size = 0;
3748 push_size = 0;
3749 bp->tx_push_thresh = 0;
3755 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
3793 return 0;
3817 return 0;
3826 for (i = 0; i < bp->cp_nr_rings; i++) {
3839 for (i = 0; i < bp->cp_nr_rings; i++) {
3849 return 0;
3859 for (i = 0; i < bp->cp_nr_rings; i++) {
3876 for (j = 0; j < cpr->cp_ring_count; j++) {
3885 cpr->cp_ring_count = 0;
3925 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
3929 int cp_count = 0, k;
3930 int rx = 0, tx = 0;
3967 for (k = 0; k < cp_count; k++) {
3989 return 0;
4026 memset(&rxr->xdp_rxq, 0, sizeof(struct xdp_rxq_info));
4031 rmem->pg_tbl_map = 0;
4032 for (i = 0; i < rmem->nr_pages; i++) {
4034 rmem->dma_arr[i] = 0;
4041 rmem->pg_tbl_map = 0;
4042 for (i = 0; i < rmem->nr_pages; i++) {
4044 rmem->dma_arr[i] = 0;
4053 for (i = 0; i < bp->cp_nr_rings; i++) {
4071 rmem->vmem_size = 0;
4116 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
4124 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
4139 for (i = 0; i < bp->rx_ring_size; i++) {
4158 for (i = 0; i < bp->rx_agg_ring_size; i++) {
4177 return 0;
4185 for (i = 0; i < bp->max_tpa; i++) {
4195 return 0;
4255 for (i = 0; i < bp->cp_nr_rings; i++) {
4264 for (j = 0; j < cpr->cp_ring_count; j++) {
4277 int i, rc = 0;
4287 for (i = 0; i < bp->rx_nr_rings; i++) {
4303 for (i = 0; i < bp->tx_nr_rings; i++) {
4315 return 0;
4335 for (i = 0; i < bp->cp_nr_rings; i++) {
4343 return 0;
4350 bp->nr_vnics = 0;
4375 return 0;
4383 for (i = 0; i < bp->nr_vnics; i++) {
4389 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
4415 bp->toeplitz_prefix = 0;
4416 for (k = 0; k < 8; k++) {
4462 u32 agg_factor = 0, agg_ring_size = 0;
4472 bp->rx_agg_ring_size = 0;
4473 bp->rx_agg_nr_pages = 0;
4585 return 0;
4597 for (i = 0; i < bp->nr_vnics; i++) {
4620 vnic->flags = 0;
4626 int i, rc = 0, size;
4631 for (i = 0; i < bp->nr_vnics; i++) {
4637 if (mem_size > 0) {
4695 return 0;
4718 BNXT_HWRM_DMA_ALIGN, 0);
4724 return 0;
4757 return 0;
4768 for (i = 0; i < count; i++)
4776 for (i = 0; i < count; i++)
4796 req->fid = cpu_to_le16(0xffff);
4814 struct bnxt_napi *bnapi = bp->bnapi[0];
4852 bnxt_hwrm_port_qstats(bp, 0);
4878 bnxt_hwrm_port_qstats_ext(bp, 0);
4900 for (i = 0; i < bp->cp_nr_rings; i++) {
4918 for (i = 0; i < bp->cp_nr_rings; i++) {
4935 return 0;
4949 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900)
4951 return 0;
4960 return 0;
4964 return 0;
4966 if (bp->hwrm_spec_code >= 0x10902 ||
4972 return 0;
4975 return 0;
4985 for (i = 0; i < bp->cp_nr_rings; i++) {
4995 cpr->cp_raw_cons = 0;
4998 txr->tx_prod = 0;
4999 txr->tx_cons = 0;
5000 txr->tx_hw_cons = 0;
5005 rxr->rx_prod = 0;
5006 rxr->rx_agg_prod = 0;
5007 rxr->rx_sw_agg_prod = 0;
5008 rxr->rx_next_cons = 0;
5010 bnapi->events = 0;
5059 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
5078 bp->ntp_fltr_count = 0;
5083 int i, rc = 0;
5086 return 0;
5088 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
5091 bp->ntp_fltr_count = 0;
5104 for (i = 0; i < BNXT_L2_FLTR_HASH_SIZE; i++) {
5123 for (i = 0; i < BNXT_L2_FLTR_HASH_SIZE; i++)
5175 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
5194 for (i = 0; i < bp->rx_nr_rings; i++) {
5222 j = 0;
5226 for (i = 0; i < bp->tx_nr_rings; i++) {
5246 bnapi2->tx_ring[0] = txr;
5297 return 0;
5311 for (i = 0; i < bp->cp_nr_rings; i++) {
5340 for (i = 0; i < bp->cp_nr_rings; i++) {
5351 atomic_set(&bp->intr_sem, 0);
5352 for (i = 0; i < bp->cp_nr_rings; i++) {
5397 memset(data, 0, sizeof(data));
5398 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
5407 for (i = 0; i < 8; i++)
5418 memset(async_events_bmap, 0, sizeof(async_events_bmap));
5419 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) {
5431 for (i = 0; i < bmap_size; i++) {
5436 for (i = 0; i < 8; i++)
5461 return 0;
5478 return 0;
5481 return 0;
5492 bp->vxlan_port = 0;
5497 bp->nge_port = 0;
5502 bp->vxlan_gpe_port = 0;
5667 return 0;
5673 u64 prefix = bp->toeplitz_prefix, hash = 0;
5676 int i, j, len = 0;
5681 return 0;
5693 for (i = 0, j = 8; i < len; i++, j++) {
5697 for (bit = 0; bit < 8; bit++, prefix <<= 1, byte <<= 1) {
5698 if (byte & 0x80)
5701 prefix |= (j < HW_HASH_KEY_SIZE) ? key[j] : 0;
5734 bp->max_fltr, 0);
5735 if (bit_id < 0)
5745 return 0;
5823 u16 target_id = 0xffff;
5850 u16 target_id = 0xffff;
5886 req->l2_ivlan_mask = cpu_to_le16(0xfff);
5936 for (i = 0; i < 4; i++)
5937 mask[i] = cpu_to_be32(~0);
6017 *(struct in6_addr *)&req->src_ipaddr[0] = keys->addrs.v6addrs.src;
6018 *(struct in6_addr *)&req->src_ipaddr_mask[0] = masks->addrs.v6addrs.src;
6019 *(struct in6_addr *)&req->dst_ipaddr[0] = keys->addrs.v6addrs.dst;
6020 *(struct in6_addr *)&req->dst_ipaddr_mask[0] = masks->addrs.v6addrs.dst;
6022 req->src_ipaddr[0] = keys->addrs.v4addrs.src;
6023 req->src_ipaddr_mask[0] = masks->addrs.v4addrs.src;
6024 req->dst_ipaddr[0] = keys->addrs.v4addrs.dst;
6025 req->dst_ipaddr_mask[0] = masks->addrs.v4addrs.dst;
6054 key.vlan = 0;
6070 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
6073 for (i = 0; i < num_of_vnics; i++) {
6076 for (j = 0; j < vnic->uc_filter_count; j++) {
6082 vnic->uc_filter_count = 0;
6118 return 0;
6126 u32 nsegs, n, segs = 0, flags;
6212 return 0;
6233 rss_indir_tbl = &bp->rss_indir_tbl[0];
6235 for (i = 0; i < max_entries; i++)
6240 memset(&rss_indir_tbl[i], 0, pad * sizeof(*rss_indir_tbl));
6245 u32 i, tbl_size, max_ring = 0;
6248 return 0;
6251 for (i = 0; i < tbl_size; i++)
6260 return 0;
6275 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++) {
6291 for (i = 0; i < tbl_size; i++) {
6342 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
6343 return 0;
6351 req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
6376 for (i = 0; i < nr_ctxs; ring_tbl_map += BNXT_RSS_TABLE_SIZE_P5, i++) {
6401 req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
6405 bp->rss_hash_delta = 0;
6456 for (i = 0; i < bp->nr_vnics; i++) {
6459 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
6464 bp->rsscos_nr_ctxs = 0;
6499 unsigned int ring = 0, grp_idx;
6500 u16 def_vlan = 0;
6508 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
6521 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
6522 req->rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
6526 req->rss_rule = cpu_to_le16(vnic0->fw_rss_cos_lb_ctx[0]);
6531 req->rss_rule = cpu_to_le16(0xffff);
6535 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
6539 req->cos_rule = cpu_to_le16(0xffff);
6543 ring = 0;
6551 req->lb_rule = cpu_to_le16(0xffff);
6589 for (i = 0; i < bp->nr_vnics; i++)
6610 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
6621 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
6643 if (bp->hwrm_spec_code < 0x10600)
6644 return 0;
6705 return 0;
6712 for (i = 0; i < bp->rx_nr_rings; i++) {
6744 for (i = 0; i < bp->cp_nr_rings; i++) {
6764 int rc, err = 0;
6771 req->enables = 0;
6778 req->page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]);
6780 req->fbo = 0;
6787 u16 flags = 0;
6810 u16 flags = 0;
6891 req->fid = cpu_to_le16(0xffff);
6959 db->doorbell = bp->bar1 + map_idx * 0x80;
6992 return 0;
7015 return 0;
7021 int i, rc = 0;
7028 for (i = 0; i < bp->cp_nr_rings; i++) {
7055 for (i = 0; i < bp->tx_nr_rings; i++) {
7083 for (i = 0; i < bp->rx_nr_rings; i++) {
7111 for (i = 0; i < bp->rx_nr_rings; i++) {
7127 u16 error_code = 0;
7131 return 0;
7151 return 0;
7206 for (i = 0; i < bp->tx_nr_rings; i++) {
7221 for (i = 0; i < bp->rx_nr_rings; i++) {
7236 for (i = 0; i < bp->cp_nr_rings; i++) {
7242 for (j = 0; j < cpr->cp_ring_count && cpr->cp_ring_arr; j++) {
7275 if (bp->hwrm_spec_code < 0x10601)
7276 return 0;
7282 req->fid = cpu_to_le16(0xffff);
7334 if (bp->hwrm_spec_code < 0x10601)
7335 return 0;
7357 u32 enables = 0;
7362 req->fid = cpu_to_le16(0xffff);
7363 enables |= hwr->tx ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
7366 enables |= hwr->rx ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
7367 enables |= hwr->stat ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
7369 enables |= hwr->cp ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
7371 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
7374 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
7376 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
7378 enables |= hwr->vnic ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
7380 0;
7401 u32 enables = 0;
7406 enables |= hwr->tx ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
7408 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
7409 enables |= hwr->stat ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
7410 enables |= hwr->rss_ctx ? FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
7413 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
7415 enables |= hwr->cp ? FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
7417 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
7419 enables |= hwr->vnic ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
7451 return 0;
7458 if (bp->hwrm_spec_code < 0x10601)
7472 return 0;
7518 return 0;
7576 bp->hwrm_spec_code >= 0x10601)
7625 struct bnxt_hw_rings hwr = {0};
7628 int ulp_msix = 0;
7633 return 0;
7638 bnxt_set_ulp_stat_ctxs(bp, 0);
7742 return 0;
7783 if (bp->hwrm_spec_code < 0x10801)
7784 return 0;
7809 if (bp->hwrm_spec_code < 0x10902)
7913 return 0;
7985 return 0;
7987 return 0;
8010 for (i = 0; i < bp->cp_nr_rings; i++) {
8024 if (bnapi->rx_ring && bnapi->tx_ring[0]) {
8062 for (i = 0; i < bp->cp_nr_rings; i++) {
8089 return 0;
8099 for (i = 0; i < bp->cp_nr_rings; i++) {
8128 req->fid = cpu_to_le16(0xffff);
8163 if (bp->hwrm_spec_code < 0x10707 ||
8205 ctxm->init_value = 0;
8213 for (type = 0; type < ctx_max; type++) {
8226 return 0;
8252 for (type = 0; type < BNXT_CTX_V2_MAX; ) {
8280 for (i = 0, p = &resp->split_entry_0; i < ctxm->split_entry_cnt;
8297 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
8298 return 0;
8312 u8 init_val, init_idx = 0;
8334 (init_mask & (1 << init_idx++)) != 0);
8341 (init_mask & (1 << init_idx++)) != 0);
8348 (init_mask & (1 << init_idx++)) != 0);
8357 (init_mask & (1 << init_idx++)) != 0);
8364 (init_mask & (1 << init_idx++)) != 0);
8383 (init_mask & (1 << init_idx++)) != 0);
8401 rc = 0;
8422 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
8443 u32 flags = 0;
8450 return 0;
8544 for (i = 0, num_entries = &req->tqm_sp_num_entries,
8589 ctx_pg->nr_pages = 0;
8605 for (i = 0; i < nr_tbls; i++) {
8647 for (i = 0; i < nr_tbls; i++) {
8664 ctx_pg->nr_pages = 0;
8672 int i, rc = 0, n = 1;
8683 for (i = 0; i < n && !rc; i++) {
8697 int i, j, rc = 0, n = 1;
8701 return 0;
8715 for (i = 0, p = &req->split_entry_0; i < ctxm->split_entry_cnt; i++)
8717 for (i = 0, j = 0; j < n && !rc; i++) {
8744 int rc = 0;
8748 return 0;
8755 for (type = 0 ; type < BNXT_CTX_V2_MAX; type++) {
8762 return 0;
8773 for (type = 0; type < BNXT_CTX_V2_MAX; type++) {
8782 for (i = 0; i < n; i++)
8802 u32 extra_srqs = 0;
8803 u32 extra_qps = 0;
8816 return 0;
8826 ena = 0;
8902 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++)
8916 return 0;
8926 return 0;
8932 if (BNXT_PAGE_SIZE == 0x2000)
8934 else if (BNXT_PAGE_SIZE == 0x10000)
8957 u32 mem_size = 0;
8961 return 0;
8990 return 0;
9004 req->fid = cpu_to_le16(0xffff);
9060 if (bp->hwrm_spec_code < 0x10801 || !BNXT_CHIP_P5_PLUS(bp)) {
9094 ptp->refclk_regs[0] = le32_to_cpu(resp->ts_ref_clock_reg_lower);
9097 ptp->refclk_regs[0] = BNXT_TS_REG_TIMESYNC_TS0_LOWER;
9103 phc_cfg = (flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED) != 0;
9110 return 0;
9131 req->fid = cpu_to_le16(0xffff);
9183 bp->tx_push_thresh = 0;
9245 bp->fw_dbg_cap = 0;
9253 req->fid = cpu_to_le16(0xffff);
9282 if (bp->hwrm_spec_code >= 0x10803) {
9290 return 0;
9301 return 0;
9333 return 0;
9340 return 0;
9349 return 0;
9358 return 0;
9435 u32 reg_base = 0xffffffff;
9441 for (i = 0; i < 4; i++) {
9446 if (reg_base == 0xffffffff)
9454 if (reg_base == 0xffffffff)
9455 return 0;
9458 return 0;
9482 return 0;
9522 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) {
9548 req->enables = 0;
9569 int rc = 0;
9591 for (i = 0, j = 0; i < bp->max_tc; i++) {
9661 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
9664 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
9680 if (bp->hwrm_spec_code > 0x10803 && fw_maj) {
9760 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
9761 bp->hwrm_spec_code < 0x10400)
9764 time64_to_tm(now, 0, &tm);
9794 for (i = 0; i < count; i++) {
9822 /* Chip bug. Counter intermittently becomes 0. */
9826 for (i = 0; i < bp->cp_nr_rings; i++) {
9868 return 0;
9896 return 0;
9910 sizeof(struct tx_port_stats_ext) : 0;
9923 le16_to_cpu(resp_qs->tx_stat_size) / 8 : 0;
9925 bp->fw_rx_stats_ext_size = 0;
9926 bp->fw_tx_stats_ext_size = 0;
9935 bp->pri2cos_valid = 0;
9952 for (i = 0; i < 8; i++) {
9956 /* Per port queue IDs start from 0, 10, 20, etc */
9963 for (j = 0; j < bp->max_q; j++) {
9986 u32 tpa_flags = 0;
9991 return 0;
9992 for (i = 0; i < bp->nr_vnics; i++) {
10000 return 0;
10007 for (i = 0; i < bp->nr_vnics; i++)
10059 req->fid = cpu_to_le16(0xffff);
10070 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
10071 return 0;
10077 req->fid = cpu_to_le16(0xffff);
10094 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, 0);
10183 for (i = 0; i < nr_ctxs; i++) {
10235 int i, rc = 0;
10239 return bnxt_alloc_and_setup_vnic(bp, vnic, 0, bp->rx_nr_rings);
10243 return 0;
10245 for (i = 0; i < bp->rx_nr_rings; i++) {
10272 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++) {
10309 if (bnxt_hwrm_vnic_alloc(bp, vnic, 0, bp->rx_nr_rings) ||
10345 unsigned int rc = 0;
10369 int rc = 0;
10396 /* default vnic 0 */
10397 rc = bnxt_hwrm_vnic_alloc(bp, vnic, 0, rx_nr_rings);
10427 /* Filter for default vnic 0 */
10428 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
10438 vnic->rx_mask = 0;
10450 vnic->mc_list_count = 0;
10452 u32 mask = 0;
10480 return 0;
10483 bnxt_hwrm_resource_free(bp, 0, true);
10491 return 0;
10548 return 0;
10586 return 0;
10593 const int len = sizeof(bp->irq_tbl[0].name);
10601 for (i = 0; i < tcs; i++) {
10608 for (i = 0; i < bp->cp_nr_rings; i++) {
10635 if (map.index < 0)
10735 if (num <= 0)
10736 return 0;
10751 int i, total_vecs, max, rc = 0, min = 1, ulp_msix, tx_cp, tbl_size;
10759 return 0;
10767 if (total_vecs < 0 || total_vecs < ulp_msix) {
10777 for (i = 0; i < total_vecs; i++)
10796 return 0;
10823 return 0;
10860 bp->num_tc = 0;
10867 return 0;
10882 for (i = 0; i < bp->cp_nr_rings; i++) {
10890 irq->have_cpumask = 0;
10895 irq->requested = 0;
10901 int i, j, rc = 0;
10902 unsigned long flags = 0;
10916 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
10962 for (i = 0; i < bp->rx_nr_rings; i++)
10964 for (i = 0; i < bp->tx_nr_rings - bp->tx_nr_rings_xdp; i++)
10967 for (i = 0; i < bp->cp_nr_rings; i++) {
10989 for (i = 0; i < cp_nr_rings; i++) {
11007 for (i = 0; i < bp->cp_nr_rings; i++) {
11027 for (i = 0; i < bp->cp_nr_rings; i++) {
11031 bnapi->tx_fault = 0;
11050 for (i = 0; i < bp->tx_nr_rings; i++) {
11068 for (i = 0; i < bp->tx_nr_rings; i++) {
11070 WRITE_ONCE(txr->dev_state, 0);
11182 int rc = 0;
11184 if (bp->hwrm_spec_code < 0x10201)
11185 return 0;
11208 if (bp->hwrm_spec_code >= 0x10a01) {
11216 link_info->support_auto_speeds = 0;
11217 link_info->support_pam4_auto_speeds = 0;
11218 link_info->support_auto_speeds2 = 0;
11292 rc = 0;
11300 if (bp->hwrm_spec_code >= 0x10800)
11313 link_info->link_speed = 0;
11314 link_info->active_lanes = 0;
11332 link_info->phy_ver[0] = resp->phy_maj;
11346 eee->eee_active = 0;
11377 if (bp->hwrm_spec_code >= 0x10504) {
11396 return 0;
11401 return 0;
11420 if (bp->hwrm_spec_code >= 0x10201) {
11435 if (bp->hwrm_spec_code >= 0x10201)
11451 if (bp->hwrm_spec_code >= 0x10201) {
11521 bp->link_info.auto_pause_setting = 0;
11577 return 0;
11581 return 0;
11620 int retry = 0, rc;
11634 "Firmware not responding, status: 0x%x\n",
11655 hw_resc->resv_cp_rings = 0;
11656 hw_resc->resv_stat_ctxs = 0;
11657 hw_resc->resv_irqs = 0;
11658 hw_resc->resv_tx_rings = 0;
11659 hw_resc->resv_rx_rings = 0;
11660 hw_resc->resv_hw_ring_grps = 0;
11661 hw_resc->resv_vnics = 0;
11662 hw_resc->resv_rsscos_ctxs = 0;
11664 bp->tx_nr_rings = 0;
11665 bp->rx_nr_rings = 0;
11674 return 0; /* no resource reservations required */
11691 int rc, retry = 0;
11692 u32 flags = 0;
11695 return 0;
11730 return 0;
11779 bp->num_leds = 0;
11780 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
11781 return 0;
11794 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
11798 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
11800 for (i = 0; i < bp->num_leds; i++) {
11806 bp->num_leds = 0;
11812 return 0;
11858 u16 next_handle = 0;
11871 if (next_handle != 0) {
11885 u16 handle = 0;
11887 bp->wol = 0;
11893 } while (handle && handle != 0xffff);
11911 eee->eee_enabled = 0;
11938 return 0;
12017 l2_fltr = bp->vnic_info[BNXT_VNIC_DEFAULT].l2_filters[0];
12050 int rc = 0;
12060 for (i = 0; i < nr_cpus; i++) {
12068 for (q_idx = 0; q_idx < bp->dev->real_num_tx_queues; q_idx++) {
12085 int rc = 0;
12171 return 0;
12186 int rc = 0;
12205 int rc = 0;
12227 return 0;
12364 else if (rc < 0)
12378 return 0;
12388 if (bp->hwrm_spec_code < 0x10a00)
12397 req->reg_addr = cpu_to_le16(reg & 0x1f);
12419 if (bp->hwrm_spec_code < 0x10a00)
12428 req->reg_addr = cpu_to_le16(reg & 0x1f);
12453 u16 mii_regval = 0;
12489 for (i = 0; i < bp->cp_nr_rings; i++) {
12607 for (i = 0; i < bp->cp_nr_rings; i++)
12617 int mc_count = 0;
12619 int off = 0;
12624 vnic->mc_list_count = 0;
12650 int off = 0;
12691 vnic->mc_list_count = 0;
12708 int i, off = 0, rc;
12739 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
12740 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
12747 rc = 0;
12762 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
12768 vnic->mc_list_count = 0;
12769 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
12818 struct bnxt_hw_rings hwr = {0};
12862 hwr.rss_ctx = 0;
12918 int rc = 0;
12941 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
12942 (flags & BNXT_FLAG_TPA) == 0 ||
12986 int hdr_count = 0;
13023 if (jhdr->tlv_type != IPV6_TLV_JUMBO || jhdr->hdrlen != 0 ||
13159 for (i = 0; i < num_words; i++)
13229 for (i = 0; i < bp->cp_nr_rings; i++) {
13323 if (atomic_read(&bp->intr_sem) != 0)
13398 for (i = 0; i < bp->rx_nr_rings; i++) {
13417 rxr->rx_prod = 0;
13418 rxr->rx_agg_prod = 0;
13419 rxr->rx_sw_agg_prod = 0;
13420 rxr->rx_next_cons = 0;
13451 u16 val = 0;
13454 if (val == 0xffff)
13455 bp->fw_reset_min_dsecs = 0;
13511 wait_dsecs = 0;
13535 * < 0 on error.
13543 return 0;
13555 return 0;
13565 int n = 0, tmo;
13579 if (n < 0) {
13585 } else if (n > 0) {
13616 for (i = 0; i < bp->cp_nr_rings; i++) {
13626 for (j = 0; j < cpr->cp_ring_count; j++) {
13640 fw_ring_id, &val[0], &val[1]);
13654 if (bp->hwrm_spec_code >= 0x10201) {
13690 bnxt_ulp_start(bp, 0);
13719 bnxt_hwrm_port_qstats(bp, 0);
13720 bnxt_hwrm_port_qstats_ext(bp, 0);
13810 struct bnxt_hw_rings hwr = {0};
13894 u16 flags = 0;
13942 bp->fw_cap = 0;
13966 return 0;
13995 rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false);
14023 return 0;
14035 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
14099 return 0;
14119 reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000;
14129 pci_read_config_dword(bp->pdev, 0, &val);
14146 req->fid = cpu_to_le16(0xffff);
14167 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++)
14197 bp->fw_reset_state = 0;
14204 int rc = 0;
14216 if (n < 0) {
14221 } else if (n > 0) {
14224 bp->fw_reset_state = 0;
14283 if (val == 0xffff) {
14338 bp->fw_reset_state = 0;
14339 /* Make sure fw_reset_state is 0 before clearing the flag */
14349 bnxt_ulp_start(bp, 0);
14364 netdev_err(bp->dev, "fw_health_status 0x%x\n", sts);
14388 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
14401 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
14402 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
14416 bp->bar0 = pci_ioremap_bar(pdev, 0);
14441 timer_setup(&bp->timer, bnxt_timer, 0);
14448 return 0;
14466 int rc = 0;
14472 return 0;
14502 return 0;
14518 return 0;
14539 bp->num_tc = 0;
14549 return 0;
14613 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, bp->max_fltr, 0);
14614 if (bit_id < 0) {
14628 return 0;
14693 int rc = 0, idx;
14697 l2_fltr = bp->vnic_info[BNXT_VNIC_DEFAULT].l2_filters[0];
14703 key.vlan = 0;
14719 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
14733 if (bp->hwrm_spec_code < 0x10601) {
14741 bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) {
14793 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
14888 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
14897 int rem, rc = 0;
14899 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
14936 return 0;
14982 stats->packets = 0;
14987 stats->bytes = 0;
15005 stats->packets = 0;
15010 stats->bytes = 0;
15046 return 0;
15062 clone->rx_prod = 0;
15063 clone->rx_agg_prod = 0;
15064 clone->rx_sw_agg_prod = 0;
15065 clone->rx_next_cons = 0;
15071 rc = xdp_rxq_info_reg(&clone->xdp_rxq, bp->dev, idx, 0);
15072 if (rc < 0)
15104 return 0;
15166 for (i = 0; i < dst_rmem->nr_pages; i++) {
15190 for (i = 0; i < dst_rmem->nr_pages; i++) {
15232 for (i = 0; i <= BNXT_VNIC_NTUPLE; i++) {
15239 return 0;
15253 for (i = 0; i <= BNXT_VNIC_NTUPLE; i++) {
15255 vnic->mru = 0;
15263 rxr->rx_next_cons = 0;
15269 return 0;
15302 bp->sp_event = 0;
15329 int rc = 0;
15332 bp->phy_flags = 0;
15344 return 0;
15363 return 0;
15381 int max_ring_grps = 0, max_irq;
15404 *max_rx = 0;
15405 *max_tx = 0;
15457 return 0;
15466 rc = 0;
15488 return 0;
15540 bp->tx_nr_rings = 0;
15541 bp->rx_nr_rings = 0;
15551 return 0;
15603 int rc = 0;
15643 if (pos < 0)
15653 if (pos < 0)
15676 return 0;
15686 return 0;
15693 (long)pci_resource_start(bp->pdev, 0), bp->dev->dev_addr);
15740 if (rc < 0)
15942 return 0;
16004 int rc = 0;
16024 int rc = 0;
16050 if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) {
16148 int retry = 0;
16149 int err = 0;
16171 * write the BARs to 0 to force restore, in case of fatal error.
16177 pci_write_config_dword(bp->pdev, off, 0);
16277 return 0;