Lines Matching full:line

115 /* lines start from 2 since line 1 is heading in csv */
118 /*line 2*/{(0x3), 1, 0x2114,
124 /*line 3*/{(0x3), 1, 0x2114,
130 /*line 4*/{(0x3), 1, 0x2120,
136 /*line 5*/{(0x3), 1, 0x2814,
142 /*line 6*/{(0x2), 1, 0x281c,
148 /*line 7*/{(0x2), 1, 0x2820,
154 /*line 8*/{(0x3), 1, PXP2_REG_PGL_EXP_ROM2,
160 /*line 9*/{(0x3), 2, 0x212c,
166 /*line 10*/{(0x1C), 1, 0x2104,
172 /*line 11*/{(0x1C), 1, 0x2104,
178 /*line 12*/{(0x1C), 1, 0x2104,
184 /*line 13*/{(0x1C), 1, 0x2110,
190 /*line 14*/{(0x1C), 1, 0x2814,
196 /*line 15*/{(0x1C), 1, 0x2814,
202 /*line 16*/{(0x1C), 1, 0x2854,
208 /*line 17*/{(0x1C), 1, 0x285c,
214 /*line 18*/{(0x18), 1, 0x3040,
220 /*line 19*/{(0x1C), 1, PXP2_REG_PGL_EXP_ROM2,
226 /*line 20*/{(0x1C), 2, 0x211c,
232 /*line 21*/{(0x1C), 1, PGLUE_B_REG_INCORRECT_RCV_DETAILS,
238 /*line 22*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_31_0,
244 /*line 23*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_63_32,
250 /*line 24*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_95_64,
256 /*line 25*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_127_96,
262 /*line 26*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_PF_7_0,
268 /*line 27*/{(0x1C), 1, PGLUE_B_REG_RX_ERR_DETAILS,
274 /*line 28*/{(0x1C), 1, PGLUE_B_REG_RX_TCPL_ERR_DETAILS,
280 /*line 29*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_ADD_31_0,
286 /*line 30*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_ADD_63_32,
292 /*line 31*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_DETAILS,
298 /*line 32*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_DETAILS2,
304 /*line 33*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_ADD_31_0,
310 /*line 34*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_ADD_63_32,
316 /*line 35*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_DETAILS,
322 /*line 36*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_DETAILS2,
328 /*line 37*/{(0x1C), 1, PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS,
334 /*line 38*/{(0x1C), 1, PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS,
340 /*line 39*/{(0x1C), 1, PGLUE_B_REG_TAGS_63_32,
346 /*line 40*/{(0x1C), 3, PXP_REG_HST_VF_DISABLED_ERROR_VALID,
352 /*line 41*/{(0x1C), 1, PXP_REG_HST_PER_VIOLATION_VALID,
358 /*line 42*/{(0x1C), 1, PXP_REG_HST_INCORRECT_ACCESS_VALID,
364 /*line 43*/{(0x1C), 1, PXP2_REG_RD_CPL_ERR_DETAILS,
370 /*line 44*/{(0x1C), 1, PXP2_REG_RD_CPL_ERR_DETAILS2,
376 /*line 45*/{(0x1F), 1, PXP2_REG_RQ_VQ0_ENTRY_CNT,
382 /*line 46*/{(0x1F), 1, PXP2_REG_RQ_VQ1_ENTRY_CNT,
388 /*line 47*/{(0x1F), 1, PXP2_REG_RQ_VQ2_ENTRY_CNT,
394 /*line 48*/{(0x1F), 1, PXP2_REG_RQ_VQ3_ENTRY_CNT,
400 /*line 49*/{(0x1F), 1, PXP2_REG_RQ_VQ4_ENTRY_CNT,
406 /*line 50*/{(0x1F), 1, PXP2_REG_RQ_VQ5_ENTRY_CNT,
412 /*line 51*/{(0x1F), 1, PXP2_REG_RQ_VQ6_ENTRY_CNT,
418 /*line 52*/{(0x1F), 1, PXP2_REG_RQ_VQ7_ENTRY_CNT,
424 /*line 53*/{(0x1F), 1, PXP2_REG_RQ_VQ8_ENTRY_CNT,
430 /*line 54*/{(0x1F), 1, PXP2_REG_RQ_VQ9_ENTRY_CNT,
436 /*line 55*/{(0x1F), 1, PXP2_REG_RQ_VQ10_ENTRY_CNT,
442 /*line 56*/{(0x1F), 1, PXP2_REG_RQ_VQ11_ENTRY_CNT,
448 /*line 57*/{(0x1F), 1, PXP2_REG_RQ_VQ12_ENTRY_CNT,
454 /*line 58*/{(0x1F), 1, PXP2_REG_RQ_VQ13_ENTRY_CNT,
460 /*line 59*/{(0x1F), 1, PXP2_REG_RQ_VQ14_ENTRY_CNT,
466 /*line 60*/{(0x1F), 1, PXP2_REG_RQ_VQ15_ENTRY_CNT,
472 /*line 61*/{(0x1F), 1, PXP2_REG_RQ_VQ16_ENTRY_CNT,
478 /*line 62*/{(0x1F), 1, PXP2_REG_RQ_VQ17_ENTRY_CNT,
484 /*line 63*/{(0x1F), 1, PXP2_REG_RQ_VQ18_ENTRY_CNT,
490 /*line 64*/{(0x1F), 1, PXP2_REG_RQ_VQ19_ENTRY_CNT,
496 /*line 65*/{(0x1F), 1, PXP2_REG_RQ_VQ20_ENTRY_CNT,
502 /*line 66*/{(0x1F), 1, PXP2_REG_RQ_VQ21_ENTRY_CNT,
508 /*line 67*/{(0x1F), 1, PXP2_REG_RQ_VQ22_ENTRY_CNT,
514 /*line 68*/{(0x1F), 1, PXP2_REG_RQ_VQ23_ENTRY_CNT,
520 /*line 69*/{(0x1F), 1, PXP2_REG_RQ_VQ24_ENTRY_CNT,
526 /*line 70*/{(0x1F), 1, PXP2_REG_RQ_VQ25_ENTRY_CNT,
532 /*line 71*/{(0x1F), 1, PXP2_REG_RQ_VQ26_ENTRY_CNT,
538 /*line 72*/{(0x1F), 1, PXP2_REG_RQ_VQ27_ENTRY_CNT,
544 /*line 73*/{(0x1F), 1, PXP2_REG_RQ_VQ28_ENTRY_CNT,
550 /*line 74*/{(0x1F), 1, PXP2_REG_RQ_VQ29_ENTRY_CNT,
556 /*line 75*/{(0x1F), 1, PXP2_REG_RQ_VQ30_ENTRY_CNT,
562 /*line 76*/{(0x1F), 1, PXP2_REG_RQ_VQ31_ENTRY_CNT,
568 /*line 77*/{(0x1F), 1, PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY,
574 /*line 78*/{(0x1F), 1, PXP2_REG_RQ_RBC_DONE,
580 /*line 79*/{(0x1F), 1, PXP2_REG_RQ_CFG_DONE,
586 /*line 80*/{(0x3), 1, PXP2_REG_PSWRQ_BW_CREDIT,
592 /*line 81*/{(0x1F), 1, PXP2_REG_RD_START_INIT,
598 /*line 82*/{(0x1F), 1, PXP2_REG_RD_INIT_DONE,
604 /*line 83*/{(0x1F), 3, PXP2_REG_RD_SR_CNT,
610 /*line 84*/{(0x1F), 3, PXP2_REG_RD_BLK_CNT,
616 /*line 85*/{(0x1F), 3, PXP2_REG_RD_SR_CNT,
622 /*line 86*/{(0x1F), 3, PXP2_REG_RD_BLK_CNT,
628 /*line 87*/{(0x1F), 1, PXP2_REG_RD_PORT_IS_IDLE_0,
634 /*line 88*/{(0x1F), 1, PXP2_REG_RD_PORT_IS_IDLE_1,
640 /*line 89*/{(0x1F), 2, PXP2_REG_RD_ALMOST_FULL_0,
646 /*line 90*/{(0x1F), 1, PXP2_REG_RD_DISABLE_INPUTS,
652 /*line 91*/{(0x1F), 1, PXP2_REG_HST_HEADER_FIFO_STATUS,
658 /*line 92*/{(0x1F), 1, PXP2_REG_HST_DATA_FIFO_STATUS,
664 /*line 93*/{(0x3), 1, PXP2_REG_PGL_WRITE_BLOCKED,
670 /*line 94*/{(0x3), 1, PXP2_REG_PGL_READ_BLOCKED,
676 /*line 95*/{(0x1C), 1, PXP2_REG_PGL_WRITE_BLOCKED,
682 /*line 96*/{(0x1C), 1, PXP2_REG_PGL_READ_BLOCKED,
688 /*line 97*/{(0x1F), 1, PXP2_REG_PGL_TXW_CDTS,
694 /*line 98*/{(0x1F), 1, PXP_REG_HST_ARB_IS_IDLE,
700 /*line 99*/{(0x1F), 1, PXP_REG_HST_CLIENTS_WAITING_TO_ARB,
706 /*line 100*/{(0x1E), 1, PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS,
712 /*line 101*/{(0x1E), 1, PXP_REG_HST_DISCARD_DOORBELLS_STATUS,
718 /*line 102*/{(0x1C), 1, PXP2_REG_RQ_GARB,
724 /*line 103*/{(0x1F), 1, DMAE_REG_GO_C0,
730 /*line 104*/{(0x1F), 1, DMAE_REG_GO_C1,
736 /*line 105*/{(0x1F), 1, DMAE_REG_GO_C2,
742 /*line 106*/{(0x1F), 1, DMAE_REG_GO_C3,
748 /*line 107*/{(0x1F), 1, DMAE_REG_GO_C4,
754 /*line 108*/{(0x1F), 1, DMAE_REG_GO_C5,
760 /*line 109*/{(0x1F), 1, DMAE_REG_GO_C6,
766 /*line 110*/{(0x1F), 1, DMAE_REG_GO_C7,
772 /*line 111*/{(0x1F), 1, DMAE_REG_GO_C8,
778 /*line 112*/{(0x1F), 1, DMAE_REG_GO_C9,
784 /*line 113*/{(0x1F), 1, DMAE_REG_GO_C10,
790 /*line 114*/{(0x1F), 1, DMAE_REG_GO_C11,
796 /*line 115*/{(0x1F), 1, DMAE_REG_GO_C12,
802 /*line 116*/{(0x1F), 1, DMAE_REG_GO_C13,
808 /*line 117*/{(0x1F), 1, DMAE_REG_GO_C14,
814 /*line 118*/{(0x1F), 1, DMAE_REG_GO_C15,
820 /*line 119*/{(0x1F), 1, CFC_REG_ERROR_VECTOR,
826 /*line 120*/{(0x1F), 1, CFC_REG_NUM_LCIDS_ARRIVING,
832 /*line 121*/{(0x1F), 1, CFC_REG_NUM_LCIDS_ALLOC,
838 /*line 122*/{(0x1F), 1, CFC_REG_NUM_LCIDS_LEAVING,
844 /*line 123*/{(0x1F), 7, CFC_REG_INFO_RAM,
850 /*line 124*/{(0x1F), 7, CFC_REG_INFO_RAM,
856 /*line 125*/{(0x1F), 7, CFC_REG_INFO_RAM,
862 /*line 126*/{(0x1F), 7, CFC_REG_INFO_RAM,
868 /*line 127*/{(0x1F), 2, QM_REG_QTASKCTR_0,
874 /*line 128*/{(0xF), 3, QM_REG_VOQCREDIT_0,
880 /*line 129*/{(0xF), 3, QM_REG_VOQCREDIT_1,
886 /*line 130*/{(0xF), 3, QM_REG_VOQCREDIT_4,
892 /*line 131*/{(0x3), 3, QM_REG_PORT0BYTECRD,
898 /*line 132*/{(0x3), 3, QM_REG_PORT1BYTECRD,
904 /*line 133*/{(0x1F), 1, CCM_REG_CAM_OCCUP,
910 /*line 134*/{(0x1F), 1, TCM_REG_CAM_OCCUP,
916 /*line 135*/{(0x1F), 1, UCM_REG_CAM_OCCUP,
922 /*line 136*/{(0x1F), 1, XCM_REG_CAM_OCCUP,
928 /*line 137*/{(0x1F), 1, BRB1_REG_NUM_OF_FULL_BLOCKS,
934 /*line 138*/{(0x1F), 1, CSEM_REG_SLEEP_THREADS_VALID,
940 /*line 139*/{(0x1F), 1, TSEM_REG_SLEEP_THREADS_VALID,
946 /*line 140*/{(0x1F), 1, USEM_REG_SLEEP_THREADS_VALID,
952 /*line 141*/{(0x1F), 1, XSEM_REG_SLEEP_THREADS_VALID,
958 /*line 142*/{(0x1F), 1, CSEM_REG_SLOW_EXT_STORE_EMPTY,
964 /*line 143*/{(0x1F), 1, TSEM_REG_SLOW_EXT_STORE_EMPTY,
970 /*line 144*/{(0x1F), 1, USEM_REG_SLOW_EXT_STORE_EMPTY,
976 /*line 145*/{(0x1F), 1, XSEM_REG_SLOW_EXT_STORE_EMPTY,
982 /*line 146*/{(0x1F), 1, CSDM_REG_SYNC_PARSER_EMPTY,
988 /*line 147*/{(0x1F), 1, TSDM_REG_SYNC_PARSER_EMPTY,
994 /*line 148*/{(0x1F), 1, USDM_REG_SYNC_PARSER_EMPTY,
1000 /*line 149*/{(0x1F), 1, XSDM_REG_SYNC_PARSER_EMPTY,
1006 /*line 150*/{(0x1F), 1, CSDM_REG_SYNC_SYNC_EMPTY,
1012 /*line 151*/{(0x1F), 1, TSDM_REG_SYNC_SYNC_EMPTY,
1018 /*line 152*/{(0x1F), 1, USDM_REG_SYNC_SYNC_EMPTY,
1024 /*line 153*/{(0x1F), 1, XSDM_REG_SYNC_SYNC_EMPTY,
1030 /*line 154*/{(0x1F), 1, CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY,
1036 /*line 155*/{(0x1F), 1, TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY,
1042 /*line 156*/{(0x1F), 1, USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY,
1048 /*line 157*/{(0x1F), 1, XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY,
1054 /*line 158*/{(0x1F), 1, DORQ_REG_DQ_FILL_LVLF,
1060 /*line 159*/{(0x1F), 1, CFC_REG_CFC_INT_STS,
1066 /*line 160*/{(0x1F), 1, CDU_REG_CDU_INT_STS,
1072 /*line 161*/{(0x1F), 1, CCM_REG_CCM_INT_STS,
1078 /*line 162*/{(0x1F), 1, TCM_REG_TCM_INT_STS,
1084 /*line 163*/{(0x1F), 1, UCM_REG_UCM_INT_STS,
1090 /*line 164*/{(0x1F), 1, XCM_REG_XCM_INT_STS,
1096 /*line 165*/{(0xF), 1, PBF_REG_PBF_INT_STS,
1102 /*line 166*/{(0x1F), 1, TM_REG_TM_INT_STS,
1108 /*line 167*/{(0x1F), 1, DORQ_REG_DORQ_INT_STS,
1114 /*line 168*/{(0x1F), 1, SRC_REG_SRC_INT_STS,
1120 /*line 169*/{(0x1F), 1, PRS_REG_PRS_INT_STS,
1126 /*line 170*/{(0x1F), 1, BRB1_REG_BRB1_INT_STS,
1132 /*line 171*/{(0x1F), 1, GRCBASE_XPB + PB_REG_PB_INT_STS,
1138 /*line 172*/{(0x1F), 1, GRCBASE_UPB + PB_REG_PB_INT_STS,
1144 /*line 173*/{(0x1), 1, PXP2_REG_PXP2_INT_STS,
1150 /*line 174*/{(0x1E), 1, PXP2_REG_PXP2_INT_STS_0,
1156 /*line 175*/{(0x1E), 1, PXP2_REG_PXP2_INT_STS_1,
1162 /*line 176*/{(0x1F), 1, QM_REG_QM_INT_STS,
1168 /*line 177*/{(0x1F), 1, PXP_REG_PXP_INT_STS_0,
1174 /*line 178*/{(0x1F), 1, PXP_REG_PXP_INT_STS_1,
1180 /*line 179*/{(0x1C), 1, PGLUE_B_REG_PGLUE_B_INT_STS,
1186 /*line 180*/{(0x1F), 1, DORQ_REG_RSPA_CRD_CNT,
1192 /*line 181*/{(0x1F), 1, DORQ_REG_RSPB_CRD_CNT,
1198 /*line 182*/{(0x3), 1, QM_REG_VOQCRDERRREG,
1204 /*line 183*/{(0x1F), 1, DORQ_REG_DQ_FULL_ST,
1210 /*line 184*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0,
1216 /*line 185*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0,
1222 /*line 186*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0,
1228 /*line 187*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0,
1234 /*line 188*/{(0x3), 1, MISC_REG_AEU_AFTER_INVERT_1_FUNC_1,
1240 /*line 189*/{(0x3), 1, MISC_REG_AEU_AFTER_INVERT_2_FUNC_1,
1246 /*line 190*/{(0x3), 1, MISC_REG_AEU_AFTER_INVERT_3_FUNC_1,
1252 /*line 191*/{(0x3), 1, MISC_REG_AEU_AFTER_INVERT_4_FUNC_1,
1258 /*line 192*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_1_MCP,
1264 /*line 193*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_2_MCP,
1270 /*line 194*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_3_MCP,
1276 /*line 195*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_4_MCP,
1282 /*line 196*/{(0xF), 5, PBF_REG_P0_CREDIT,
1288 /*line 197*/{(0xF), 5, PBF_REG_P1_CREDIT,
1294 /*line 198*/{(0xF), 3, PBF_REG_P4_CREDIT,
1300 /*line 199*/{(0x10), 5, PBF_REG_CREDIT_Q0,
1306 /*line 200*/{(0x10), 5, PBF_REG_CREDIT_Q1,
1312 /*line 201*/{(0x10), 5, PBF_REG_CREDIT_Q2,
1318 /*line 202*/{(0x10), 5, PBF_REG_CREDIT_Q3,
1324 /*line 203*/{(0x10), 5, PBF_REG_CREDIT_Q4,
1330 /*line 204*/{(0x10), 5, PBF_REG_CREDIT_Q5,
1336 /*line 205*/{(0x10), 3, PBF_REG_CREDIT_LB_Q,
1342 /*line 206*/{(0xF), 1, PBF_REG_P0_TASK_CNT,
1348 /*line 207*/{(0xF), 1, PBF_REG_P1_TASK_CNT,
1354 /*line 208*/{(0xF), 1, PBF_REG_P4_TASK_CNT,
1360 /*line 209*/{(0x10), 1, PBF_REG_TASK_CNT_Q0,
1366 /*line 210*/{(0x10), 1, PBF_REG_TASK_CNT_Q1,
1372 /*line 211*/{(0x10), 1, PBF_REG_TASK_CNT_Q2,
1378 /*line 212*/{(0x10), 1, PBF_REG_TASK_CNT_Q3,
1384 /*line 213*/{(0x10), 1, PBF_REG_TASK_CNT_Q4,
1390 /*line 214*/{(0x10), 1, PBF_REG_TASK_CNT_Q5,
1396 /*line 215*/{(0x10), 1, PBF_REG_TASK_CNT_LB_Q,
1402 /*line 216*/{(0x1F), 1, XCM_REG_CFC_INIT_CRD,
1408 /*line 217*/{(0x1F), 1, UCM_REG_CFC_INIT_CRD,
1414 /*line 218*/{(0x1F), 1, TCM_REG_CFC_INIT_CRD,
1420 /*line 219*/{(0x1F), 1, CCM_REG_CFC_INIT_CRD,
1426 /*line 220*/{(0x1F), 1, XCM_REG_XQM_INIT_CRD,
1432 /*line 221*/{(0x1F), 1, UCM_REG_UQM_INIT_CRD,
1438 /*line 222*/{(0x1F), 1, TCM_REG_TQM_INIT_CRD,
1444 /*line 223*/{(0x1F), 1, CCM_REG_CQM_INIT_CRD,
1450 /*line 224*/{(0x1F), 1, XCM_REG_TM_INIT_CRD,
1456 /*line 225*/{(0x1F), 1, UCM_REG_TM_INIT_CRD,
1462 /*line 226*/{(0x1F), 1, XCM_REG_FIC0_INIT_CRD,
1468 /*line 227*/{(0x1F), 1, UCM_REG_FIC0_INIT_CRD,
1474 /*line 228*/{(0x1F), 1, TCM_REG_FIC0_INIT_CRD,
1480 /*line 229*/{(0x1F), 1, CCM_REG_FIC0_INIT_CRD,
1486 /*line 230*/{(0x1F), 1, XCM_REG_FIC1_INIT_CRD,
1492 /*line 231*/{(0x1F), 1, UCM_REG_FIC1_INIT_CRD,
1498 /*line 232*/{(0x1F), 1, TCM_REG_FIC1_INIT_CRD,
1504 /*line 233*/{(0x1F), 1, CCM_REG_FIC1_INIT_CRD,
1510 /*line 234*/{(0x1), 1, XCM_REG_XX_FREE,
1516 /*line 235*/{(0x1E), 1, XCM_REG_XX_FREE,
1522 /*line 236*/{(0x1F), 1, UCM_REG_XX_FREE,
1528 /*line 237*/{(0x7), 1, TCM_REG_XX_FREE,
1534 /*line 238*/{(0x18), 1, TCM_REG_XX_FREE,
1540 /*line 239*/{(0x1F), 1, CCM_REG_XX_FREE,
1546 /*line 240*/{(0x1F), 1, XSEM_REG_FAST_MEMORY + 0x18000,
1552 /*line 241*/{(0x1F), 1, XSEM_REG_FAST_MEMORY + 0x18040,
1558 /*line 242*/{(0x1F), 1, XSEM_REG_FAST_MEMORY + 0x18080,
1564 /*line 243*/{(0x1F), 1, USEM_REG_FAST_MEMORY + 0x18000,
1570 /*line 244*/{(0x1F), 1, USEM_REG_FAST_MEMORY + 0x18040,
1576 /*line 245*/{(0x1F), 1, USEM_REG_FAST_MEMORY + 0x18080,
1582 /*line 246*/{(0x1F), 1, USEM_REG_FAST_MEMORY + 0x180C0,
1588 /*line 247*/{(0x1F), 1, TSEM_REG_FAST_MEMORY + 0x18000,
1594 /*line 248*/{(0x1F), 1, TSEM_REG_FAST_MEMORY + 0x18040,
1600 /*line 249*/{(0x1F), 1, TSEM_REG_FAST_MEMORY + 0x18080,
1606 /*line 250*/{(0x1F), 1, TSEM_REG_FAST_MEMORY + 0x180C0,
1612 /*line 251*/{(0x1F), 1, CSEM_REG_FAST_MEMORY + 0x18000,
1618 /*line 252*/{(0x1F), 1, CSEM_REG_FAST_MEMORY + 0x18040,
1624 /*line 253*/{(0x1F), 1, CSEM_REG_FAST_MEMORY + 0x18080,
1630 /*line 254*/{(0x1F), 1, CSEM_REG_FAST_MEMORY + 0x180C0,
1636 /*line 255*/{(0x1F), 1, PRS_REG_TSDM_CURRENT_CREDIT,
1642 /*line 256*/{(0x1F), 1, PRS_REG_TCM_CURRENT_CREDIT,
1648 /*line 257*/{(0x1F), 1, PRS_REG_CFC_LD_CURRENT_CREDIT,
1654 /*line 258*/{(0x1F), 1, PRS_REG_CFC_SEARCH_CURRENT_CREDIT,
1660 /*line 259*/{(0x1F), 1, PRS_REG_SRC_CURRENT_CREDIT,
1666 /*line 260*/{(0x1F), 1, PRS_REG_PENDING_BRB_PRS_RQ,
1672 /*line 261*/{(0x1F), 2, PRS_REG_PENDING_BRB_CAC0_RQ,
1678 /*line 262*/{(0x1F), 1, PRS_REG_SERIAL_NUM_STATUS_LSB,
1684 /*line 263*/{(0x1F), 1, PRS_REG_SERIAL_NUM_STATUS_MSB,
1690 /*line 264*/{(0x1F), 1, CDU_REG_ERROR_DATA,
1696 /*line 265*/{(0x1F), 1, CCM_REG_STORM_LENGTH_MIS,
1702 /*line 266*/{(0x1F), 1, CCM_REG_CSDM_LENGTH_MIS,
1708 /*line 267*/{(0x1F), 1, CCM_REG_TSEM_LENGTH_MIS,
1714 /*line 268*/{(0x1F), 1, CCM_REG_XSEM_LENGTH_MIS,
1720 /*line 269*/{(0x1F), 1, CCM_REG_USEM_LENGTH_MIS,
1726 /*line 270*/{(0x1F), 1, CCM_REG_PBF_LENGTH_MIS,
1732 /*line 271*/{(0x1F), 1, TCM_REG_STORM_LENGTH_MIS,
1738 /*line 272*/{(0x1F), 1, TCM_REG_TSDM_LENGTH_MIS,
1744 /*line 273*/{(0x1F), 1, TCM_REG_PRS_LENGTH_MIS,
1750 /*line 274*/{(0x1F), 1, TCM_REG_PBF_LENGTH_MIS,
1756 /*line 275*/{(0x1F), 1, TCM_REG_USEM_LENGTH_MIS,
1762 /*line 276*/{(0x1F), 1, TCM_REG_CSEM_LENGTH_MIS,
1768 /*line 277*/{(0x1F), 1, UCM_REG_STORM_LENGTH_MIS,
1774 /*line 278*/{(0x1F), 1, UCM_REG_USDM_LENGTH_MIS,
1780 /*line 279*/{(0x1F), 1, UCM_REG_TSEM_LENGTH_MIS,
1786 /*line 280*/{(0x1F), 1, UCM_REG_CSEM_LENGTH_MIS,
1792 /*line 281*/{(0x1F), 1, UCM_REG_XSEM_LENGTH_MIS,
1798 /*line 282*/{(0x1F), 1, UCM_REG_DORQ_LENGTH_MIS,
1804 /*line 283*/{(0x1F), 1, XCM_REG_STORM_LENGTH_MIS,
1810 /*line 284*/{(0x1F), 1, XCM_REG_XSDM_LENGTH_MIS,
1816 /*line 285*/{(0x1F), 1, XCM_REG_TSEM_LENGTH_MIS,
1822 /*line 286*/{(0x1F), 1, XCM_REG_CSEM_LENGTH_MIS,
1828 /*line 287*/{(0x1F), 1, XCM_REG_USEM_LENGTH_MIS,
1834 /*line 288*/{(0x1F), 1, XCM_REG_DORQ_LENGTH_MIS,
1840 /*line 289*/{(0x1F), 1, XCM_REG_PBF_LENGTH_MIS,
1846 /*line 290*/{(0x1F), 1, XCM_REG_NIG0_LENGTH_MIS,
1852 /*line 291*/{(0x1F), 1, XCM_REG_NIG1_LENGTH_MIS,
1858 /*line 292*/{(0x1F), 1, QM_REG_XQM_WRC_FIFOLVL,
1864 /*line 293*/{(0x1F), 1, QM_REG_UQM_WRC_FIFOLVL,
1870 /*line 294*/{(0x1F), 1, QM_REG_TQM_WRC_FIFOLVL,
1876 /*line 295*/{(0x1F), 1, QM_REG_CQM_WRC_FIFOLVL,
1882 /*line 296*/{(0x1F), 1, QM_REG_QSTATUS_LOW,
1888 /*line 297*/{(0x1F), 1, QM_REG_QSTATUS_HIGH,
1894 /*line 298*/{(0x1F), 1, QM_REG_PAUSESTATE0,
1900 /*line 299*/{(0x1F), 1, QM_REG_PAUSESTATE1,
1906 /*line 300*/{(0x1F), 1, QM_REG_OVFQNUM,
1912 /*line 301*/{(0x1F), 1, QM_REG_OVFERROR,
1918 /*line 302*/{(0x1F), 6, QM_REG_PTRTBL,
1924 /*line 303*/{(0x1F), 1, BRB1_REG_BRB1_PRTY_STS,
1930 /*line 304*/{(0x1F), 1, CDU_REG_CDU_PRTY_STS,
1936 /*line 305*/{(0x1F), 1, CFC_REG_CFC_PRTY_STS,
1942 /*line 306*/{(0x1F), 1, CSDM_REG_CSDM_PRTY_STS,
1948 /*line 307*/{(0x3), 1, DBG_REG_DBG_PRTY_STS,
1954 /*line 308*/{(0x1F), 1, DMAE_REG_DMAE_PRTY_STS,
1960 /*line 309*/{(0x1F), 1, DORQ_REG_DORQ_PRTY_STS,
1966 /*line 310*/{(0x1), 1, TCM_REG_TCM_PRTY_STS,
1972 /*line 311*/{(0x1E), 1, TCM_REG_TCM_PRTY_STS,
1978 /*line 312*/{(0x1), 1, CCM_REG_CCM_PRTY_STS,
1984 /*line 313*/{(0x1E), 1, CCM_REG_CCM_PRTY_STS,
1990 /*line 314*/{(0x1), 1, UCM_REG_UCM_PRTY_STS,
1996 /*line 315*/{(0x1E), 1, UCM_REG_UCM_PRTY_STS,
2002 /*line 316*/{(0x1), 1, XCM_REG_XCM_PRTY_STS,
2008 /*line 317*/{(0x1E), 1, XCM_REG_XCM_PRTY_STS,
2014 /*line 318*/{(0x1), 1, HC_REG_HC_PRTY_STS,
2020 /*line 319*/{(0x1), 1, MISC_REG_MISC_PRTY_STS,
2026 /*line 320*/{(0x1F), 1, PRS_REG_PRS_PRTY_STS,
2032 /*line 321*/{(0x1F), 1, PXP_REG_PXP_PRTY_STS,
2038 /*line 322*/{(0x1F), 1, QM_REG_QM_PRTY_STS,
2044 /*line 323*/{(0x1), 1, SRC_REG_SRC_PRTY_STS,
2050 /*line 324*/{(0x1F), 1, TSDM_REG_TSDM_PRTY_STS,
2056 /*line 325*/{(0x1F), 1, USDM_REG_USDM_PRTY_STS,
2062 /*line 326*/{(0x1F), 1, XSDM_REG_XSDM_PRTY_STS,
2068 /*line 327*/{(0x1F), 1, GRCBASE_XPB + PB_REG_PB_PRTY_STS,
2074 /*line 328*/{(0x1F), 1, GRCBASE_UPB + PB_REG_PB_PRTY_STS,
2080 /*line 329*/{(0x1F), 1, CSEM_REG_CSEM_PRTY_STS_0,
2086 /*line 330*/{(0x1), 1, PXP2_REG_PXP2_PRTY_STS_0,
2092 /*line 331*/{(0x1E), 1, PXP2_REG_PXP2_PRTY_STS_0,
2098 /*line 332*/{(0x1F), 1, TSEM_REG_TSEM_PRTY_STS_0,
2104 /*line 333*/{(0x1F), 1, USEM_REG_USEM_PRTY_STS_0,
2110 /*line 334*/{(0x1F), 1, XSEM_REG_XSEM_PRTY_STS_0,
2116 /*line 335*/{(0x1F), 1, CSEM_REG_CSEM_PRTY_STS_1,
2122 /*line 336*/{(0x1), 1, PXP2_REG_PXP2_PRTY_STS_1,
2128 /*line 337*/{(0x1E), 1, PXP2_REG_PXP2_PRTY_STS_1,
2134 /*line 338*/{(0x1F), 1, TSEM_REG_TSEM_PRTY_STS_1,
2140 /*line 339*/{(0x1F), 1, USEM_REG_USEM_PRTY_STS_1,
2146 /*line 340*/{(0x1F), 1, XSEM_REG_XSEM_PRTY_STS_1,
2152 /*line 341*/{(0x1C), 1, PGLUE_B_REG_PGLUE_B_PRTY_STS,
2158 /*line 342*/{(0x2), 2, QM_REG_QTASKCTR_EXT_A_0,
2164 /*line 343*/{(0x2), 1, QM_REG_QSTATUS_LOW_EXT_A,
2170 /*line 344*/{(0x2), 1, QM_REG_QSTATUS_HIGH_EXT_A,
2176 /*line 345*/{(0x1E), 1, QM_REG_PAUSESTATE2,
2182 /*line 346*/{(0x1E), 1, QM_REG_PAUSESTATE3,
2188 /*line 347*/{(0x2), 1, QM_REG_PAUSESTATE4,
2194 /*line 348*/{(0x2), 1, QM_REG_PAUSESTATE5,
2200 /*line 349*/{(0x2), 1, QM_REG_PAUSESTATE6,
2206 /*line 350*/{(0x2), 1, QM_REG_PAUSESTATE7,
2212 /*line 351*/{(0x2), 6, QM_REG_PTRTBL_EXT_A,
2218 /*line 352*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_OCCURRED,
2224 /*line 353*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_STATUS_0,
2230 /*line 354*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_STATUS_1,
2236 /*line 355*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_STATUS_2,
2242 /*line 356*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_STATUS_3,
2248 /*line 357*/{(0x1E), 1, MISC_REG_PCIE_HOT_RESET,
2254 /*line 358*/{(0x1F), 1, NIG_REG_NIG_INT_STS_0,
2260 /*line 359*/{(0x1F), 1, NIG_REG_NIG_INT_STS_0,
2266 /*line 360*/{(0x1F), 1, NIG_REG_NIG_INT_STS_1,
2272 /*line 361*/{(0x1F), 1, NIG_REG_NIG_INT_STS_1,
2278 /*line 362*/{(0x1F), 1, NIG_REG_NIG_INT_STS_1,
2284 /*line 363*/{(0x2), 1, NIG_REG_NIG_PRTY_STS,
2290 /*line 364*/{(0x1C), 1, NIG_REG_NIG_PRTY_STS_0,
2296 /*line 365*/{(0x4), 1, NIG_REG_NIG_PRTY_STS_1,
2302 /*line 366*/{(0x18), 1, NIG_REG_NIG_PRTY_STS_1,
2308 /*line 367*/{(0x1F), 1, TSEM_REG_TSEM_INT_STS_0,
2314 /*line 368*/{(0x1F), 1, TSEM_REG_TSEM_INT_STS_0,
2320 /*line 369*/{(0x1F), 1, TSEM_REG_TSEM_INT_STS_1,
2326 /*line 370*/{(0x1F), 1, CSEM_REG_CSEM_INT_STS_0,
2332 /*line 371*/{(0x1F), 1, CSEM_REG_CSEM_INT_STS_0,
2338 /*line 372*/{(0x1F), 1, CSEM_REG_CSEM_INT_STS_1,
2344 /*line 373*/{(0x1F), 1, USEM_REG_USEM_INT_STS_0,
2350 /*line 374*/{(0x1F), 1, USEM_REG_USEM_INT_STS_0,
2356 /*line 375*/{(0x1F), 1, USEM_REG_USEM_INT_STS_1,
2362 /*line 376*/{(0x1F), 1, XSEM_REG_XSEM_INT_STS_0,
2368 /*line 377*/{(0x1F), 1, XSEM_REG_XSEM_INT_STS_0,
2374 /*line 378*/{(0x1F), 1, XSEM_REG_XSEM_INT_STS_1,
2380 /*line 379*/{(0x1F), 1, TSDM_REG_TSDM_INT_STS_0,
2386 /*line 380*/{(0x1F), 1, TSDM_REG_TSDM_INT_STS_1,
2392 /*line 381*/{(0x1F), 1, CSDM_REG_CSDM_INT_STS_0,
2398 /*line 382*/{(0x1F), 1, CSDM_REG_CSDM_INT_STS_1,
2404 /*line 383*/{(0x1F), 1, USDM_REG_USDM_INT_STS_0,
2410 /*line 384*/{(0x1F), 1, USDM_REG_USDM_INT_STS_1,
2416 /*line 385*/{(0x1F), 1, XSDM_REG_XSDM_INT_STS_0,
2422 /*line 386*/{(0x1F), 1, XSDM_REG_XSDM_INT_STS_1,
2428 /*line 387*/{(0x2), 1, HC_REG_HC_PRTY_STS,
2434 /*line 388*/{(0x1E), 1, MISC_REG_MISC_PRTY_STS,
2440 /*line 389*/{(0x1E), 1, SRC_REG_SRC_PRTY_STS,
2446 /*line 390*/{(0xC), 3, QM_REG_BYTECRD0,
2452 /*line 391*/{(0xC), 3, QM_REG_BYTECRD1,
2458 /*line 392*/{(0xC), 3, QM_REG_BYTECRD2,
2464 /*line 393*/{(0x1C), 1, QM_REG_VOQCRDERRREG,
2470 /*line 394*/{(0x1C), 1, QM_REG_BYTECRDERRREG,
2476 /*line 395*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_VF_31_0,
2482 /*line 396*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_VF_63_32,
2488 /*line 397*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_VF_95_64,
2494 /*line 398*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_VF_127_96,
2500 /*line 399*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_PF_7_0,
2506 /*line 400*/{(0x1C), 1, PGLUE_B_REG_SR_IOV_DISABLED_REQUEST,
2512 /*line 401*/{(0x1C), 1, PGLUE_B_REG_CFG_SPACE_A_REQUEST,
2518 /*line 402*/{(0x1C), 1, PGLUE_B_REG_CFG_SPACE_B_REQUEST,
2524 /*line 403*/{(0x1C), 1, IGU_REG_ERROR_HANDLING_DATA_VALID,
2530 /*line 404*/{(0x1C), 1, IGU_REG_ATTN_WRITE_DONE_PENDING,
2536 /*line 405*/{(0x1C), 1, IGU_REG_WRITE_DONE_PENDING,
2542 /*line 406*/{(0x1C), 1, IGU_REG_IGU_PRTY_STS,
2548 /*line 407*/{(0x1E), 3, MISC_REG_GRC_TIMEOUT_ATTN,
2554 /*line 408*/{(0x1C), 3, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID,
2560 /*line 409*/{(0x1E), 3, MISC_REG_GRC_TIMEOUT_ATTN,
2566 /*line 410*/{(0x1C), 3, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID,
2572 /*line 411*/{(0x1E), 3, MISC_REG_GRC_TIMEOUT_ATTN,
2578 /*line 412*/{(0x1C), 3, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID,
2584 /*line 413*/{(0x1C), 1, IGU_REG_SILENT_DROP,
2590 /*line 414*/{(0x1C), 1, PXP2_REG_PSWRQ_BW_CREDIT,
2596 /*line 415*/{(0x1C), 1, IGU_REG_SB_CTRL_FSM,
2602 /*line 416*/{(0x1C), 1, IGU_REG_INT_HANDLE_FSM,
2608 /*line 417*/{(0x1C), 1, IGU_REG_ATTN_FSM,
2614 /*line 418*/{(0x1C), 1, IGU_REG_CTRL_FSM,
2620 /*line 419*/{(0x1C), 1, IGU_REG_PXP_ARB_FSM,
2626 /*line 420*/{(0x1C), 1, IGU_REG_PENDING_BITS_STATUS,
2632 /*line 421*/{(0x10), 3, QM_REG_VOQCREDIT_0,
2638 /*line 422*/{(0x10), 3, QM_REG_VOQCREDIT_1,
2644 /*line 423*/{(0x10), 3, QM_REG_VOQCREDIT_2,
2650 /*line 424*/{(0x10), 3, QM_REG_VOQCREDIT_3,
2656 /*line 425*/{(0x10), 3, QM_REG_VOQCREDIT_4,
2662 /*line 426*/{(0x10), 3, QM_REG_VOQCREDIT_5,
2668 /*line 427*/{(0x10), 3, QM_REG_VOQCREDIT_6,
2674 /*line 428*/{(0x10), 3, QM_REG_BYTECRD0,
2680 /*line 429*/{(0x10), 3, QM_REG_BYTECRD1,
2686 /*line 430*/{(0x10), 3, QM_REG_BYTECRD2,
2692 /*line 431*/{(0x10), 3, QM_REG_BYTECRD3,
2698 /*line 432*/{(0x10), 3, QM_REG_BYTECRD4,
2704 /*line 433*/{(0x10), 3, QM_REG_BYTECRD5,
2710 /*line 434*/{(0x10), 3, QM_REG_BYTECRD6,
2716 /*line 435*/{(0x10), 1, QM_REG_FWVOQ0TOHWVOQ,
2722 /*line 436*/{(0x10), 1, QM_REG_FWVOQ1TOHWVOQ,
2728 /*line 437*/{(0x10), 1, QM_REG_FWVOQ2TOHWVOQ,
2734 /*line 438*/{(0x10), 1, QM_REG_FWVOQ3TOHWVOQ,
2740 /*line 439*/{(0x10), 1, QM_REG_FWVOQ4TOHWVOQ,
2746 /*line 440*/{(0x10), 1, QM_REG_FWVOQ5TOHWVOQ,
2752 /*line 441*/{(0x10), 1, QM_REG_FWVOQ6TOHWVOQ,
2758 /*line 442*/{(0x10), 1, QM_REG_FWVOQ7TOHWVOQ,
2764 /*line 443*/{(0x1F), 1, NIG_REG_INGRESS_EOP_PORT0_EMPTY,
2770 /*line 444*/{(0x1F), 1, NIG_REG_INGRESS_EOP_PORT1_EMPTY,
2776 /*line 445*/{(0x1F), 1, NIG_REG_INGRESS_EOP_LB_EMPTY,
2782 /*line 446*/{(0x1F), 1, NIG_REG_INGRESS_RMP0_DSCR_EMPTY,
2788 /*line 447*/{(0x1F), 1, NIG_REG_INGRESS_RMP1_DSCR_EMPTY,
2794 /*line 448*/{(0x1F), 1, NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY,
2800 /*line 449*/{(0x1F), 1, NIG_REG_EGRESS_MNG0_FIFO_EMPTY,
2806 /*line 450*/{(0x1F), 1, NIG_REG_EGRESS_MNG1_FIFO_EMPTY,
2812 /*line 451*/{(0x1F), 1, NIG_REG_EGRESS_DEBUG_FIFO_EMPTY,
2818 /*line 452*/{(0x1F), 1, NIG_REG_EGRESS_DELAY0_EMPTY,
2824 /*line 453*/{(0x1F), 1, NIG_REG_EGRESS_DELAY1_EMPTY,
2830 /*line 454*/{(0x1F), 1, NIG_REG_LLH0_FIFO_EMPTY,
2836 /*line 455*/{(0x1F), 1, NIG_REG_LLH1_FIFO_EMPTY,
2842 /*line 456*/{(0x1C), 1, NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY,
2848 /*line 457*/{(0x1C), 1, NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY,
2854 /*line 458*/{(0x1C), 1, NIG_REG_P0_TLLH_FIFO_EMPTY,
2860 /*line 459*/{(0x1C), 1, NIG_REG_P1_TLLH_FIFO_EMPTY,
2866 /*line 460*/{(0x1C), 1, NIG_REG_P0_HBUF_DSCR_EMPTY,
2872 /*line 461*/{(0x1C), 1, NIG_REG_P1_HBUF_DSCR_EMPTY,
2878 /*line 462*/{(0x18), 1, NIG_REG_P0_RX_MACFIFO_EMPTY,
2884 /*line 463*/{(0x18), 1, NIG_REG_P1_RX_MACFIFO_EMPTY,
2890 /*line 464*/{(0x18), 1, NIG_REG_P0_TX_MACFIFO_EMPTY,
2896 /*line 465*/{(0x18), 1, NIG_REG_P1_TX_MACFIFO_EMPTY,
2902 /*line 466*/{(0x10), 1, NIG_REG_EGRESS_DELAY2_EMPTY,
2908 /*line 467*/{(0x10), 1, NIG_REG_EGRESS_DELAY3_EMPTY,
2914 /*line 468*/{(0x10), 1, NIG_REG_EGRESS_DELAY4_EMPTY,
2920 /*line 469*/{(0x10), 1, NIG_REG_EGRESS_DELAY5_EMPTY,
3031  * for each line:
3164 			   "unknown macro in self test data base. macro %d line %d",  in bnx2x_idle_chk()