Lines Matching +full:phy +full:- +full:3 +full:p0 +full:- +full:supply
3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
29 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
67 * is de-asserted */
75 * is de-asserted */
82 * port is de-asserted */
85 interface #n is de-asserted. */
98 interface #n is de-asserted. */
151 * is de-asserted */
159 * is de-asserted */
162 /* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
167 /* [RW 1] Indicates if to use per-class guaranty mode (new mode) or per-MAC
168 * guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC
169 * mode). 1=per-class guaranty mode (new mode). */
177 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
179 if 1 - normal activity. */
181 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
183 if 1 - normal activity. */
198 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
199 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
200 Is used to determine the number of the AG context REG-pairs written back;
203 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
205 if 1 - normal activity. */
207 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
209 if 1 - normal activity. */
211 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
213 usual; if 1 - normal activity. */
215 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
216 are disregarded; all other signals are treated as usual; if 1 - normal
219 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
221 usual; if 1 - normal activity. */
223 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
224 input is disregarded; all other signals are treated as usual; if 1 -
227 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
229 counter. Must be initialized to 1 at start-up. */
239 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
241 if 1 - normal activity. */
243 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
245 counter. Must be initialized to 32 at start-up. */
247 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
251 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
255 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
257 if 1 - normal activity. */
262 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
271 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
273 credit counter. Must be initialized to 64 at start-up. */
275 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
277 credit counter. Must be initialized to 64 at start-up. */
279 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
280 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
286 highest priority is 3. It is supposed; that the Store channel priority is
287 the complement to 4 of the rest priorities - Aggregation channel; Load
291 highest priority is 3. It is supposed; that the Store channel priority is
292 the complement to 4 of the rest priorities - Aggregation channel; Load
297 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
299 REG-pairs are used in order to align to STORM context row size of 128
307 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
309 if 1 - normal activity. */
314 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
332 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
334 treated as usual; if 1 - normal activity. */
339 /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
344 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
346 treated as usual; if 1 - normal activity. */
351 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
355 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
357 treated as usual; if 1 - normal activity. */
362 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
366 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
368 treated as usual; if 1 - normal activity. */
373 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
378 mechanism. The fields are: [5:0] - message length; [12:6] - message
379 pointer; 18:13] - next pointer. */
386 messages. Max credit available - 127. Write writes the initial credit
388 initialized to maximum XX protected message size - 2 at start-up. */
398 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
422 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
449 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
466 field allows changing the priorities of the weighted-round-robin arbiter
500 or auto-mask-mode (1) */
520 /* [RW 16] The maximum value of the completion counter #3 */
558 /* [ST 32] The number of commands received in queue 3 */
585 /* [RW 3] The source that is associated with arbitration element 0. Source
586 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
587 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
589 /* [RW 3] The source that is associated with arbitration element 1. Source
590 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
591 sleeping thread with priority 1; 4- sleeping thread with priority 2.
594 /* [RW 3] The source that is associated with arbitration element 2. Source
595 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
596 sleeping thread with priority 1; 4- sleeping thread with priority 2.
600 /* [RW 3] The source that is associated with arbitration element 3. Source
601 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
602 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
607 /* [RW 3] The source that is associated with arbitration element 4. Source
608 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
609 sleeping thread with priority 1; 4- sleeping thread with priority 2.
669 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
677 /* [RW 3] The arbitration scheme of time_slot 0 */
679 /* [RW 3] The arbitration scheme of time_slot 10 */
681 /* [RW 3] The arbitration scheme of time_slot 11 */
683 /* [RW 3] The arbitration scheme of time_slot 12 */
685 /* [RW 3] The arbitration scheme of time_slot 13 */
687 /* [RW 3] The arbitration scheme of time_slot 14 */
689 /* [RW 3] The arbitration scheme of time_slot 15 */
691 /* [RW 3] The arbitration scheme of time_slot 16 */
693 /* [RW 3] The arbitration scheme of time_slot 17 */
695 /* [RW 3] The arbitration scheme of time_slot 18 */
697 /* [RW 3] The arbitration scheme of time_slot 1 */
699 /* [RW 3] The arbitration scheme of time_slot 2 */
701 /* [RW 3] The arbitration scheme of time_slot 3 */
703 /* [RW 3] The arbitration scheme of time_slot 4 */
705 /* [RW 3] The arbitration scheme of time_slot 5 */
707 /* [RW 3] The arbitration scheme of time_slot 6 */
709 /* [RW 3] The arbitration scheme of time_slot 7 */
711 /* [RW 3] The arbitration scheme of time_slot 8 */
713 /* [RW 3] The arbitration scheme of time_slot 9 */
715 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
716 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
725 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
732 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
735 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
736 CRC-16 T10 initial value is all ones. */
764 /* [RW 1] Command 3 go. */
778 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
780 as usual; if 1 - normal activity. */
782 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
784 all other signals are treated as usual; if 1 - normal activity. */
786 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
823 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
838 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch
880 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
899 /* [RW 3] Parity mask register #0 read/write */
901 /* [R 3] Parity register #0 read */
903 /* [RC 3] Parity register #0 read clear */
930 /* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
931 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
939 * command. Data valid only in addresses 0-4. all the rest are zero. */
955 /* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
956 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
957 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */
967 * done was not received. Data valid only in addresses 0-4. all the rest are
971 /* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
972 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
973 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
974 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
975 * - In backward compatible mode; for non default SB; each even line in the
977 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
979 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
980 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */
982 /* [R 3] Debug: pxp_arb_fsm */
985 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
986 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
987 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */
1000 /* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
1001 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
1002 * PF; 68-71 number of ATTN messages per PF */
1011 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
1035 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
1050 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1064 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1079 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
1092 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
1106 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
1119 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1133 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
1147 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1148 * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */
1163 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1183 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
1203 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1218 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1233 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1248 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1263 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1278 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1293 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1308 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1323 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1338 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1352 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1370 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1388 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1402 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1417 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1419 * parity; [31-10] Reserved; */
1423 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1425 * parity; [31-10] Reserved; */
1445 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1460 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1482 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1497 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1503 starts at 0x0 for the A0 tape-out and increments by one for each
1504 all-layer tape-out. */
1506 /* [R 14] otp_misc_do[100:0] spare bits collection: 13:11-
1507 * otp_misc_do[100:98]; 10:7 - otp_misc_do[87:84]; 6:3 - otp_misc_do[75:72];
1508 * 2:1 - otp_misc_do[51:50]; 0 - otp_misc_do[1]. */
1519 /* [RW 18] LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that
1521 * end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that
1523 * that the FW command that all Queues are empty is enabled. [2] - FW Early
1527 * [3] - PBF Request Mask. When 1 indicates that the PBF Request indication
1529 * [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF
1531 * PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1
1535 * Status (Rx LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that
1537 * indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the
1539 * indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM
1541 * is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When
1543 * indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1
1547 * bit masks the falling edge detect of the L1 status (L1 is on - off). [11]
1548 * - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE
1549 * LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI
1550 * REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1
1551 * indicates that the P0 EEE LPI REQ indication is disabled. When =0
1552 * indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE
1553 * LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is
1554 * disabled. When =0 indicates that the P0 EEE LPI REQ indication is
1555 * enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
1556 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
1557 * indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1
1559 * enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates
1561 * EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status
1562 * Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This
1563 * bit is applicable only in the EXIT Events Masks registers. [17] - L1
1565 * Edge Detect indication from the PCIE CORE is disabled (L1 is on - off).
1567 * the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in
1570 /* [RW 18] EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates
1572 * SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates
1574 * indicates that the FW command that all Queues are empty is enabled. [2] -
1578 * registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request
1580 * is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other
1582 * Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status
1586 * the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1
1588 * the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1
1590 * that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1
1593 * - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for
1595 * LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1
1599 * the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When
1600 * =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When
1601 * =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1
1602 * E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication
1603 * is disabled. When =0 indicates that the P0 EEE LPI REQ indication is
1604 * enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
1605 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
1606 * indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates
1607 * that the P0 EEE LPI REQ indication is disabled. When =0 indicates that
1608 * the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1
1610 * the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask.
1612 * indication is disabled (Rx EEE LPI is on - off). When =0 indicates that
1614 * LPI is on - off). This bit is applicable only in the EXIT Events Masks
1615 * registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the
1617 * (L1 is on - off). When =0 indicates that the L1 Status Falling Edge
1618 * Detect indication from the PCIE CORE is enabled (L1 is on - off). This
1653 /* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
1655 is 1 - the path_swap output is equal to bit[1] of this register; [1] -
1661 /* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
1663 is 1 - the port_swap output is equal to bit[1] of this register; [1] -
1676 Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When
1677 set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON.
1678 When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change
1682 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1687 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1690 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1694 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1701 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
1704 /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1707 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1710 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1716 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1723 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1724 [27:24] the master that caused the attention - according to the following
1725 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1729 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1730 [27:24] the master that caused the attention - according to the following
1731 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1742 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1775 /* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR
1793 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1794 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1796 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1798 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1814 /* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
1815 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
1816 * the port4mode_en output is equal to bit[1] of this register; [1] -
1821 write/read zero = the specific block is in reset; addr 0-wr- the write
1822 value will be written to the register; addr 1-set - one will be written
1824 have the value of zero will not be change) ; addr 2-clear - zero will be
1826 (bits that have the value of zero will not be change); addr 3-ignore;
1828 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1836 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1839 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1843 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1846 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1850 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1853 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1855 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1857 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1858 select VAUX supply. (This is an output pin only; it is not controlled by
1860 field is not applicable for this pin; only the VALUE fields is relevant -
1861 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
1866 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1869 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1872 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1874 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1879 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1889 /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1890 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 -
1895 /* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
1897 - the path_swap output is equal to bit[1] of this register; [1] -
1902 loaded; 0-prepare; -unprepare */
1908 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1909 /* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or
1918 This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -
1919 Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap
1923 /* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp
1924 Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;
1925 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the
1939 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1966 72:73]-vnic_num; 81:74]-sideband_info */
1970 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1977 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1991 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1992 be cleared in the attached PHY device that is driving the MINT pin. */
2009 /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
2015 b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
2037 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
2060 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
2061 9-11PHY7; 12 MAC4; 13-15 PHY10; */
2063 /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
2064 tsdm enable; b2- usdm enable */
2072 /* [RW 16] classes are high-priority for port0 */
2075 /* [RW 16] classes are low-priority for port0 */
2088 classification upon VLAN id. 2: classification upon MAC address. 3:
2109 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
2122 classification upon VLAN id. 2: classification upon MAC address. 3:
2144 /* [RW 16] Outer VLAN type identifier for multi-function mode. In non
2145 * multi-function mode; it will hold the inner VLAN type. Typically 0x8100.
2184 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2193 /* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
2199 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2203 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2209 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2210 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2211 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2212 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2213 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2218 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2219 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2220 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2221 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2222 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2223 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2224 * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
2226 * Note that rules 4-7 are for IPv6 packets only and require that the packet
2238 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2239 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2240 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2241 * priority field is extracted from the outer-most VLAN in receive packet.
2245 * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
2247 * frame format in timesync event detection on RX side. Bit 3 enables
2255 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2260 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2265 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2270 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
2271 * priority is mapped to COS 3 when the corresponding mask bit is 1. More
2275 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
2280 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
2288 * clients that are not subject to WFQ credit blocking - their
2292 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2294 * subject to WFQ credit blocking - their specifications here are not used.
2297 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2298 * use credit registers 0-5 respectively (0x543210876). Note that credit
2302 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2304 * subject to WFQ credit blocking - their specifications here are not used.
2307 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2308 * use credit registers 0-5 respectively (0x543210876). Note that credit
2314 * strict priorities for clients 0-2 -- management and debug traffic. */
2344 * two round-robin arbitration slots to avoid starvation. A value of 0 means
2345 * no strict priority cycles - the strict priority with anti-starvation
2346 * arbiter becomes a round-robin arbiter. */
2351 * clients are assigned the following IDs: 0-management; 1-debug traffic
2352 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2355 * traffic at priority 3; and COS1 traffic at priority 4. */
2357 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2362 /* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
2368 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2372 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2378 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2379 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2380 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2381 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2382 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2387 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2388 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2389 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2390 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2391 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2392 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2393 * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
2395 * Note that rules 4-7 are for IPv6 packets only and require that the packet
2402 * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2403 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2404 * client; bits [35-32] are for priority 8 client. The clients are assigned
2405 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2406 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2407 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2412 * strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2413 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2414 * client; bits [35-32] are for priority 8 client. The clients are assigned
2415 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2416 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2417 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2421 /* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
2423 * packets from MCP are forwarded to the network when this bit is cleared -
2425 * When MCP-to-host paths for both ports 0 and 1 are disabled - the arbiter
2436 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2437 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2438 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2439 * priority field is extracted from the outer-most VLAN in receive packet.
2443 * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
2445 * frame format in timesync event detection on RX side. Bit 3 enables
2453 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2458 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2463 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2472 /* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
2480 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2484 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2490 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2491 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2492 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2493 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2494 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2499 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2500 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2501 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2502 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2503 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2504 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2508 /* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
2516 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2520 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2526 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2527 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2528 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2529 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2530 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2535 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2536 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2537 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2538 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2539 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2540 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2545 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2547 * subject to WFQ credit blocking - their specifications here are not used.
2550 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2551 * use credit registers 0-5 respectively (0x543210876). Note that credit
2553 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2554 * credit registers 0-5 are valid. This register should be configured
2558 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2560 * subject to WFQ credit blocking - their specifications here are not used.
2563 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2564 * use credit registers 0-5 respectively (0x543210876). Note that credit
2566 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2567 * credit registers 0-5 are valid. This register should be configured
2572 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
2573 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2574 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
2579 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
2580 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
2581 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
2599 two round-robin arbitration slots to avoid starvation. A value of 0 means
2600 no strict priority cycles - the strict priority with anti-starvation
2601 arbiter becomes a round-robin arbiter. */
2604 strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2605 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2606 client; bits [35-32] are for priority 8 client. The clients are assigned
2607 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2608 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2609 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2612 is the same as the one for port 0, except that port 1 only has COS 0-2
2613 traffic. There is no traffic for COS 3-5 of port 1. */
2616 strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2617 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2618 client; bits [35-32] are for priority 8 client. The clients are assigned
2619 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2620 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2621 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2624 is the same as the one for port 0, except that port 1 only has COS 0-2
2625 traffic. There is no traffic for COS 3-5 of port 1. */
2629 /* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
2631 * packets from MCP are forwarded to the network when this bit is cleared -
2659 /* [RW 5] control to serdes - CL45 DEVAD */
2661 /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
2663 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
2697 * generator sub-module.
2704 /* [RW 1] control to xgxs - remote PHY in-band MDIO */
2706 /* [RW 5] control to xgxs - CL45 DEVAD */
2708 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
2710 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
2790 * lowest priority in the strict-priority arbiter. */
2792 /* [RW 3] For port 1: Bit per client to indicate if the client competes in
2795 * lowest priority in the strict-priority arbiter. */
2800 /* [RW 3] For port 0: Bit per client to indicate if the client is subject to
2805 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2810 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2814 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2819 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2824 * arbiter. If reset strict priority w/ anti-starvation will be performed
2827 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2830 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2832 /* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest
2876 /* [RW 6] Bit-map indicating which headers must appear in the packet */
2880 * strict-priority w/ anti-starvation arbiter is a RR arbiter. */
2893 /* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
2895 /* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
2897 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2902 /* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port
2905 /* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
2911 /* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */
2913 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2926 /* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */
2928 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2986 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
2999 /* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1
3000 * - enable. */
3002 /* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;
3003 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */
3005 /* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1
3006 * - enable. */
3014 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3043 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
3044 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
3045 * arrived with a correctable error. Bit 3 - Configuration RW arrived with
3046 * an uncorrectable error. Bit 4 - Completion with Configuration Request
3047 * Retry Status. Bit 5 - Expansion ROM access received with a write request.
3048 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
3049 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
3057 * details register and enables logging new error details. Bit 0 - clears
3058 * INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears
3061 * TX_ERR_RD_DETAILS TX_ERR_RD_DETAILS2 TX_ERR_WR_DETAILS_ICPL; Bit 3 -
3062 * clears VF_LENGTH_VIOLATION_DETAILS. Bit 4 - clears
3063 * VF_GRC_SPACE_VIOLATION_DETAILS. Bit 5 - clears RX_TCPL_ERR_DETAILS. Bit 6
3064 * - clears TCPL_IN_TWO_RCBS_DETAILS. */
3077 /* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
3078 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
3079 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
3080 * completer abort. 3 - Illegal value for this field. [12] valid - indicates
3085 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
3086 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
3087 * unsupported request. 2 - completer abort. 3 - Illegal value for this
3088 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
3091 /* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
3094 * work-around is needed. Note: register contains bits from both paths. */
3102 /* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
3103 * completion did not return yet. 1 - tag is unused. Same functionality as
3104 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */
3106 /* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1
3107 * - enable. */
3115 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3122 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
3123 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
3127 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
3128 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
3129 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
3130 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
3139 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
3140 * - VFID. */
3143 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
3144 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
3145 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
3146 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
3150 /* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;
3151 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any
3160 /* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1
3161 * - enable. */
3163 /* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1
3164 * - enable. */
3166 /* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1
3167 * - enable. */
3175 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3178 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
3179 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
3186 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
3187 * valid - indicates if there was a request with length violation since the
3237 /* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1
3238 * - enable. */
3246 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3291 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
3293 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
3310 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
3313 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
3317 /* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
3319 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
3325 /* [RW 6] Bit-map indicating which headers must appear in the packet */
3327 /* [RW 6] Bit-map indicating which headers must appear in the packet for
3332 /* [RW 8] The 8-bit event ID for cases where there is no match on the
3433 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
3434 its[15:0]-address */
3443 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
3444 its[15:0]-address */
3453 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
3454 its[15:0]-address */
3463 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
3464 its[15:0]-address */
3473 /* [RW 3] this field allows one function to pretend being another function
3552 /* [R 8] Debug only: The blocks counter - number of unused block ids */
3597 /* [R 7] Debug only: The SR counter - number of unused sub request ids */
3601 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
3678 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
3734 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
3735 -128k */
3746 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3747 * aligned. 4 - 512B aligned. */
3750 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3751 * aligned. 4 - 512B aligned. */
3766 /* [WB 53] Onchip address table - B0 */
3774 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
3775 -128k */
3779 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
3782 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
3789 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
3790 -128k */
3796 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
3797 -128k */
3853 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */
3867 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
3870 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
3873 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3876 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3879 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3882 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3889 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3892 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3895 /* [RW 1] 0 - working in A0 mode; - working in B0 mode */
3897 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3900 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3903 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3910 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3913 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3966 queues 63-0 */
3971 queues 127-64 */
3978 queue uses port 0 else it uses port 1; queues 31-0 */
3981 queue uses port 0 else it uses port 1; queues 95-64 */
3984 queue uses port 0 else it uses port 1; queues 63-32 */
3987 queue uses port 0 else it uses port 1; queues 127-96 */
4029 physical queue uses the byte credit; queues 31-0 */
4032 physical queue uses the byte credit; queues 95-64 */
4035 physical queue uses the byte credit; queues 63-32 */
4038 physical queue uses the byte credit; queues 127-96 */
4051 be use for the almost empty indication to the HW block; queues 95-64 */
4057 be use for the almost empty indication to the HW block; queues 127-96 */
4066 /* [R 16] Pause state for physical queues 15-0 */
4068 /* [R 16] Pause state for physical queues 31-16 */
4070 /* [R 16] Pause state for physical queues 47-32 */
4072 /* [R 16] Pause state for physical queues 63-48 */
4074 /* [R 16] Pause state for physical queues 79-64 */
4076 /* [R 16] Pause state for physical queues 95-80 */
4078 /* [R 16] Pause state for physical queues 111-96 */
4080 /* [R 16] Pause state for physical queues 127-112 */
4092 /* [RW 3] pci function number of queues 15-0 */
4101 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
4103 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
4105 /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
4107 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
4127 /* [R 24] The number of tasks queued for each queue; queues 63-0 */
4129 /* [R 24] The number of tasks queued for each queue; queues 127-64 */
4255 /* [R 6] Keep the fill level of the fifo from write client 3 */
4277 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4279 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4281 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4283 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4285 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4287 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4289 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4291 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4293 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4295 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4297 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4299 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4301 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4303 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4305 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4307 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4309 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4311 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4313 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4315 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4317 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4319 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4321 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4323 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4325 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4327 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4329 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4331 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4333 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4335 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4337 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4339 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4341 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4343 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4345 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4347 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4349 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4351 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4353 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4355 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4357 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4359 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4361 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4363 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4365 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4367 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4407 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
4428 /* [R 3] Interrupt register #0 read */
4430 /* [RW 3] Parity mask register #0 read/write */
4432 /* [R 3] Parity register #0 read */
4434 /* [RC 3] Parity register #0 read clear */
4438 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4440 usual; if 1 - normal activity. */
4442 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4443 are disregarded; all other signals are treated as usual; if 1 - normal
4446 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4448 usual; if 1 - normal activity. */
4450 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4451 input is disregarded; all other signals are treated as usual; if 1 -
4454 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4456 counter. Must be initialized to 1 at start-up. */
4458 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4462 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4464 treated as usual; if 1 - normal activity. */
4469 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4479 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4481 credit counter. Must be initialized to 64 at start-up. */
4483 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4485 credit counter. Must be initialized to 64 at start-up. */
4487 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4488 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
4493 highest priority is 3. It is supposed that the Store channel is the
4494 complement of the other 3 groups. */
4497 highest priority is 3. It is supposed that the Store channel is the
4498 complement of the other 3 groups. */
4500 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
4501 sent to STORM; for a specific connection type. The double REG-pairs are
4511 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4513 if 1 - normal activity. */
4518 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4530 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
4532 if 1 - normal activity. */
4537 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
4546 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4548 treated as usual; if 1 - normal activity. */
4550 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4554 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4556 if 1 - normal activity. */
4568 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
4569 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4570 Is used to determine the number of the AG context REG-pairs written back;
4573 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4575 if 1 - normal activity. */
4577 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4579 if 1 - normal activity. */
4581 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4583 if 1 - normal activity. */
4589 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4591 treated as usual; if 1 - normal activity. */
4593 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4597 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4599 counter. Must be initialized to 32 at start-up. */
4601 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4605 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4613 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4615 if 1 - normal activity. */
4617 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4619 if 1 - normal activity. */
4624 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4628 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
4630 treated as usual; if 1 - normal activity. */
4635 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4640 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
4641 pointer; 20:16] - next pointer. */
4648 messages. Max credit available - 127.Write writes the initial credit
4650 initialized to 19 at start-up. */
4661 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
4702 /* [WB 64] Linear0 phy address. */
4712 /* [WB 64] Linear1 phy address. */
4751 /* [RW 16] The maximum value of the completion counter #3 */
4777 /* [ST 32] The number of commands received in queue 3 */
4818 /* [RW 3] The source that is associated with arbitration element 0. Source
4819 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4820 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4822 /* [RW 3] The source that is associated with arbitration element 1. Source
4823 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4824 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4827 /* [RW 3] The source that is associated with arbitration element 2. Source
4828 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4829 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4833 /* [RW 3] The source that is associated with arbitration element 3. Source
4834 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4835 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4840 /* [RW 3] The source that is associated with arbitration element 4. Source
4841 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4842 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4887 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4898 /* [RW 3] The arbitration scheme of time_slot 0 */
4900 /* [RW 3] The arbitration scheme of time_slot 10 */
4902 /* [RW 3] The arbitration scheme of time_slot 11 */
4904 /* [RW 3] The arbitration scheme of time_slot 12 */
4906 /* [RW 3] The arbitration scheme of time_slot 13 */
4908 /* [RW 3] The arbitration scheme of time_slot 14 */
4910 /* [RW 3] The arbitration scheme of time_slot 15 */
4912 /* [RW 3] The arbitration scheme of time_slot 16 */
4914 /* [RW 3] The arbitration scheme of time_slot 17 */
4916 /* [RW 3] The arbitration scheme of time_slot 18 */
4918 /* [RW 3] The arbitration scheme of time_slot 1 */
4920 /* [RW 3] The arbitration scheme of time_slot 2 */
4922 /* [RW 3] The arbitration scheme of time_slot 3 */
4924 /* [RW 3] The arbitration scheme of time_slot 4 */
4926 /* [RW 3] The arbitration scheme of time_slot 5 */
4928 /* [RW 3] The arbitration scheme of time_slot 6 */
4930 /* [RW 3] The arbitration scheme of time_slot 7 */
4932 /* [RW 3] The arbitration scheme of time_slot 8 */
4934 /* [RW 3] The arbitration scheme of time_slot 9 */
4948 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4949 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4951 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
4958 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4960 usual; if 1 - normal activity. */
4962 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4963 are disregarded; all other signals are treated as usual; if 1 - normal
4966 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4968 usual; if 1 - normal activity. */
4970 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4971 input is disregarded; all other signals are treated as usual; if 1 -
4974 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4976 counter. Must be initialized to 1 at start-up. */
4978 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4982 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4984 treated as usual; if 1 - normal activity. */
4989 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4993 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4995 treated as usual; if 1 - normal activity. */
5000 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
5010 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
5012 credit counter. Must be initialized to 64 at start-up. */
5014 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
5016 credit counter. Must be initialized to 64 at start-up. */
5018 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
5019 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
5024 highest priority is 3. It is supposed that the Store channel group is
5028 highest priority is 3. It is supposed that the Store channel group is
5033 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
5034 sent to STORM; for a specific connection type. the double REG-pairs are
5057 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
5059 treated as usual; if 1 - normal activity. */
5061 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
5065 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
5067 credit counter. Must be initialized to 4 at start-up. */
5071 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
5073 treated as usual; if 1 - normal activity. */
5075 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
5079 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
5081 treated as usual; if 1 - normal activity. */
5086 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
5090 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
5092 if 1 - normal activity. */
5104 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
5105 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
5106 Is used to determine the number of the AG context REG-pairs written back;
5109 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
5111 if 1 - normal activity. */
5113 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
5115 if 1 - normal activity. */
5117 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
5119 treated as usual; if 1 - normal activity. */
5121 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
5123 if 1 - normal activity. */
5127 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
5129 counter. Must be initialized to 32 at start-up. */
5131 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
5135 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
5143 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
5145 if 1 - normal activity. */
5147 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
5149 if 1 - normal activity. */
5154 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
5158 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
5160 treated as usual; if 1 - normal activity. */
5165 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
5170 mechanism. The fields are:[5:0] - message length; 14:6] - message
5171 pointer; 19:15] - next pointer. */
5179 value of the credit counter. Must be initialized to 12 at start-up. */
5187 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
5203 * decrement unit is 1 micro-second. */
5211 /* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive
5215 #define UMAC_UMAC_EEE_CTRL_REG_EEE_EN (0x1<<3)
5224 or auto-mask-mode (1) */
5241 /* [RW 16] The maximum value of the completion counter #3 */
5269 /* [ST 32] The number of commands received in queue 3 */
5310 /* [RW 3] The source that is associated with arbitration element 0. Source
5311 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5312 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
5314 /* [RW 3] The source that is associated with arbitration element 1. Source
5315 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5316 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5319 /* [RW 3] The source that is associated with arbitration element 2. Source
5320 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5321 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5325 /* [RW 3] The source that is associated with arbitration element 3. Source
5326 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5327 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
5332 /* [RW 3] The source that is associated with arbitration element 4. Source
5333 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5334 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5379 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5387 /* [RW 3] The arbitration scheme of time_slot 0 */
5389 /* [RW 3] The arbitration scheme of time_slot 10 */
5391 /* [RW 3] The arbitration scheme of time_slot 11 */
5393 /* [RW 3] The arbitration scheme of time_slot 12 */
5395 /* [RW 3] The arbitration scheme of time_slot 13 */
5397 /* [RW 3] The arbitration scheme of time_slot 14 */
5399 /* [RW 3] The arbitration scheme of time_slot 15 */
5401 /* [RW 3] The arbitration scheme of time_slot 16 */
5403 /* [RW 3] The arbitration scheme of time_slot 17 */
5405 /* [RW 3] The arbitration scheme of time_slot 18 */
5407 /* [RW 3] The arbitration scheme of time_slot 1 */
5409 /* [RW 3] The arbitration scheme of time_slot 2 */
5411 /* [RW 3] The arbitration scheme of time_slot 3 */
5413 /* [RW 3] The arbitration scheme of time_slot 4 */
5415 /* [RW 3] The arbitration scheme of time_slot 5 */
5417 /* [RW 3] The arbitration scheme of time_slot 6 */
5419 /* [RW 3] The arbitration scheme of time_slot 7 */
5421 /* [RW 3] The arbitration scheme of time_slot 8 */
5423 /* [RW 3] The arbitration scheme of time_slot 9 */
5440 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5441 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
5446 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
5457 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
5459 usual; if 1 - normal activity. */
5461 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
5462 are disregarded; all other signals are treated as usual; if 1 - normal
5465 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
5467 usual; if 1 - normal activity. */
5469 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
5470 input is disregarded; all other signals are treated as usual; if 1 -
5473 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
5475 counter. Must be initialized to 1 at start-up. */
5477 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
5481 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
5483 treated as usual; if 1 - normal activity. */
5488 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
5492 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
5494 treated as usual; if 1 - normal activity. */
5499 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
5509 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
5511 credit counter. Must be initialized to 64 at start-up. */
5513 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
5515 credit counter. Must be initialized to 64 at start-up. */
5521 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
5522 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
5527 highest priority is 3. It is supposed that the Channel group is the
5528 complement of the other 3 groups. */
5531 highest priority is 3. It is supposed that the Channel group is the
5532 complement of the other 3 groups. */
5534 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
5536 treated as usual; if 1 - normal activity. */
5541 /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
5545 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
5547 treated as usual; if 1 - normal activity. */
5552 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
5553 sent to STORM; for a specific connection type. The double REG-pairs are
5563 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
5565 if 1 - normal activity. */
5570 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
5581 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
5585 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
5587 treated as usual; if 1 - normal activity. */
5589 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
5591 credit counter. Must be initialized to 4 at start-up. */
5593 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
5599 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
5601 treated as usual; if 1 - normal activity. */
5603 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
5605 treated as usual; if 1 - normal activity. */
5610 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
5616 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
5618 treated as usual; if 1 - normal activity. */
5623 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
5639 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
5641 if 1 - normal activity. */
5654 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
5655 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
5656 Is used to determine the number of the AG context REG-pairs written back;
5659 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
5661 if 1 - normal activity. */
5663 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
5665 if 1 - normal activity. */
5667 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
5669 treated as usual; if 1 - normal activity. */
5671 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
5673 if 1 - normal activity. */
5679 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
5681 counter. Must be initialized to 32 at start-up. */
5683 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
5687 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
5695 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
5697 if 1 - normal activity. */
5699 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
5701 if 1 - normal activity. */
5706 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
5711 mechanism. The fields are: [5:0] - message length; 11:6] - message
5712 pointer; 16:12] - next pointer. */
5719 messages. Max credit available - 3.Write writes the initial credit value;
5721 to 2 at start-up. */
5739 #define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3)
5764 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
5784 or auto-mask-mode (1) */
5795 /* [RW 16] The maximum value of the completion counter #3 */
5821 /* [ST 32] The number of commands received in queue 3 */
5837 /* [W 17] Generate an operation after completion; bit-16 is
5864 /* [RW 3] The source that is associated with arbitration element 0. Source
5865 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5866 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
5868 /* [RW 3] The source that is associated with arbitration element 1. Source
5869 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5870 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5873 /* [RW 3] The source that is associated with arbitration element 2. Source
5874 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5875 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5879 /* [RW 3] The source that is associated with arbitration element 3. Source
5880 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5881 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
5886 /* [RW 3] The source that is associated with arbitration element 4. Source
5887 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5888 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5933 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5941 /* [RW 3] The arbitration scheme of time_slot 0 */
5943 /* [RW 3] The arbitration scheme of time_slot 10 */
5945 /* [RW 3] The arbitration scheme of time_slot 11 */
5947 /* [RW 3] The arbitration scheme of time_slot 12 */
5949 /* [RW 3] The arbitration scheme of time_slot 13 */
5951 /* [RW 3] The arbitration scheme of time_slot 14 */
5953 /* [RW 3] The arbitration scheme of time_slot 15 */
5955 /* [RW 3] The arbitration scheme of time_slot 16 */
5957 /* [RW 3] The arbitration scheme of time_slot 17 */
5959 /* [RW 3] The arbitration scheme of time_slot 18 */
5961 /* [RW 3] The arbitration scheme of time_slot 1 */
5963 /* [RW 3] The arbitration scheme of time_slot 2 */
5965 /* [RW 3] The arbitration scheme of time_slot 3 */
5967 /* [RW 3] The arbitration scheme of time_slot 4 */
5969 /* [RW 3] The arbitration scheme of time_slot 5 */
5971 /* [RW 3] The arbitration scheme of time_slot 6 */
5973 /* [RW 3] The arbitration scheme of time_slot 7 */
5975 /* [RW 3] The arbitration scheme of time_slot 8 */
5977 /* [RW 3] The arbitration scheme of time_slot 9 */
5979 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5980 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
6003 #define MCPR_NVM_COMMAND_DONE (1L<<3)
6010 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
6011 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
6012 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
6013 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
6014 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
6015 #define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3)
6016 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
6017 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
6018 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
6019 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
6020 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
6021 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
6022 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
6023 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
6024 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
6025 #define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
6026 #define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
6027 #define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
6028 #define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
6029 #define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
6030 #define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
6031 #define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3)
6032 #define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
6033 #define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
6034 #define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
6035 #define BIGMAC2_REGISTER_RX_STAT_GRPP (0x51<<3)
6036 #define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
6037 #define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
6038 #define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
6039 #define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
6040 #define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
6041 #define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
6042 #define BIGMAC2_REGISTER_TX_STAT_GTPP (0x24<<3)
6045 #define EMAC_LED_10MB_OVERRIDE (1L<<3)
6051 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
6065 #define EMAC_MODE_PORT_MII_10M (3L<<2)
6097 #define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
6102 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
6108 #define MISC_REGISTERS_GPIO_3 3
6141 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
6160 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
6195 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
6234 #define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
6237 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
6239 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
6301 /*E1H NIG status sync attention mapped to group 4-7*/
6388 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
6448 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)
6472 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
6493 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
6524 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
6552 * Since registers from 0x000-0x7ff are split across functions, each PF will
6583 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/
6626 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \
6629 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \
6632 (1 << 15) /* Receiver Overflow Status Status in function 3, if \
6636 (1 << 14) /* Unexpected Completion Status Status in function 3, \
6640 (1 << 13) /* Receive UR Statusin function 3. If set, generate \
6643 (1 << 12) /* Completer Timeout Status Status in function 3, if \
6647 function 3, if set, generate pcie_err_attn output when this error \
6650 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \
6671 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \
6767 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \
6798 #define ME_REG_VF_ERR (0x1<<3)
6807 ((PXP_VF_ADDR_IGU_START) + (PXP_VF_ADDR_IGU_SIZE) - 1)
6813 ((PXP_VF_ADDR_USDM_QUEUES_START) + (PXP_VF_ADDR_USDM_QUEUES_SIZE) - 1)
6818 ((PXP_VF_ADDR_CSDM_GLOBAL_START) + (PXP_VF_ADDR_CSDM_GLOBAL_SIZE) - 1)
6823 ((PXP_VF_ADDR_DB_START) + (PXP_VF_ADDR_DB_SIZE) - 1)
7002 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
7286 /* When this pin is active high during reset, 10GBASE-T core is power
7287 * down, When it is active low the 10GBASE-T is power up
7347 #define PHY84833_MB_PROCESS3 3
7545 #define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3
7571 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
7576 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
7593 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
7612 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \
7630 /* String-to-compress [31:8] = CID (all 24 bits)
7631 * String-to-compress [7:4] = Region
7632 * String-to-compress [3:0] = Type
7641 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
7722 * Calculates crc 8 on a word value: polynomial 0-1-2-8
7756 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^ in calc_crc8()
7757 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^ in calc_crc8()
7760 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^ in calc_crc8()
7761 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7]; in calc_crc8()
7763 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^ in calc_crc8()
7764 C[3] ^ C[4] ^ C[7]; in calc_crc8()
7769 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ in calc_crc8()