Lines Matching +full:0 +full:x20020000
126 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
147 BCM57710 = 0,
286 { 0 }
412 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
414 "comp_addr [%x:%08x], comp_val 0x%08x\n", in bnx2x_dp_dmae()
420 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
422 "comp_addr [%x:%08x], comp_val 0x%08x\n", in bnx2x_dp_dmae()
430 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
432 "comp_addr [%x:%08x], comp_val 0x%08x\n", in bnx2x_dp_dmae()
438 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
440 "comp_addr [%x:%08x], comp_val 0x%08x\n", in bnx2x_dp_dmae()
448 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
450 "comp_addr [%x:%08x] comp_val 0x%08x\n", in bnx2x_dp_dmae()
455 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
457 "comp_addr [%x:%08x] comp_val 0x%08x\n", in bnx2x_dp_dmae()
464 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) in bnx2x_dp_dmae()
465 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n", in bnx2x_dp_dmae()
476 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { in bnx2x_post_dmae()
496 u32 opcode = 0; in bnx2x_dmae_opcode()
522 memset(dmae, 0, sizeof(struct dmae_command)); in bnx2x_prep_dmae_with_comp()
539 int rc = 0; in bnx2x_issue_dmae_with_comp()
551 *comp = 0; in bnx2x_issue_dmae_with_comp()
589 u32 *data = bnx2x_sp(bp, wb_data[0]); in bnx2x_write_dmae()
605 dmae.dst_addr_hi = 0; in bnx2x_write_dmae()
624 u32 *data = bnx2x_sp(bp, wb_data[0]); in bnx2x_read_dmae()
628 for (i = 0; i < len32; i++) in bnx2x_read_dmae()
631 for (i = 0; i < len32; i++) in bnx2x_read_dmae()
642 dmae.src_addr_hi = 0; in bnx2x_read_dmae()
661 int offset = 0; in bnx2x_write_dmae_phys_len()
707 int i, j, rc = 0; in bnx2x_mc_assert()
733 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n", in bnx2x_mc_assert()
737 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { in bnx2x_mc_assert()
739 for (j = 0; j < REGS_IN_ENTRY; j++) in bnx2x_mc_assert()
747 if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) { in bnx2x_mc_assert()
748 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", in bnx2x_mc_assert()
750 regs[2], regs[1], regs[0]); in bnx2x_mc_assert()
767 #define MCPR_TRACE_BUFFER_SIZE (0x800)
769 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
783 (bp->common.bc_ver & 0xff0000) >> 16, in bnx2x_fw_dump_lvl()
784 (bp->common.bc_ver & 0xff00) >> 8, in bnx2x_fw_dump_lvl()
785 (bp->common.bc_ver & 0xff)); in bnx2x_fw_dump_lvl()
794 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); in bnx2x_fw_dump_lvl()
796 if (BP_PATH(bp) == 0) in bnx2x_fw_dump_lvl()
822 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000; in bnx2x_fw_dump_lvl()
827 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); in bnx2x_fw_dump_lvl()
832 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) { in bnx2x_fw_dump_lvl()
833 for (word = 0; word < 8; word++) in bnx2x_fw_dump_lvl()
835 data[8] = 0x0; in bnx2x_fw_dump_lvl()
840 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { in bnx2x_fw_dump_lvl()
841 for (word = 0; word < 8; word++) in bnx2x_fw_dump_lvl()
843 data[8] = 0x0; in bnx2x_fw_dump_lvl()
869 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); in bnx2x_hc_int_disable()
881 "write %x to HC %d (addr 0x%x)\n", in bnx2x_hc_int_disable()
919 u16 start = 0, end = 0; in bnx2x_panic_dump()
937 …BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0… in bnx2x_panic_dump()
940 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", in bnx2x_panic_dump()
946 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) in bnx2x_panic_dump()
947 pr_cont("0x%x%s", in bnx2x_panic_dump()
954 for (i = 0; i < data_size; i++) in bnx2x_panic_dump()
959 …pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x… in bnx2x_panic_dump()
993 …BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_c… in bnx2x_panic_dump()
997 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", in bnx2x_panic_dump()
1012 …BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_con… in bnx2x_panic_dump()
1028 for (j = 0; j < HC_SB_MAX_SM; j++) in bnx2x_panic_dump()
1029 pr_cont("0x%x%s", in bnx2x_panic_dump()
1034 for (j = 0; j < loop; j++) in bnx2x_panic_dump()
1035 pr_cont("0x%x%s", in bnx2x_panic_dump()
1052 for (j = 0; j < data_size; j++) in bnx2x_panic_dump()
1058 …pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\… in bnx2x_panic_dump()
1066 …pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\… in bnx2x_panic_dump()
1076 for (j = 0; j < HC_SB_MAX_SM; j++) { in bnx2x_panic_dump()
1077 …pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_valu… in bnx2x_panic_dump()
1086 for (j = 0; j < loop; j++) { in bnx2x_panic_dump()
1087 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, in bnx2x_panic_dump()
1097 for (i = 0; i < NUM_EQ_DESC; i++) { in bnx2x_panic_dump()
1104 data[0], data[1], data[2]); in bnx2x_panic_dump()
1126 i, j, rx_bd[1], rx_bd[0], sw_bd->data); in bnx2x_panic_dump()
1136 i, j, rx_sge[1], rx_sge[0], sw_page->page); in bnx2x_panic_dump()
1145 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); in bnx2x_panic_dump()
1182 i, cos, j, tx_bd[0], tx_bd[1], in bnx2x_panic_dump()
1309 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); in bnx2x_flr_clnup_poll_hw_counter()
1310 if (val != 0) { in bnx2x_flr_clnup_poll_hw_counter()
1314 return 0; in bnx2x_flr_clnup_poll_hw_counter()
1333 {0, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1354 {0, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1386 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) in bnx2x_tx_hw_flushed()
1390 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) in bnx2x_tx_hw_flushed()
1405 u32 op_gen_command = 0; in bnx2x_send_final_clnup()
1410 BNX2X_ERR("Cleanup complete was not 0 before sending\n"); in bnx2x_send_final_clnup()
1430 REG_WR(bp, comp_addr, 0); in bnx2x_send_final_clnup()
1432 return 0; in bnx2x_send_final_clnup()
1487 return 0; in bnx2x_poll_hw_usage_counters()
1495 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); in bnx2x_hw_enable_status()
1498 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); in bnx2x_hw_enable_status()
1501 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); in bnx2x_hw_enable_status()
1504 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); in bnx2x_hw_enable_status()
1507 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); in bnx2x_hw_enable_status()
1510 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); in bnx2x_hw_enable_status()
1513 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); in bnx2x_hw_enable_status()
1516 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", in bnx2x_hw_enable_status()
1561 return 0; in bnx2x_pf_flr_clnup()
1593 "write %x to HC %d (addr 0x%x)\n", val, port, addr); in bnx2x_hc_int_enable()
1602 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); in bnx2x_hc_int_enable()
1605 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, in bnx2x_hc_int_enable()
1617 val = (0xee0f | (1 << (BP_VN(bp) + 4))); in bnx2x_hc_int_enable()
1620 val |= 0x1100; in bnx2x_hc_int_enable()
1622 val = 0xffff; in bnx2x_hc_int_enable()
1666 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", in bnx2x_igu_int_enable()
1678 val = (0xee0f | (1 << (BP_VN(bp) + 4))); in bnx2x_igu_int_enable()
1681 val |= 0x1100; in bnx2x_igu_int_enable()
1683 val = 0xffff; in bnx2x_igu_int_enable()
1699 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; in bnx2x_int_disable_sync()
1708 synchronize_irq(bp->msix_table[0].vector); in bnx2x_int_disable_sync()
1743 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", in bnx2x_trylock_hw_lock()
1811 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); in bnx2x_schedule_sp_task()
1931 if (unlikely(status == 0)) { in bnx2x_interrupt()
1935 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); in bnx2x_interrupt()
1945 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); in bnx2x_interrupt()
1957 mask = 0x2; in bnx2x_interrupt()
1958 if (status & (mask | 0x1)) { in bnx2x_interrupt()
1972 if (unlikely(status & 0x1)) { in bnx2x_interrupt()
1979 status &= ~0x1; in bnx2x_interrupt()
1985 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", in bnx2x_interrupt()
2007 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", in bnx2x_acquire_hw_lock()
2022 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", in bnx2x_acquire_hw_lock()
2028 for (cnt = 0; cnt < 1000; cnt++) { in bnx2x_acquire_hw_lock()
2033 return 0; in bnx2x_acquire_hw_lock()
2055 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", in bnx2x_release_hw_lock()
2070 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n", in bnx2x_release_hw_lock()
2076 return 0; in bnx2x_release_hw_lock()
2085 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); in bnx2x_get_gpio()
2102 value = 0; in bnx2x_get_gpio()
2113 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); in bnx2x_set_gpio()
2160 return 0; in bnx2x_set_gpio()
2165 u32 gpio_reg = 0; in bnx2x_set_mult_gpio()
2166 int rc = 0; in bnx2x_set_mult_gpio()
2179 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); in bnx2x_set_mult_gpio()
2185 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); in bnx2x_set_mult_gpio()
2191 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); in bnx2x_set_mult_gpio()
2202 if (rc == 0) in bnx2x_set_mult_gpio()
2216 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); in bnx2x_set_gpio_int()
2255 return 0; in bnx2x_set_gpio_int()
2264 BNX2X_ERR("Invalid SPIO 0x%x\n", spio); in bnx2x_set_spio()
2274 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); in bnx2x_set_spio()
2281 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); in bnx2x_set_spio()
2288 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); in bnx2x_set_spio()
2300 return 0; in bnx2x_set_spio()
2339 u32 pause_enabled = 0; in bnx2x_init_dropless_fc()
2399 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); in bnx2x_initial_phy_init()
2440 u8 rc = 0; in bnx2x_link_test()
2458 0 - if all the min_rates are 0.
2475 vn_min_rate = 0; in bnx2x_calc_vn_min()
2480 all_zero = 0; in bnx2x_calc_vn_min()
2507 vn_max_rate = 0; in bnx2x_calc_vn_max()
2573 memset(&input, 0, sizeof(struct cmng_init_input)); in bnx2x_cmng_fns_init()
2584 /* vn_weight_sum and enable fairness if not 0 */ in bnx2x_cmng_fns_init()
2666 memset(&(pstats->mac_stx[0]), 0, in bnx2x_link_attn()
2699 bp->port.supported[0] |= (SUPPORTED_10baseT_Half | in bnx2x__link_status_update()
2711 bp->port.advertising[0] = bp->port.supported[0]; in bnx2x__link_status_update()
2715 bp->link_params.req_duplex[0] = DUPLEX_FULL; in bnx2x__link_status_update()
2716 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; in bnx2x__link_status_update()
2717 bp->link_params.req_line_speed[0] = SPEED_10000; in bnx2x__link_status_update()
2718 bp->link_params.speed_cap_mask[0] = 0x7f0000; in bnx2x__link_status_update()
2760 if (bnx2x_func_state_change(bp, &func_params) < 0) in bnx2x_afex_func_update()
2761 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); in bnx2x_afex_func_update()
2763 return 0; in bnx2x_afex_func_update()
2777 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", in bnx2x_afex_handle_vif_list_cmd()
2787 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; in bnx2x_afex_handle_vif_list_cmd()
2788 update_params->func_to_clear = 0; in bnx2x_afex_handle_vif_list_cmd()
2798 if (rc < 0) in bnx2x_afex_handle_vif_list_cmd()
2799 bnx2x_fw_command(bp, drv_msg_code, 0); in bnx2x_afex_handle_vif_list_cmd()
2801 return 0; in bnx2x_afex_handle_vif_list_cmd()
2819 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); in bnx2x_handle_afex_cmd()
2820 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); in bnx2x_handle_afex_cmd()
2827 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", in bnx2x_handle_afex_cmd()
2840 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", in bnx2x_handle_afex_cmd()
2846 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) in bnx2x_handle_afex_cmd()
2851 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); in bnx2x_handle_afex_cmd()
2858 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", in bnx2x_handle_afex_cmd()
2917 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); in bnx2x_handle_afex_cmd()
2930 memset(&func_params, 0, sizeof(struct bnx2x_func_state_params)); in bnx2x_handle_update_svid_cmd()
2962 if (bnx2x_func_state_change(bp, &func_params) < 0) { in bnx2x_handle_update_svid_cmd()
2974 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0); in bnx2x_handle_update_svid_cmd()
2977 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0); in bnx2x_handle_update_svid_cmd()
2995 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); in bnx2x_pmf_update()
3000 val = (0xff0f | (1 << (BP_VN(bp) + 4))); in bnx2x_pmf_update()
3025 u32 rc = 0; in bnx2x_fw_command()
3034 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", in bnx2x_fw_command()
3056 rc = 0; in bnx2x_fw_command()
3078 struct tstorm_eth_function_common_config tcfg = {0}; in bnx2x_func_init()
3108 unsigned long flags = 0; in bnx2x_get_common_flags()
3139 unsigned long flags = 0; in bnx2x_get_q_flags()
3195 u8 max_sge = 0; in bnx2x_pf_rx_q_prep()
3196 u16 sge_sz = 0; in bnx2x_pf_rx_q_prep()
3197 u16 tpa_agg_size = 0; in bnx2x_pf_rx_q_prep()
3213 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff); in bnx2x_pf_rx_q_prep()
3292 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); in bnx2x_pf_tx_q_prep()
3302 struct bnx2x_func_init_params func_init = {0}; in bnx2x_pf_init()
3303 struct event_ring_data eq_data = { {0} }; in bnx2x_pf_init()
3311 BP_FUNC(bp) : BP_VN(bp))*4, 0); in bnx2x_pf_init()
3317 BP_FUNC(bp) : BP_VN(bp))*4, 0); in bnx2x_pf_init()
3328 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); in bnx2x_pf_init()
3358 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bnx2x_e1h_disable()
3398 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++) in bnx2x_drv_info_ether_stat()
3399 memset(ether_stat->mac_local + i, 0, in bnx2x_drv_info_ether_stat()
3400 sizeof(ether_stat->mac_local[0])); in bnx2x_drv_info_ether_stat()
3401 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj, in bnx2x_drv_info_ether_stat()
3412 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; in bnx2x_drv_info_ether_stat()
3418 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0; in bnx2x_drv_info_ether_stat()
3570 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); in bnx2x_set_mf_bw()
3576 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); in bnx2x_handle_eee_event()
3591 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); in bnx2x_handle_drv_info_req()
3601 memset(&bp->slowpath->drv_info_to_mcp, 0, in bnx2x_handle_drv_info_req()
3616 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); in bnx2x_handle_drv_info_req()
3628 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); in bnx2x_handle_drv_info_req()
3639 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) { in bnx2x_handle_drv_info_req()
3665 int i = 0; in bnx2x_update_mng_version_utility()
3669 &vals[0], &vals[1], &vals[2], &vals[3]); in bnx2x_update_mng_version_utility()
3670 if (i > 0) in bnx2x_update_mng_version_utility()
3671 vals[0] -= '0'; in bnx2x_update_mng_version_utility()
3674 &vals[0], &vals[1], &vals[2], &vals[3]); in bnx2x_update_mng_version_utility()
3678 vals[i++] = 0; in bnx2x_update_mng_version_utility()
3680 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3]; in bnx2x_update_mng_version_utility()
3708 memset(&bp->slowpath->drv_info_to_mcp, 0, in bnx2x_update_mng_version()
3714 memset(&bp->slowpath->drv_info_to_mcp, 0, in bnx2x_update_mng_version()
3776 DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event); in bnx2x_oem_event()
3808 bnx2x_fw_command(bp, cmd_fail, 0); in bnx2x_oem_event()
3810 bnx2x_fw_command(bp, cmd_ok, 0); in bnx2x_oem_event()
3820 bp->spq_prod_idx = 0; in bnx2x_sp_get_next()
3945 …"SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x… in bnx2x_sp_post()
3954 return 0; in bnx2x_sp_post()
3961 int rc = 0; in bnx2x_acquire_alr()
3964 for (j = 0; j < 1000; j++) { in bnx2x_acquire_alr()
3983 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); in bnx2x_release_alr()
3986 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3987 #define BNX2X_DEF_SB_IDX 0x0002
3992 u16 rc = 0; in bnx2x_update_dsb_idx()
4022 u32 nig_mask = 0; in bnx2x_attn_int_asserted()
4033 aeu_mask &= ~(asserted & 0x3ff); in bnx2x_attn_int_asserted()
4055 REG_WR(bp, nig_int_mask_addr, 0); in bnx2x_attn_int_asserted()
4074 if (port == 0) { in bnx2x_attn_int_asserted()
4077 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); in bnx2x_attn_int_asserted()
4081 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); in bnx2x_attn_int_asserted()
4085 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); in bnx2x_attn_int_asserted()
4090 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); in bnx2x_attn_int_asserted()
4094 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); in bnx2x_attn_int_asserted()
4098 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); in bnx2x_attn_int_asserted()
4110 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, in bnx2x_attn_int_asserted()
4120 u32 cnt = 0, igu_acked; in bnx2x_attn_int_asserted()
4124 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && in bnx2x_attn_int_asserted()
4158 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0); in bnx2x_fan_failure()
4195 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", in bnx2x_attn_int_deasserted0()
4208 BNX2X_ERR("DB hw attention 0x%x\n", val); in bnx2x_attn_int_deasserted1()
4210 if (val & 0x2) in bnx2x_attn_int_deasserted1()
4226 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", in bnx2x_attn_int_deasserted1()
4239 BNX2X_ERR("CFC hw attention 0x%x\n", val); in bnx2x_attn_int_deasserted2()
4241 if (val & 0x2) in bnx2x_attn_int_deasserted2()
4247 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); in bnx2x_attn_int_deasserted2()
4249 if (val & 0x18000) in bnx2x_attn_int_deasserted2()
4254 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); in bnx2x_attn_int_deasserted2()
4270 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", in bnx2x_attn_int_deasserted2()
4285 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_attn_int_deasserted3()
4308 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) in bnx2x_attn_int_deasserted3()
4313 bp->dcbx_enabled > 0) in bnx2x_attn_int_deasserted3()
4325 BNX2X_SP_RTNL_UPDATE_SVID, 0); in bnx2x_attn_int_deasserted3()
4346 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); in bnx2x_attn_int_deasserted3()
4347 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); in bnx2x_attn_int_deasserted3()
4348 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); in bnx2x_attn_int_deasserted3()
4349 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); in bnx2x_attn_int_deasserted3()
4355 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); in bnx2x_attn_int_deasserted3()
4359 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); in bnx2x_attn_int_deasserted3()
4363 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); in bnx2x_attn_int_deasserted3()
4365 val = CHIP_IS_E1(bp) ? 0 : in bnx2x_attn_int_deasserted3()
4367 BNX2X_ERR("GRC time-out 0x%08x\n", val); in bnx2x_attn_int_deasserted3()
4370 val = CHIP_IS_E1(bp) ? 0 : in bnx2x_attn_int_deasserted3()
4372 BNX2X_ERR("GRC reserved 0x%08x\n", val); in bnx2x_attn_int_deasserted3()
4374 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); in bnx2x_attn_int_deasserted3()
4380 * 0-7 - Engine0 load counter.
4394 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4395 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4396 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4398 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4399 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4400 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4439 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); in bnx2x_reset_is_global()
4512 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); in bnx2x_set_pf_load()
4549 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); in bnx2x_clear_pf_load()
4565 return val1 != 0; in bnx2x_clear_pf_load()
4581 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); in bnx2x_get_load_status()
4585 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", in bnx2x_get_load_status()
4588 return val != 0; in bnx2x_get_load_status()
4593 pr_cont(" [0x%08x] ", REG_RD(bp, reg)); in _print_parity()
4610 for (i = 0; sig; i++) { in bnx2x_check_blocks_with_parity0()
4611 cur_bit = (0x1UL << i); in bnx2x_check_blocks_with_parity0()
4675 for (i = 0; sig; i++) { in bnx2x_check_blocks_with_parity1()
4676 cur_bit = (0x1UL << i); in bnx2x_check_blocks_with_parity1()
4818 for (i = 0; sig; i++) { in bnx2x_check_blocks_with_parity2()
4819 cur_bit = (0x1UL << i); in bnx2x_check_blocks_with_parity2()
4891 for (i = 0; sig; i++) { in bnx2x_check_blocks_with_parity3()
4892 cur_bit = (0x1UL << i); in bnx2x_check_blocks_with_parity3()
4941 for (i = 0; sig; i++) { in bnx2x_check_blocks_with_parity4()
4942 cur_bit = (0x1UL << i); in bnx2x_check_blocks_with_parity4()
4973 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || in bnx2x_parity_attn()
4978 int par_num = 0; in bnx2x_parity_attn()
4981 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", in bnx2x_parity_attn()
4982 sig[0] & HW_PRTY_ASSERT_SET_0, in bnx2x_parity_attn()
4988 if (((sig[0] & HW_PRTY_ASSERT_SET_0) || in bnx2x_parity_attn()
5000 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print); in bnx2x_parity_attn()
5026 struct attn_route attn = { {0} }; in bnx2x_chk_parity_attn()
5029 attn.sig[0] = REG_RD(bp, in bnx2x_chk_parity_attn()
5064 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); in bnx2x_attn_int_deasserted4()
5088 BNX2X_ERR("ATC hw attention 0x%x\n", val); in bnx2x_attn_int_deasserted4()
5105 BNX2X_ERR("FATAL parity attention set4 0x%x\n", in bnx2x_attn_int_deasserted4()
5128 schedule_delayed_work(&bp->sp_rtnl_task, 0); in bnx2x_attn_int_deasserted()
5141 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); in bnx2x_attn_int_deasserted()
5149 attn.sig[4] = 0; in bnx2x_attn_int_deasserted()
5152 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); in bnx2x_attn_int_deasserted()
5154 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { in bnx2x_attn_int_deasserted()
5160 group_mask->sig[0], group_mask->sig[1], in bnx2x_attn_int_deasserted()
5173 attn.sig[0] & group_mask->sig[0]); in bnx2x_attn_int_deasserted()
5186 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, in bnx2x_attn_int_deasserted()
5201 aeu_mask |= (deasserted & 0x3ff); in bnx2x_attn_int_deasserted()
5274 return 0; in bnx2x_cnic_handle_cfc_del()
5282 memset(&rparam, 0, sizeof(rparam)); in bnx2x_handle_mcast_eqe()
5294 if (rc < 0) in bnx2x_handle_mcast_eqe()
5305 unsigned long ramrod_flags = 0; in bnx2x_handle_classification_eqe()
5306 int rc = 0; in bnx2x_handle_classification_eqe()
5335 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo); in bnx2x_handle_classification_eqe()
5341 if (rc < 0) in bnx2x_handle_classification_eqe()
5343 else if (rc > 0) in bnx2x_handle_classification_eqe()
5373 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", in bnx2x_after_afex_vif_lists()
5380 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); in bnx2x_after_afex_vif_lists()
5403 /* in access mode mark mask and value are 0 to strip all vlans */ in bnx2x_after_function_update()
5405 q_update_params->silent_removal_value = 0; in bnx2x_after_function_update()
5406 q_update_params->silent_removal_mask = 0; in bnx2x_after_function_update()
5420 if (rc < 0) in bnx2x_after_function_update()
5439 if (rc < 0) in bnx2x_after_function_update()
5445 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); in bnx2x_after_function_update()
5467 int rc, spqe_cnt = 0; in bnx2x_eq_int()
5474 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. in bnx2x_eq_int()
5581 bnx2x_schedule_sp_rtnl(bp, cmd, 0); in bnx2x_eq_int()
5663 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", in bnx2x_eq_int()
5696 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n"); in bnx2x_sp_task()
5697 atomic_set(&bp->interrupt_occurred, 0); in bnx2x_sp_task()
5730 "got an unknown interrupt! (status 0x%x)\n", status); in bnx2x_sp_task()
5741 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); in bnx2x_sp_task()
5750 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, in bnx2x_msix_sp_int()
5751 IGU_INT_DISABLE, 0); in bnx2x_msix_sp_int()
5810 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n", in bnx2x_timer()
5836 for (i = 0; i < len; i += 4) in bnx2x_fill()
5839 for (i = 0; i < len; i++) in bnx2x_fill()
5850 for (index = 0; index < data_size; index++) in bnx2x_wr_fp_sb_data()
5860 u32 data_size = 0; in bnx2x_zero_fp_sb()
5866 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); in bnx2x_zero_fp_sb()
5872 memset(&sb_data_e1x, 0, in bnx2x_zero_fp_sb()
5882 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, in bnx2x_zero_fp_sb()
5885 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, in bnx2x_zero_fp_sb()
5895 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) in bnx2x_wr_sp_sb_data()
5906 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); in bnx2x_zero_sp_sb()
5914 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, in bnx2x_zero_sp_sb()
5917 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, in bnx2x_zero_sp_sb()
5926 hc_sm->timer_value = 0xFF; in bnx2x_setup_ndsb_state_machine()
5927 hc_sm->time_to_expire = 0xFFFFFFFF; in bnx2x_setup_ndsb_state_machine()
5978 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); in bnx2x_init_sb()
5992 memset(&sb_data_e1x, 0, in bnx2x_init_sb()
5996 sb_data_e1x.common.p_func.vf_id = 0xff; in bnx2x_init_sb()
6047 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); in bnx2x_init_def_sb()
6062 bp->attn_state = 0; in bnx2x_init_def_sb()
6068 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { in bnx2x_init_def_sb()
6070 /* take care of sig[0]..sig[4] */ in bnx2x_init_def_sb()
6071 for (sindex = 0; sindex < 4; sindex++) in bnx2x_init_def_sb()
6073 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); in bnx2x_init_def_sb()
6082 reg_offset_en5 + 0x4*index); in bnx2x_init_def_sb()
6084 bp->attn_group[index].sig[4] = 0; in bnx2x_init_def_sb()
6111 sp_sb_data.p_func.vf_id = 0xff; in bnx2x_init_def_sb()
6115 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); in bnx2x_init_def_sb()
6132 bp->spq_prod_idx = 0; in bnx2x_init_sp_ring()
6152 bp->eq_cons = 0; in bnx2x_init_eq_ring()
6170 memset(&ramrod_param, 0, sizeof(ramrod_param)); in bnx2x_set_q_rx_mode()
6173 ramrod_param.cid = 0; in bnx2x_set_q_rx_mode()
6193 if (rc < 0) { in bnx2x_set_q_rx_mode()
6198 return 0; in bnx2x_set_q_rx_mode()
6206 *rx_accept_flags = 0; in bnx2x_fill_accept_flags()
6207 *tx_accept_flags = 0; in bnx2x_fill_accept_flags()
6276 return 0; in bnx2x_fill_accept_flags()
6282 unsigned long rx_mode_flags = 0, ramrod_flags = 0; in bnx2x_set_storm_rx_mode()
6283 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; in bnx2x_set_storm_rx_mode()
6309 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) in bnx2x_init_internal_common()
6311 USTORM_AGG_DATA_OFFSET + i * 4, 0); in bnx2x_init_internal_common()
6337 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); in bnx2x_init_internal()
6364 unsigned long q_type = 0; in bnx2x_init_eth_fp()
6365 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; in bnx2x_init_eth_fp()
6433 *txdata->tx_cons_sb = cpu_to_le16(0); in bnx2x_init_tx_ring_one()
6436 txdata->tx_db.data.zero_fill1 = 0; in bnx2x_init_tx_ring_one()
6437 txdata->tx_db.data.prod = 0; in bnx2x_init_tx_ring_one()
6439 txdata->tx_pkt_prod = 0; in bnx2x_init_tx_ring_one()
6440 txdata->tx_pkt_cons = 0; in bnx2x_init_tx_ring_one()
6441 txdata->tx_bd_prod = 0; in bnx2x_init_tx_ring_one()
6442 txdata->tx_bd_cons = 0; in bnx2x_init_tx_ring_one()
6443 txdata->tx_pkt = 0; in bnx2x_init_tx_ring_one()
6451 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); in bnx2x_init_tx_rings_cnic()
6467 unsigned long q_type = 0; in bnx2x_init_fcoe_fp()
6476 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), in bnx2x_init_fcoe_fp()
6585 return 0; in bnx2x_gunzip_init()
6621 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { in bnx2x_gunzip()
6628 #define FNAME 0x8 in bnx2x_gunzip()
6631 while ((zbuf[n++] != 0) && (n < len)); in bnx2x_gunzip()
6648 if (bp->gunzip_outlen & 0x3) in bnx2x_gunzip()
6657 return 0; in bnx2x_gunzip()
6674 wb_write[0] = 0x55555555; in bnx2x_lb_pckt()
6675 wb_write[1] = 0x55555555; in bnx2x_lb_pckt()
6676 wb_write[2] = 0x20; /* SOP */ in bnx2x_lb_pckt()
6680 wb_write[0] = 0x09000000; in bnx2x_lb_pckt()
6681 wb_write[1] = 0x55555555; in bnx2x_lb_pckt()
6682 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ in bnx2x_lb_pckt()
6694 u32 val = 0; in bnx2x_int_mem_test()
6704 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); in bnx2x_int_mem_test()
6705 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); in bnx2x_int_mem_test()
6706 REG_WR(bp, CFC_REG_DEBUG0, 0x1); in bnx2x_int_mem_test()
6707 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); in bnx2x_int_mem_test()
6709 /* Write 0 to parser credits for CFC search request */ in bnx2x_int_mem_test()
6710 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bnx2x_int_mem_test()
6716 /* Wait until NIG register shows 1 packet of size 0x10 */ in bnx2x_int_mem_test()
6721 val = *bnx2x_sp(bp, wb_data[0]); in bnx2x_int_mem_test()
6722 if (val == 0x10) in bnx2x_int_mem_test()
6728 if (val != 0x10) { in bnx2x_int_mem_test()
6729 BNX2X_ERR("NIG timeout val = 0x%x\n", val); in bnx2x_int_mem_test()
6743 if (val != 0x1) { in bnx2x_int_mem_test()
6744 BNX2X_ERR("PRS timeout val = 0x%x\n", val); in bnx2x_int_mem_test()
6749 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bnx2x_int_mem_test()
6751 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bnx2x_int_mem_test()
6759 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); in bnx2x_int_mem_test()
6760 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); in bnx2x_int_mem_test()
6761 REG_WR(bp, CFC_REG_DEBUG0, 0x1); in bnx2x_int_mem_test()
6762 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); in bnx2x_int_mem_test()
6764 /* Write 0 to parser credits for CFC search request */ in bnx2x_int_mem_test()
6765 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bnx2x_int_mem_test()
6768 for (i = 0; i < 10; i++) in bnx2x_int_mem_test()
6772 packets of size 11*0x10 = 0xb0 */ in bnx2x_int_mem_test()
6777 val = *bnx2x_sp(bp, wb_data[0]); in bnx2x_int_mem_test()
6778 if (val == 0xb0) in bnx2x_int_mem_test()
6784 if (val != 0xb0) { in bnx2x_int_mem_test()
6785 BNX2X_ERR("NIG timeout val = 0x%x\n", val); in bnx2x_int_mem_test()
6792 BNX2X_ERR("PRS timeout val = 0x%x\n", val); in bnx2x_int_mem_test()
6795 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); in bnx2x_int_mem_test()
6799 /* Wait until NIG register shows 1 packet of size 0x10 */ in bnx2x_int_mem_test()
6802 BNX2X_ERR("PRS timeout val = 0x%x\n", val); in bnx2x_int_mem_test()
6805 for (i = 0; i < 11; i++) in bnx2x_int_mem_test()
6814 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bnx2x_int_mem_test()
6816 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bnx2x_int_mem_test()
6825 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); in bnx2x_int_mem_test()
6826 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); in bnx2x_int_mem_test()
6827 REG_WR(bp, CFC_REG_DEBUG0, 0x0); in bnx2x_int_mem_test()
6828 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); in bnx2x_int_mem_test()
6832 return 0; /* OK */ in bnx2x_int_mem_test()
6839 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6841 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); in bnx2x_enable_blocks_attention()
6843 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6844 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6845 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6852 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); in bnx2x_enable_blocks_attention()
6853 REG_WR(bp, QM_REG_QM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6854 REG_WR(bp, TM_REG_TM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6855 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6856 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6857 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6858 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ in bnx2x_enable_blocks_attention()
6859 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ in bnx2x_enable_blocks_attention()
6860 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6861 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6862 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6863 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ in bnx2x_enable_blocks_attention()
6864 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ in bnx2x_enable_blocks_attention()
6865 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6866 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6867 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6868 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6869 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ in bnx2x_enable_blocks_attention()
6870 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ in bnx2x_enable_blocks_attention()
6880 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6881 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6882 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6883 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ in bnx2x_enable_blocks_attention()
6887 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); in bnx2x_enable_blocks_attention()
6889 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6890 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6891 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ in bnx2x_enable_blocks_attention()
6892 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ in bnx2x_enable_blocks_attention()
6897 u32 val = 0x1400; in bnx2x_reset_common()
6901 0xd3ffff7f); in bnx2x_reset_common()
6913 bp->dmae_ready = 0; in bnx2x_setup_dmae()
6923 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); in bnx2x_init_pxp()
6944 is_required = 0; in bnx2x_setup_fan_failure_detection()
6968 if (is_required == 0) in bnx2x_setup_fan_failure_detection()
6991 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); in bnx2x_pf_disable()
6992 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); in bnx2x_pf_disable()
7002 shmem_base[0] = bp->common.shmem_base; in bnx2x__common_init_phy()
7003 shmem2_base[0] = bp->common.shmem2_base; in bnx2x__common_init_phy()
7024 /* make sure this value is 0 */ in bnx2x_config_endianity()
7025 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); in bnx2x_config_endianity()
7038 bnx2x_config_endianity(bp, 0); in bnx2x_set_endianity()
7044 bnx2x_config_endianity(bp, 0); in bnx2x_reset_endianity()
7065 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); in bnx2x_init_hw_common()
7067 val = 0xfffc; in bnx2x_init_hw_common()
7085 * for all functions on the given path, this means 0,2,4,6 for in bnx2x_init_hw_common()
7086 * path 0 and 1,3,5,7 for path 1 in bnx2x_init_hw_common()
7108 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); in bnx2x_init_hw_common()
7117 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); in bnx2x_init_hw_common()
7134 * have entries with value "0" and valid bit on. in bnx2x_init_hw_common()
7151 * it will write "0" to the following registers of in bnx2x_init_hw_common()
7153 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); in bnx2x_init_hw_common()
7154 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); in bnx2x_init_hw_common()
7155 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); in bnx2x_init_hw_common()
7178 * b. Polling for scan_on=0 for that PF. in bnx2x_init_hw_common()
7203 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); in bnx2x_init_hw_common()
7204 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); in bnx2x_init_hw_common()
7207 ilt_cli.start = 0; in bnx2x_init_hw_common()
7231 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); in bnx2x_init_hw_common()
7232 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); in bnx2x_init_hw_common()
7236 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); in bnx2x_init_hw_common()
7259 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); in bnx2x_init_hw_common()
7281 REG_WR(bp, QM_REG_SOFT_RESET, 0); in bnx2x_init_hw_common()
7290 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); in bnx2x_init_hw_common()
7295 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); in bnx2x_init_hw_common()
7305 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); in bnx2x_init_hw_common()
7306 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); in bnx2x_init_hw_common()
7307 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); in bnx2x_init_hw_common()
7308 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); in bnx2x_init_hw_common()
7309 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); in bnx2x_init_hw_common()
7343 0x80000000); in bnx2x_init_hw_common()
7345 0x80000000); in bnx2x_init_hw_common()
7356 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); in bnx2x_init_hw_common()
7357 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); in bnx2x_init_hw_common()
7358 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); in bnx2x_init_hw_common()
7359 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); in bnx2x_init_hw_common()
7360 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); in bnx2x_init_hw_common()
7372 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); in bnx2x_init_hw_common()
7373 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); in bnx2x_init_hw_common()
7374 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); in bnx2x_init_hw_common()
7375 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); in bnx2x_init_hw_common()
7376 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); in bnx2x_init_hw_common()
7377 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); in bnx2x_init_hw_common()
7378 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); in bnx2x_init_hw_common()
7379 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); in bnx2x_init_hw_common()
7380 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); in bnx2x_init_hw_common()
7381 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); in bnx2x_init_hw_common()
7383 REG_WR(bp, SRC_REG_SOFT_RST, 0); in bnx2x_init_hw_common()
7392 val = (4 << 24) + (0 << 12) + 1024; in bnx2x_init_hw_common()
7396 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); in bnx2x_init_hw_common()
7398 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); in bnx2x_init_hw_common()
7401 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); in bnx2x_init_hw_common()
7406 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); in bnx2x_init_hw_common()
7412 REG_WR(bp, 0x2814, 0xffffffff); in bnx2x_init_hw_common()
7413 REG_WR(bp, 0x3820, 0xffffffff); in bnx2x_init_hw_common()
7458 REG_WR(bp, CFC_REG_DEBUG0, 0); in bnx2x_init_hw_common()
7464 val = *bnx2x_sp(bp, wb_data[0]); in bnx2x_init_hw_common()
7467 if ((val == 0) && bnx2x_int_mem_test(bp)) { in bnx2x_init_hw_common()
7490 return 0; in bnx2x_init_hw_common()
7509 return 0; in bnx2x_init_hw_common_chip()
7521 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bnx2x_init_hw_port()
7569 ((val % 64) ? 1 : 0); in bnx2x_init_hw_port()
7589 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); in bnx2x_init_hw_port()
7592 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); in bnx2x_init_hw_port()
7595 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); in bnx2x_init_hw_port()
7625 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); in bnx2x_init_hw_port()
7635 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); in bnx2x_init_hw_port()
7645 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_init_hw_port()
7646 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_init_hw_port()
7654 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use in bnx2x_init_hw_port()
7655 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF in bnx2x_init_hw_port()
7657 val = IS_MF(bp) ? 0xF7 : 0x7; in bnx2x_init_hw_port()
7659 val |= CHIP_IS_E1(bp) ? 0 : 0x10; in bnx2x_init_hw_port()
7682 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); in bnx2x_init_hw_port()
7698 /* 0x2 disable mf_ov, 0x1 enable */ in bnx2x_init_hw_port()
7700 (IS_MF_SD(bp) ? 0x1 : 0x2)); in bnx2x_init_hw_port()
7703 val = 0; in bnx2x_init_hw_port()
7718 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); in bnx2x_init_hw_port()
7719 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); in bnx2x_init_hw_port()
7737 return 0; in bnx2x_init_hw_port()
7750 wb_write[0] = ONCHIP_ADDR1(addr); in bnx2x_ilt_wr()
7762 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; in bnx2x_igu_clear_sb_gen()
7778 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", in bnx2x_igu_clear_sb_gen()
7782 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", in bnx2x_igu_clear_sb_gen()
7807 bnx2x_ilt_wr(bp, i, 0); in bnx2x_clear_func_ilt()
7847 int vlan_en = 0, mac_en[NUM_MACS]; in bnx2x_reset_nic_mode()
7851 bnx2x_set_rx_filter(&bp->link_params, 0); in bnx2x_reset_nic_mode()
7856 NIG_REG_LLH0_FUNC_EN, 0); in bnx2x_reset_nic_mode()
7857 for (i = 0; i < NUM_MACS; i++) { in bnx2x_reset_nic_mode()
7865 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0); in bnx2x_reset_nic_mode()
7871 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0); in bnx2x_reset_nic_mode()
7885 REG_WR(bp, PRS_REG_NIC_MODE, 0); in bnx2x_reset_nic_mode()
7893 for (i = 0; i < NUM_MACS; i++) { in bnx2x_reset_nic_mode()
7906 rc = bnx2x_func_switch_update(bp, 0); in bnx2x_reset_nic_mode()
7913 return 0; in bnx2x_reset_nic_mode()
7933 return 0; in bnx2x_init_hw_func_cnic()
7990 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes in bnx2x_init_hw_func()
7994 for (i = 0; i < L2_ILT_LINES(bp); i++) { in bnx2x_init_hw_func()
8005 REG_WR(bp, PRS_REG_NIC_MODE, 0); in bnx2x_init_hw_func()
8085 REG_WR(bp, PBF_REG_DISABLE_PF, 0); in bnx2x_init_hw_func()
8107 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_init_hw_func()
8109 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_init_hw_func()
8110 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_init_hw_func()
8117 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_init_hw_func()
8120 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); in bnx2x_init_hw_func()
8121 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); in bnx2x_init_hw_func()
8127 int dsb_idx = 0; in bnx2x_init_hw_func()
8130 * E2 mode: address 0-135 match to the mapping memory; in bnx2x_init_hw_func()
8141 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 in bnx2x_init_hw_func()
8151 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { in bnx2x_init_hw_func()
8155 for (i = 0; i < num_segs; i++) { in bnx2x_init_hw_func()
8158 REG_WR(bp, addr, 0); in bnx2x_init_hw_func()
8160 /* send consumer update with value 0 */ in bnx2x_init_hw_func()
8162 USTORM_ID, 0, IGU_INT_NOP, 1); in bnx2x_init_hw_func()
8184 for (i = 0; i < (num_segs * E1HVN_MAX); in bnx2x_init_hw_func()
8188 REG_WR(bp, addr, 0); in bnx2x_init_hw_func()
8190 /* send consumer update with 0 */ in bnx2x_init_hw_func()
8193 USTORM_ID, 0, IGU_INT_NOP, 1); in bnx2x_init_hw_func()
8195 CSTORM_ID, 0, IGU_INT_NOP, 1); in bnx2x_init_hw_func()
8197 XSTORM_ID, 0, IGU_INT_NOP, 1); in bnx2x_init_hw_func()
8199 TSTORM_ID, 0, IGU_INT_NOP, 1); in bnx2x_init_hw_func()
8201 ATTENTION_ID, 0, IGU_INT_NOP, 1); in bnx2x_init_hw_func()
8204 USTORM_ID, 0, IGU_INT_NOP, 1); in bnx2x_init_hw_func()
8206 ATTENTION_ID, 0, IGU_INT_NOP, 1); in bnx2x_init_hw_func()
8212 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); in bnx2x_init_hw_func()
8213 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); in bnx2x_init_hw_func()
8214 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); in bnx2x_init_hw_func()
8215 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); in bnx2x_init_hw_func()
8216 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); in bnx2x_init_hw_func()
8217 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); in bnx2x_init_hw_func()
8222 REG_WR(bp, 0x2114, 0xffffffff); in bnx2x_init_hw_func()
8223 REG_WR(bp, 0x2120, 0xffffffff); in bnx2x_init_hw_func()
8235 "Hmmm... Parity errors in HC block during function init (0x%x)!\n", in bnx2x_init_hw_func()
8264 return 0; in bnx2x_init_hw_func()
8297 for (i = 0; i < L2_ILT_LINES(bp); i++) in bnx2x_free_mem()
8343 return 0; in bnx2x_alloc_mem_cnic()
8387 for (i = 0, allocated = 0; allocated < context_size; i++) { in bnx2x_alloc_mem()
8418 return 0; in bnx2x_alloc_mem()
8437 memset(&ramrod_param, 0, sizeof(ramrod_param)); in bnx2x_set_mac_one()
8461 rc = 0; in bnx2x_set_mac_one()
8462 } else if (rc < 0) in bnx2x_set_mac_one()
8475 memset(&ramrod_param, 0, sizeof(ramrod_param)); in bnx2x_set_vlan_one()
8497 rc = 0; in bnx2x_set_vlan_one()
8498 } else if (rc < 0) { in bnx2x_set_vlan_one()
8513 bp->vlan_cnt = 0; in bnx2x_clear_vlan_info()
8518 struct bnx2x_vlan_mac_obj *vlan_obj = &bp->sp_objs[0].vlan_obj; in bnx2x_del_all_vlans()
8519 unsigned long ramrod_flags = 0, vlan_flags = 0; in bnx2x_del_all_vlans()
8530 return 0; in bnx2x_del_all_vlans()
8538 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; in bnx2x_del_all_macs()
8548 if (rc < 0) in bnx2x_del_all_macs()
8557 unsigned long ramrod_flags = 0; in bnx2x_set_eth_mac()
8573 return bnx2x_setup_queue(bp, &bp->fp[0], true); in bnx2x_setup_leading()
8575 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true); in bnx2x_setup_leading()
8587 int rc = 0; in bnx2x_set_int_mode()
8601 return 0; in bnx2x_set_int_mode()
8626 return 0; in bnx2x_set_int_mode()
8641 u16 line = 0; in bnx2x_ilt_set_info()
8658 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", in bnx2x_ilt_set_info()
8670 ilt_client->flags = 0; in bnx2x_ilt_set_info()
8680 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", in bnx2x_ilt_set_info()
8693 ilt_client->flags = 0; in bnx2x_ilt_set_info()
8699 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", in bnx2x_ilt_set_info()
8710 ilt_client->flags = 0; in bnx2x_ilt_set_info()
8716 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", in bnx2x_ilt_set_info()
8757 (1000000 / bp->rx_ticks) : 0; in bnx2x_pf_q_prep_init()
8759 (1000000 / bp->tx_ticks) : 0; in bnx2x_pf_q_prep_init()
8794 memset(tx_only_params, 0, sizeof(*tx_only_params)); in bnx2x_setup_tx_only()
8847 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, in bnx2x_setup_queue()
8848 IGU_INT_ENABLE, 0); in bnx2x_setup_queue()
8870 memset(setup_params, 0, sizeof(*setup_params)); in bnx2x_setup_queue()
8942 memset(&q_params.params.terminate, 0, in bnx2x_stop_queue()
8952 memset(&q_params.params.cfc_del, 0, in bnx2x_stop_queue()
8968 memset(&q_params.params.terminate, 0, in bnx2x_stop_queue()
8976 memset(&q_params.params.cfc_del, 0, in bnx2x_stop_queue()
8989 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); in bnx2x_reset_func()
8990 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); in bnx2x_reset_func()
8991 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); in bnx2x_reset_func()
8992 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); in bnx2x_reset_func()
9013 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) in bnx2x_reset_func()
9015 0); in bnx2x_reset_func()
9019 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_reset_func()
9020 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_reset_func()
9022 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); in bnx2x_reset_func()
9023 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); in bnx2x_reset_func()
9028 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); in bnx2x_reset_func()
9033 for (i = 0; i < 200; i++) { in bnx2x_reset_func()
9048 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); in bnx2x_reset_func()
9049 ilt_cli.start = 0; in bnx2x_reset_func()
9053 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); in bnx2x_reset_func()
9060 bp->dmae_ready = 0; in bnx2x_reset_func()
9071 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bnx2x_reset_port()
9074 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); in bnx2x_reset_port()
9077 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); in bnx2x_reset_port()
9080 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); in bnx2x_reset_port()
9134 return 0; in bnx2x_func_stop()
9147 u32 reset_code = 0; in bnx2x_send_unload_req()
9165 * preserve entry 0 which is used by the PMF in bnx2x_send_unload_req()
9169 val = (mac_addr[0] << 8) | mac_addr[1]; in bnx2x_send_unload_req()
9188 reset_code = bnx2x_fw_command(bp, reset_code, 0); in bnx2x_send_unload_req()
9193 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], in bnx2x_send_unload_req()
9195 bnx2x_load_count[path][0]--; in bnx2x_send_unload_req()
9198 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], in bnx2x_send_unload_req()
9200 if (bnx2x_load_count[path][0] == 0) in bnx2x_send_unload_req()
9202 else if (bnx2x_load_count[path][1 + port] == 0) in bnx2x_send_unload_req()
9219 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; in bnx2x_send_unload_done()
9229 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; in bnx2x_func_wait_started()
9232 return 0; in bnx2x_func_wait_started()
9250 synchronize_irq(bp->msix_table[0].vector); in bnx2x_func_wait_started()
9290 return 0; in bnx2x_func_wait_started()
9299 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0); in bnx2x_disable_ptp()
9303 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF); in bnx2x_disable_ptp()
9305 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF); in bnx2x_disable_ptp()
9307 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF); in bnx2x_disable_ptp()
9309 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF); in bnx2x_disable_ptp()
9313 NIG_REG_P0_PTP_EN, 0x0); in bnx2x_disable_ptp()
9338 int i, rc = 0; in bnx2x_chip_cleanup()
9359 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, in bnx2x_chip_cleanup()
9361 if (rc < 0) in bnx2x_chip_cleanup()
9365 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, in bnx2x_chip_cleanup()
9367 if (rc < 0) in bnx2x_chip_cleanup()
9378 if (rc < 0) in bnx2x_chip_cleanup()
9384 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bnx2x_chip_cleanup()
9400 if (rc < 0) in bnx2x_chip_cleanup()
9450 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) in bnx2x_chip_cleanup()
9517 val &= ~(0x300); in bnx2x_disable_close_the_gate()
9566 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9615 if (shmem > 0) in bnx2x_reset_mcp_prep()
9616 REG_WR(bp, shmem + validity_offset, 0); in bnx2x_reset_mcp_prep()
9642 int cnt = 0; in bnx2x_init_shmem()
9643 u32 val = 0; in bnx2x_init_shmem()
9648 /* If we read all 0xFFs, means we are in PCI error state and in bnx2x_init_shmem()
9651 if (bp->common.shmem_base == 0xFFFFFFFF) { in bnx2x_init_shmem()
9659 return 0; in bnx2x_init_shmem()
9685 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); in bnx2x_pxp_prep()
9686 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); in bnx2x_pxp_prep()
9750 reset_mask1 = 0xffffffff; in bnx2x_process_kill_chip_reset()
9753 reset_mask2 = 0xffff; in bnx2x_process_kill_chip_reset()
9755 reset_mask2 = 0x1ffff; in bnx2x_process_kill_chip_reset()
9757 reset_mask2 = 0xfffff; in bnx2x_process_kill_chip_reset()
9759 reset_mask2 = 0x3ffffff; in bnx2x_process_kill_chip_reset()
9801 * It should get cleared in no more than 1s. Returns 0 if
9807 u32 pend_bits = 0; in bnx2x_er_poll_igu_vq()
9812 if (pend_bits == 0) in bnx2x_er_poll_igu_vq()
9816 } while (cnt-- > 0); in bnx2x_er_poll_igu_vq()
9818 if (cnt <= 0) { in bnx2x_er_poll_igu_vq()
9824 return 0; in bnx2x_er_poll_igu_vq()
9830 u32 val = 0; in bnx2x_process_kill()
9832 u32 tags_63_32 = 0; in bnx2x_process_kill()
9844 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && in bnx2x_process_kill()
9845 ((port_is_idle_0 & 0x1) == 0x1) && in bnx2x_process_kill()
9846 ((port_is_idle_1 & 0x1) == 0x1) && in bnx2x_process_kill()
9847 (pgl_exp_rom2 == 0xffffffff) && in bnx2x_process_kill()
9848 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) in bnx2x_process_kill()
9851 } while (cnt-- > 0); in bnx2x_process_kill()
9853 if (cnt <= 0) { in bnx2x_process_kill()
9855 …BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_ro… in bnx2x_process_kill()
9873 REG_WR(bp, MISC_REG_UNPREPARED, 0); in bnx2x_process_kill()
9896 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f); in bnx2x_process_kill()
9911 return 0; in bnx2x_process_kill()
9916 int rc = 0; in bnx2x_leader_reset()
9937 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); in bnx2x_leader_reset()
9964 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); in bnx2x_leader_reset()
9965 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); in bnx2x_leader_reset()
9968 bp->is_leader = 0; in bnx2x_leader_reset()
10007 for (vf_idx = 0; vf_idx < bp->requested_nr_virtfn; vf_idx++) { in bnx2x_parity_recover()
10054 int other_engine = BP_PATH(bp) ? 0 : 1; in bnx2x_parity_recover()
10167 u16 vxlan_port = 0, geneve_port = 0; in bnx2x_udp_port_update()
10199 BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n", in bnx2x_udp_port_update()
10214 udp_tunnel_nic_get_port(netdev, table, 0, &ti); in bnx2x_udp_tunnel_sync()
10256 bp->sp_rtnl_state = 0; in bnx2x_sp_rtnl_task()
10276 bp->sp_rtnl_state = 0; in bnx2x_sp_rtnl_task()
10280 bp->link_vars.link_up = 0; in bnx2x_sp_rtnl_task()
10421 REG_WR(bp, vals->umac_addr[port], 0); in bnx2x_prev_unload_close_umac()
10434 memset(vals, 0, sizeof(*vals)); in bnx2x_prev_unload_close_mac()
10455 wb_data[0] = REG_RD(bp, base_addr + offset); in bnx2x_prev_unload_close_mac()
10456 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); in bnx2x_prev_unload_close_mac()
10458 vals->bmac_val[0] = wb_data[0]; in bnx2x_prev_unload_close_mac()
10460 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; in bnx2x_prev_unload_close_mac()
10461 REG_WR(bp, vals->bmac_addr, wb_data[0]); in bnx2x_prev_unload_close_mac()
10462 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); in bnx2x_prev_unload_close_mac()
10467 REG_WR(bp, vals->emac_addr, 0); in bnx2x_prev_unload_close_mac()
10480 REG_WR(bp, vals->xmac_addr, 0); in bnx2x_prev_unload_close_mac()
10484 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0, in bnx2x_prev_unload_close_mac()
10494 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10496 0x1848 + ((f) << 4))
10497 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10498 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10501 #define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10502 #define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10503 #define BCM_5710_UNDI_FW_MF_VERS (0x05)
10508 * it initializes CID offset for normal bell to 0x7 in bnx2x_prev_is_after_undi()
10514 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) { in bnx2x_prev_is_after_undi()
10539 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n", in bnx2x_prev_unload_undi_inc()
10552 return 0; in bnx2x_prev_mcp_done()
10583 rc = 0; in bnx2x_prev_path_mark_eeh()
10653 tmp_list->aer = 0; in bnx2x_prev_mark_path()
10656 return 0; in bnx2x_prev_mark_path()
10670 tmp_list->aer = 0; in bnx2x_prev_mark_path()
10671 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; in bnx2x_prev_mark_path()
10698 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", in bnx2x_do_flr()
10707 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); in bnx2x_do_flr()
10709 return 0; in bnx2x_do_flr()
10743 return 0; in bnx2x_prev_unload_uncommon()
10759 u32 reset_reg, tmp_reg = 0, rc; in bnx2x_prev_unload_common()
10769 memset(&mac_vals, 0, sizeof(mac_vals)); in bnx2x_prev_unload_common()
10784 bnx2x_set_rx_filter(&bp->link_params, 0); in bnx2x_prev_unload_common()
10786 bnx2x_set_rx_filter(&bp->link_params, 0); in bnx2x_prev_unload_common()
10793 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); in bnx2x_prev_unload_common()
10799 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); in bnx2x_prev_unload_common()
10810 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); in bnx2x_prev_unload_common()
10834 if (mac_vals.umac_addr[0]) in bnx2x_prev_unload_common()
10835 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]); in bnx2x_prev_unload_common()
10841 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); in bnx2x_prev_unload_common()
10879 REG_WR(bp, hw_lock_reg, 0xffffffff); in bnx2x_prev_unload()
10889 int aer = 0; in bnx2x_prev_unload()
10891 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); in bnx2x_prev_unload()
10943 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ in bnx2x_get_common_hwinfo()
10945 id = ((val & 0xffff) << 16); in bnx2x_get_common_hwinfo()
10947 id |= ((val & 0xf) << 12); in bnx2x_get_common_hwinfo()
10949 /* Metal is read from PCI regs, but we can't access >=0x400 from in bnx2x_get_common_hwinfo()
10953 id |= (((val >> 24) & 0xf) << 4); in bnx2x_get_common_hwinfo()
10955 id |= (val & 0xf); in bnx2x_get_common_hwinfo()
10962 (bp->common.chip_id & 0x0000FFFF); in bnx2x_get_common_hwinfo()
10965 (bp->common.chip_id & 0x0000FFFF); in bnx2x_get_common_hwinfo()
10966 bp->common.chip_id |= 0x1; in bnx2x_get_common_hwinfo()
10974 if ((val & 1) == 0) in bnx2x_get_common_hwinfo()
10984 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ in bnx2x_get_common_hwinfo()
10986 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ in bnx2x_get_common_hwinfo()
10989 bp->pfid = bp->pf_num; /* 0..7 */ in bnx2x_get_common_hwinfo()
10995 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); in bnx2x_get_common_hwinfo()
10997 val = (REG_RD(bp, 0x2874) & 0x55); in bnx2x_get_common_hwinfo()
10998 if ((bp->common.chip_id & 0x1) || in bnx2x_get_common_hwinfo()
10999 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { in bnx2x_get_common_hwinfo()
11007 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", in bnx2x_get_common_hwinfo()
11025 bp->link_params.lfa_base = 0; in bnx2x_get_common_hwinfo()
11026 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", in bnx2x_get_common_hwinfo()
11036 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); in bnx2x_get_common_hwinfo()
11042 bp->link_params.feature_config_flags = 0; in bnx2x_get_common_hwinfo()
11062 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; in bnx2x_get_common_hwinfo()
11066 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; in bnx2x_get_common_hwinfo()
11069 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; in bnx2x_get_common_hwinfo()
11072 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; in bnx2x_get_common_hwinfo()
11076 FEATURE_CONFIG_MT_SUPPORT : 0; in bnx2x_get_common_hwinfo()
11079 BC_SUPPORTS_PFC_STATS : 0; in bnx2x_get_common_hwinfo()
11082 BC_SUPPORTS_FCOE_FEATURES : 0; in bnx2x_get_common_hwinfo()
11085 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0; in bnx2x_get_common_hwinfo()
11088 BC_SUPPORTS_RMMOD_CMD : 0; in bnx2x_get_common_hwinfo()
11109 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; in bnx2x_get_common_hwinfo()
11131 u8 fid, igu_sb_cnt = 0; in bnx2x_get_igu_cam_info()
11133 bp->igu_base_sb = 0xff; in bnx2x_get_igu_cam_info()
11143 return 0; in bnx2x_get_igu_cam_info()
11147 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; in bnx2x_get_igu_cam_info()
11156 if (IGU_VEC(val) == 0) in bnx2x_get_igu_cam_info()
11160 if (bp->igu_base_sb == 0xff) in bnx2x_get_igu_cam_info()
11177 if (igu_sb_cnt == 0) { in bnx2x_get_igu_cam_info()
11182 return 0; in bnx2x_get_igu_cam_info()
11187 int cfg_size = 0, idx, port = BP_PORT(bp); in bnx2x_link_settings_supported()
11190 bp->port.supported[0] = 0; in bnx2x_link_settings_supported()
11191 bp->port.supported[1] = 0; in bnx2x_link_settings_supported()
11194 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; in bnx2x_link_settings_supported()
11198 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; in bnx2x_link_settings_supported()
11206 bp->port.supported[0] = in bnx2x_link_settings_supported()
11209 bp->port.supported[0] = in bnx2x_link_settings_supported()
11218 if (!(bp->port.supported[0] || bp->port.supported[1])) { in bnx2x_link_settings_supported()
11219 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", in bnx2x_link_settings_supported()
11233 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); in bnx2x_link_settings_supported()
11237 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); in bnx2x_link_settings_supported()
11240 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", in bnx2x_link_settings_supported()
11241 bp->port.link_config[0]); in bnx2x_link_settings_supported()
11245 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); in bnx2x_link_settings_supported()
11247 for (idx = 0; idx < cfg_size; idx++) { in bnx2x_link_settings_supported()
11282 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], in bnx2x_link_settings_supported()
11288 u32 link_config, idx, cfg_size = 0; in bnx2x_link_settings_requested()
11289 bp->port.advertising[0] = 0; in bnx2x_link_settings_requested()
11290 bp->port.advertising[1] = 0; in bnx2x_link_settings_requested()
11300 for (idx = 0; idx < cfg_size; idx++) { in bnx2x_link_settings_requested()
11334 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", in bnx2x_link_settings_requested()
11351 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", in bnx2x_link_settings_requested()
11367 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", in bnx2x_link_settings_requested()
11385 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", in bnx2x_link_settings_requested()
11407 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", in bnx2x_link_settings_requested()
11423 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", in bnx2x_link_settings_requested()
11446 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", in bnx2x_link_settings_requested()
11457 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", in bnx2x_link_settings_requested()
11477 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", in bnx2x_link_settings_requested()
11505 bp->link_params.speed_cap_mask[0] = in bnx2x_get_port_hwinfo()
11513 bp->port.link_config[0] = in bnx2x_get_port_hwinfo()
11535 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", in bnx2x_get_port_hwinfo()
11537 bp->link_params.speed_cap_mask[0], in bnx2x_get_port_hwinfo()
11538 bp->port.link_config[0]); in bnx2x_get_port_hwinfo()
11540 bp->link_params.switch_cfg = (bp->port.link_config[0] & in bnx2x_get_port_hwinfo()
11573 bp->link_params.eee_mode = 0; in bnx2x_get_port_hwinfo()
11594 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", in bnx2x_get_iscsi_info()
11622 u8 count = 0; in bnx2x_shared_fcoe_funcs()
11650 for (port = 0; port < port_cnt; port++) { in bnx2x_shared_fcoe_funcs()
11719 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); in bnx2x_get_fcoe_info()
11917 if (val != 0xffff) { in validate_set_si_mode()
11929 u32 val = 0, val2 = 0; in bnx2x_get_hwinfo()
11930 int rc = 0; in bnx2x_get_hwinfo()
11933 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) { in bnx2x_get_hwinfo()
11948 bp->igu_base_sb = 0; in bnx2x_get_hwinfo()
11964 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); in bnx2x_get_hwinfo()
12013 bp->mf_ov = 0; in bnx2x_get_hwinfo()
12014 bp->mf_mode = 0; in bnx2x_get_hwinfo()
12015 bp->mf_sub_mode = 0; in bnx2x_get_hwinfo()
12019 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", in bnx2x_get_hwinfo()
12050 mac_upper) != 0xffff) && in bnx2x_get_hwinfo()
12105 bp->mf_config[vn] = 0; in bnx2x_get_hwinfo()
12119 bp->mf_config[vn] = 0; in bnx2x_get_hwinfo()
12120 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n", in bnx2x_get_hwinfo()
12126 bp->mf_config[vn] = 0; in bnx2x_get_hwinfo()
12127 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); in bnx2x_get_hwinfo()
12142 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", in bnx2x_get_hwinfo()
12214 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); in bnx2x_read_fwinfo()
12222 if (rodi < 0 || kw_len != VENDOR_ID_LEN) in bnx2x_read_fwinfo()
12231 if (rodi >= 0 && kw_len < sizeof(bp->fw_ver)) { in bnx2x_read_fwinfo()
12242 u32 flags = 0; in bnx2x_set_modes_bitmap()
12332 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); in bnx2x_init_bp()
12344 if (BP_NOMCP(bp) && (func == 0)) in bnx2x_init_bp()
12365 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL; in bnx2x_init_bp()
12375 timer_setup(&bp->timer, bnx2x_timer, 0); in bnx2x_init_bp()
12453 int other_engine = BP_PATH(bp) ? 0 : 1; in bnx2x_open()
12492 } while (0); in bnx2x_open()
12501 return 0; in bnx2x_open()
12512 return 0; in bnx2x_close()
12546 int offset = 0; in bnx2x_init_mcast_macs_list()
12567 offset = 0; in bnx2x_init_mcast_macs_list()
12570 return 0; in bnx2x_init_mcast_macs_list()
12578 * We will use zero (0) as a MAC type for these MACs.
12586 unsigned long ramrod_flags = 0; in bnx2x_set_uc_list()
12590 if (rc < 0) { in bnx2x_set_uc_list()
12602 rc = 0; in bnx2x_set_uc_list()
12604 } else if (rc < 0) { in bnx2x_set_uc_list()
12623 int rc = 0; in bnx2x_set_mc_list_e1x()
12629 if (rc < 0) { in bnx2x_set_mc_list_e1x()
12643 if (rc < 0) in bnx2x_set_mc_list_e1x()
12658 int rc = 0; in bnx2x_set_mc_list()
12674 if (rc < 0) in bnx2x_set_mc_list()
12682 if (rc < 0) in bnx2x_set_mc_list()
12722 if (bnx2x_set_mc_list(bp) < 0) in bnx2x_set_rx_mode_inner()
12727 if (bnx2x_set_uc_list(bp) < 0) in bnx2x_set_rx_mode_inner()
12735 BNX2X_SP_RTNL_VFPF_MCAST, 0); in bnx2x_set_rx_mode_inner()
12772 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", in bnx2x_mdio_read()
12781 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); in bnx2x_mdio_read()
12796 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", in bnx2x_mdio_write()
12821 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", in bnx2x_ioctl()
12839 return 0; in bnx2x_validate_addr()
12853 return 0; in bnx2x_get_phys_port_id()
12887 unsigned long ramrod_flags = 0; in __bnx2x_vlan_configure_vid()
12902 int rc = 0; in bnx2x_vlan_configure_vid_list()
12923 return 0; in bnx2x_vlan_configure_vid_list()
12950 return 0; in bnx2x_vlan_reconfigure_vid()
12971 return 0; in bnx2x_vlan_rx_add_vid()
12979 int rc = 0; in bnx2x_vlan_rx_kill_vid()
13063 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { in bnx2x_init_dev()
13117 dev->mem_start = pci_resource_start(pdev, 0); in bnx2x_init_dev()
13119 dev->mem_end = pci_resource_end(pdev, 0); in bnx2x_init_dev()
13123 bp->regview = pci_ioremap_bar(pdev, 0); in bnx2x_init_dev()
13159 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); in bnx2x_init_dev()
13160 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); in bnx2x_init_dev()
13161 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); in bnx2x_init_dev()
13162 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); in bnx2x_init_dev()
13165 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); in bnx2x_init_dev()
13166 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); in bnx2x_init_dev()
13167 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); in bnx2x_init_dev()
13168 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); in bnx2x_init_dev()
13244 bp->mdio.mmds = 0; in bnx2x_init_dev()
13250 return 0; in bnx2x_init_dev()
13283 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { in bnx2x_check_firmware()
13297 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { in bnx2x_check_firmware()
13307 if (fw_ver[0] != bp->fw_major || fw_ver[1] != bp->fw_minor || in bnx2x_check_firmware()
13310 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], in bnx2x_check_firmware()
13315 return 0; in bnx2x_check_firmware()
13324 for (i = 0; i < n/4; i++) in be32_to_cpu_n()
13338 for (i = 0, j = 0; i < n/8; i++, j += 2) { in bnx2x_prep_ops()
13340 target[i].op = (tmp >> 24) & 0xff; in bnx2x_prep_ops()
13341 target[i].offset = tmp & 0xffffff; in bnx2x_prep_ops()
13355 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { in bnx2x_prep_iro()
13359 target[i].m1 = (tmp >> 16) & 0xffff; in bnx2x_prep_iro()
13360 target[i].m2 = tmp & 0xffff; in bnx2x_prep_iro()
13363 target[i].m3 = (tmp >> 16) & 0xffff; in bnx2x_prep_iro()
13364 target[i].size = tmp & 0xffff; in bnx2x_prep_iro()
13375 for (i = 0; i < n/2; i++) in be16_to_cpu_n()
13387 } while (0)
13396 return 0; in bnx2x_init_firmware()
13474 return 0; in bnx2x_init_firmware()
13551 u16 control = 0; in bnx2x_get_num_non_def_sbs()
13626 #define tsgen_ctrl 0x0
13627 #define tsgen_freecount 0x10
13628 #define tsgen_synctime_t0 0x20
13629 #define tsgen_offset_t0 0x28
13630 #define tsgen_drift_t0 0x30
13631 #define tsgen_synctime_t1 0x58
13632 #define tsgen_offset_t1 0x60
13633 #define tsgen_drift_t1 0x68
13667 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0; in bnx2x_ptp_adjfine()
13678 if (ppb < 0) { in bnx2x_ptp_adjfine()
13680 drift_dir = 0; in bnx2x_ptp_adjfine()
13683 if (ppb == 0) { in bnx2x_ptp_adjfine()
13685 best_period = 0x1FFFFFF; in bnx2x_ptp_adjfine()
13693 for (val = 0; val <= 31; val++) { in bnx2x_ptp_adjfine()
13694 if ((val & 0x7) == 0) in bnx2x_ptp_adjfine()
13698 if (period1 != 0) in bnx2x_ptp_adjfine()
13702 if (dif1 < 0) in bnx2x_ptp_adjfine()
13705 if (dif2 < 0) in bnx2x_ptp_adjfine()
13727 return 0; in bnx2x_ptp_adjfine()
13744 return 0; in bnx2x_ptp_adjtime()
13764 return 0; in bnx2x_ptp_gettime()
13786 return 0; in bnx2x_ptp_settime()
13805 bp->ptp_clock_info.n_alarm = 0; in bnx2x_register_phc()
13806 bp->ptp_clock_info.n_ext_ts = 0; in bnx2x_register_phc()
13807 bp->ptp_clock_info.n_per_out = 0; in bnx2x_register_phc()
13808 bp->ptp_clock_info.pps = 0; in bnx2x_register_phc()
13838 ktime_t fw_ready_time = ktime_set(5, 0); in bnx2x_init_one()
13853 if (max_cos_est < 0) in bnx2x_init_one()
13856 cnic_cnt = is_vf ? 0 : 1; in bnx2x_init_one()
13861 max_non_def_sbs += is_vf ? 1 : 0; in bnx2x_init_one()
13884 bp->flags = 0; in bnx2x_init_one()
13897 if (rc < 0) { in bnx2x_init_one()
14004 return 0; in bnx2x_init_one()
14046 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0); in __bnx2x_remove()
14156 return 0; in bnx2x_eeh_nic_unload()
14258 bp->sp_state = 0; in bnx2x_io_slot_reset()
14259 bp->port.pmf = 0; in bnx2x_io_slot_reset()
14414 * Return 0 if success, -ENODEV if ramrod doesn't return.
14418 unsigned long ramrod_flags = 0; in bnx2x_set_iscsi_eth_mac_addr()
14446 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; in bnx2x_cnic_sp_post()
14529 for (i = 0; i < count; i++) { in bnx2x_cnic_sp_queue()
14554 bnx2x_cnic_sp_post(bp, 0); in bnx2x_cnic_sp_queue()
14562 int rc = 0; in bnx2x_cnic_ctl_send()
14577 int rc = 0; in bnx2x_cnic_ctl_send_bh()
14593 struct cnic_ctl_info ctl = {0}; in bnx2x_cnic_notify()
14602 struct cnic_ctl_info ctl = {0}; in bnx2x_cnic_cfc_comp()
14610 bnx2x_cnic_sp_post(bp, 0); in bnx2x_cnic_cfc_comp()
14620 unsigned long accept_flags = 0, ramrod_flags = 0; in bnx2x_set_iscsi_eth_rx_mode()
14648 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, in bnx2x_set_iscsi_eth_rx_mode()
14656 int rc = 0; in bnx2x_drv_ctl()
14677 unsigned long sp_bits = 0; in bnx2x_drv_ctl()
14714 unsigned long sp_bits = 0; in bnx2x_drv_ctl()
14775 for (i = 0; i < sizeof(struct fcoe_capabilities); in bnx2x_drv_ctl()
14780 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); in bnx2x_drv_ctl()
14798 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); in bnx2x_drv_ctl()
14841 if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0])) in bnx2x_get_fc_npiv()
14877 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n", in bnx2x_get_fc_npiv()
14881 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n", in bnx2x_get_fc_npiv()
14887 for (i = 0; i < cnic_tbl->count; i++) { in bnx2x_get_fc_npiv()
14892 rc = 0; in bnx2x_get_fc_npiv()
14904 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; in bnx2x_setup_cnic_irq_info()
14905 cp->irq_arr[0].vector = bp->msix_table[1].vector; in bnx2x_setup_cnic_irq_info()
14908 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; in bnx2x_setup_cnic_irq_info()
14911 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; in bnx2x_setup_cnic_irq_info()
14913 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; in bnx2x_setup_cnic_irq_info()
14915 cp->irq_arr[0].status_blk_map = bp->cnic_sb_mapping; in bnx2x_setup_cnic_irq_info()
14916 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); in bnx2x_setup_cnic_irq_info()
14917 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); in bnx2x_setup_cnic_irq_info()
14981 bp->cnic_spq_pending = 0; in bnx2x_register_cnic()
14982 bp->cnic_kwq_pending = 0; in bnx2x_register_cnic()
14986 cp->num_irq = 0; in bnx2x_register_cnic()
14995 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); in bnx2x_register_cnic()
14997 return 0; in bnx2x_register_cnic()
15006 cp->drv_state = 0; in bnx2x_unregister_cnic()
15014 return 0; in bnx2x_unregister_cnic()
15084 * When pretending to be PF, the pretend value is the function number 0...7
15099 return 0; in bnx2x_pretend_func()
15115 for (i = 0; i < 10; i++) { in bnx2x_ptp_task()
15119 if (val_seq & 0x10000) { in bnx2x_ptp_task()
15135 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000); in bnx2x_ptp_task()
15138 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); in bnx2x_ptp_task()
15168 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000); in bnx2x_set_rx_ts()
15189 phc_cycles = (phc_cycles << 32) + wb_data[0]; in bnx2x_cyclecounter_read()
15198 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter)); in bnx2x_init_cyclecounter()
15201 bp->cyclecounter.shift = 0; in bnx2x_init_cyclecounter()
15231 memset(&q_params, 0, sizeof(q_params)); in bnx2x_enable_ptp_packets()
15254 return 0; in bnx2x_enable_ptp_packets()
15257 #define BNX2X_P2P_DETECT_PARAM_MASK 0x5F5
15258 #define BNX2X_P2P_DETECT_RULE_MASK 0x3DBB
15259 #define BNX2X_PTP_TX_ON_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6AA)
15260 #define BNX2X_PTP_TX_ON_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EEE)
15261 #define BNX2X_PTP_V1_L4_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x7EE)
15262 #define BNX2X_PTP_V1_L4_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3FFE)
15263 #define BNX2X_PTP_V2_L4_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x7EA)
15264 #define BNX2X_PTP_V2_L4_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3FEE)
15265 #define BNX2X_PTP_V2_L2_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6BF)
15266 #define BNX2X_PTP_V2_L2_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EFF)
15267 #define BNX2X_PTP_V2_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6AA)
15268 #define BNX2X_PTP_V2_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EEE)
15277 return 0; in bnx2x_configure_ptp_filters()
15349 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1); in bnx2x_configure_ptp_filters()
15351 return 0; in bnx2x_configure_ptp_filters()
15378 -EFAULT : 0; in bnx2x_hwtstamp_ioctl()
15389 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF); in bnx2x_configure_ptp()
15391 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF); in bnx2x_configure_ptp()
15393 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF); in bnx2x_configure_ptp()
15395 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF); in bnx2x_configure_ptp()
15399 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0); in bnx2x_configure_ptp()
15403 NIG_REG_P0_PTP_EN, 0x3F); in bnx2x_configure_ptp()
15406 wb_data[0] = 0; in bnx2x_configure_ptp()
15407 wb_data[1] = 0; in bnx2x_configure_ptp()
15419 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000); in bnx2x_configure_ptp()
15421 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000); in bnx2x_configure_ptp()
15423 return 0; in bnx2x_configure_ptp()