1477 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_emac_init()
1480 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in bnx2x_emac_init()
1552 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_umac_enable()
1556 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in bnx2x_umac_enable()
1667 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_xmac_init()
1671 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in bnx2x_xmac_init()
1697 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_xmac_init()
1701 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in bnx2x_xmac_init()
1815 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_emac_enable()
2407 		REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_bmac_enable()
2412 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in bnx2x_bmac_enable()
3335 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);  in bnx2x_serdes_deassert()
3337 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);  in bnx2x_serdes_deassert()
3371 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);  in bnx2x_xgxs_deassert()
3373 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);  in bnx2x_xgxs_deassert()
6610 	REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,  in bnx2x_int_link_reset()
12848 			REG_WR(bp, GRCBASE_MISC +  in bnx2x_avoid_link_flap()
12852 			REG_WR(bp, GRCBASE_MISC +  in bnx2x_avoid_link_flap()
13111 		REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_link_reset()