Lines Matching +full:0 +full:x0020000
42 #define DRV_MODULE_VERSION "1.713.36-0"
43 #define BNX2X_BC_VER 0x040200
77 #define BNX2X_MSG_OFF 0x0
78 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
79 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
80 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
81 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
82 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
83 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
84 #define BNX2X_MSG_IOV 0x0800000
85 #define BNX2X_MSG_PTP 0x1000000
86 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
87 #define BNX2X_MSG_ETHTOOL 0x4000000
88 #define BNX2X_MSG_DCB 0x8000000
101 } while (0)
107 } while (0)
113 } while (0)
123 } while (0)
132 } while (0)
142 } while (0)
152 } while (0)
159 } while (0)
165 #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff))
191 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
192 } while (0)
196 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
199 } while (0)
208 } while (0)
265 * CLIDs below is a CLID for func 0, then the CLID for other
280 * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number
282 * the designated UIO cid will come out 0 and it has a special handling for that
284 * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18.
299 /* but wait - avoid UIO special case for cid 0 */
302 /* Properly DPM aligned CID dajusted to cid 0 secal case */
321 #define SM_RX_ID 0
326 #define FIRST_TX_COS_INDEX 0
367 #define BNX2X_TSO_SPLIT_BD (1<<0)
397 #define PAGES_PER_SGE_SHIFT 0
405 SGE_PAGES), 0xffff)
448 el = ((el) | ((u64)0x1 << (bit))); \
449 } while (0)
453 el = ((el) & (~((u64)0x1 << (bit)))); \
454 } while (0)
466 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
471 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
472 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
563 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
615 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
629 #define FCOE_IDX_OFFSET 0
757 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
782 #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff)
784 #define XMIT_PLAIN 0
785 #define XMIT_CSUM_V4 (1 << 0)
850 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
851 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
854 #define CHIP_NUM_57710 0x164e
855 #define CHIP_NUM_57711 0x164f
856 #define CHIP_NUM_57711E 0x1650
857 #define CHIP_NUM_57712 0x1662
858 #define CHIP_NUM_57712_MF 0x1663
859 #define CHIP_NUM_57712_VF 0x166f
860 #define CHIP_NUM_57713 0x1651
861 #define CHIP_NUM_57713E 0x1652
862 #define CHIP_NUM_57800 0x168a
863 #define CHIP_NUM_57800_MF 0x16a5
864 #define CHIP_NUM_57800_VF 0x16a9
865 #define CHIP_NUM_57810 0x168e
866 #define CHIP_NUM_57810_MF 0x16ae
867 #define CHIP_NUM_57810_VF 0x16af
868 #define CHIP_NUM_57811 0x163d
869 #define CHIP_NUM_57811_MF 0x163e
870 #define CHIP_NUM_57811_VF 0x163f
871 #define CHIP_NUM_57840_OBSOLETE 0x168d
872 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
873 #define CHIP_NUM_57840_4_10 0x16a1
874 #define CHIP_NUM_57840_2_20 0x16a2
875 #define CHIP_NUM_57840_MF 0x16a4
876 #define CHIP_NUM_57840_VF 0x16ad
922 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
924 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
925 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
927 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
928 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
930 !(CHIP_REV_VAL(bp) & 0x00001000))
931 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
933 (CHIP_REV_VAL(bp) & 0x00001000))
938 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
939 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
964 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
978 #define INT_BLOCK_HC 0
980 #define INT_BLOCK_MODE_NORMAL 0
988 #define CHIP_4_PORT_MODE 0x0
989 #define CHIP_2_PORT_MODE 0x1
990 #define CHIP_PORT_MODE_NONE 0x2
1043 #define BNX2X_VF_ID_INVALID 0xFF
1095 #define QM_ILT_PAGE_SZ_HW 0
1100 #define TM_ILT_PAGE_SZ_HW 0
1109 #define SRC_ILT_PAGE_SZ_HW 0
1327 SUB_MF_MODE_UNKNOWN = 0,
1360 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1468 #define PCIX_FLAG (1 << 0)
1552 #define IS_MF(bp) (bp->mf_mode != 0)
1576 #define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR)
1581 #define BNX2X_STATE_CLOSED 0
1582 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1583 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1584 #define BNX2X_STATE_OPEN 0x3000
1585 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1586 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1588 #define BNX2X_STATE_DIAG 0xe000
1589 #define BNX2X_STATE_ERROR 0xf000
1598 #define BNX2X_RX_MODE_NONE 0
1726 #define FW_BUF_SIZE 0x8000
1768 #define BNX2X_DCB_STATE_OFF 0
1773 #define BNX2X_DCBX_ENABLED_OFF 0
1855 #define FW_CAP_INVALIDATE_VF_FP_HSI BIT(0)
1907 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1913 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1920 for ((var) = 0; \
1936 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1943 for ((var) = 0; \
1959 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1971 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
2087 } while (ms > 0); in reg_poll()
2103 y = 0; \
2105 } while (0)
2123 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
2127 #define LOAD_NORMAL 0
2131 #define UNLOAD_NORMAL 0
2139 #define DMAE_PCI_ERR_FLAG 0x80000000
2141 #define DMAE_SRC_PCI 0
2144 #define DMAE_DST_NONE 0
2148 #define DMAE_COMP_PCI 0
2153 #define DMAE_COMP_REGULAR 0
2173 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
2178 #define DMAE_CMD_PORT_0 0
2185 #define DMAE_SRC_PF 0
2188 #define DMAE_DST_PF 0
2191 #define DMAE_C_SRC 0
2194 #define DMAE_LEN32_RD_MAX 0x80
2195 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
2197 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
2209 * Driver: 0-3 and 8-11 (for PF dmae operations)
2215 #define PCICFG_LINK_WIDTH 0x1f00000
2217 #define PCICFG_LINK_SPEED 0xf0000
2223 IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF)
2225 #define BNX2X_PHY_LOOPBACK 0
2277 #define ATTN_HARD_WIRED_MASK 0xff00
2372 #define MULTI_MASK 0x7f
2431 #define CMNG_FNS_NONE 0
2434 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2436 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2499 } while (0)