Lines Matching +full:0 +full:x00001480
30 #define TX_BD_FLAGS_CONN_FAULT (1<<0)
40 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8)
57 #define RX_BD_FLAGS_NOPUSH (1<<0)
71 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
279 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0)
321 #define BNX2_L2CTX_TYPE 0x00000000
322 #define BNX2_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
323 #define BNX2_L2CTX_TYPE_TYPE (0xf<<28)
324 #define BNX2_L2CTX_TYPE_TYPE_EMPTY (0<<28)
327 #define BNX2_L2CTX_TX_HOST_BIDX 0x00000088
328 #define BNX2_L2CTX_EST_NBD 0x00000088
329 #define BNX2_L2CTX_CMD_TYPE 0x00000088
330 #define BNX2_L2CTX_CMD_TYPE_TYPE (0xf<<24)
331 #define BNX2_L2CTX_CMD_TYPE_TYPE_L2 (0<<24)
334 #define BNX2_L2CTX_TX_HOST_BSEQ 0x00000090
335 #define BNX2_L2CTX_TSCH_BSEQ 0x00000094
336 #define BNX2_L2CTX_TBDR_BSEQ 0x00000098
337 #define BNX2_L2CTX_TBDR_BOFF 0x0000009c
338 #define BNX2_L2CTX_TBDR_BIDX 0x0000009c
339 #define BNX2_L2CTX_TBDR_BHADDR_HI 0x000000a0
340 #define BNX2_L2CTX_TBDR_BHADDR_LO 0x000000a4
341 #define BNX2_L2CTX_TXP_BOFF 0x000000a8
342 #define BNX2_L2CTX_TXP_BIDX 0x000000a8
343 #define BNX2_L2CTX_TXP_BSEQ 0x000000ac
345 #define BNX2_L2CTX_TYPE_XI 0x00000080
346 #define BNX2_L2CTX_CMD_TYPE_XI 0x00000240
347 #define BNX2_L2CTX_TBDR_BHADDR_HI_XI 0x00000258
348 #define BNX2_L2CTX_TBDR_BHADDR_LO_XI 0x0000025c
353 #define BNX2_L2CTX_BD_PRE_READ 0x00000000
354 #define BNX2_L2CTX_CTX_SIZE 0x00000000
355 #define BNX2_L2CTX_CTX_TYPE 0x00000000
356 #define BNX2_L2CTX_FLOW_CTRL_ENABLE 0x000000ff
357 #define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
358 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
359 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
362 #define BNX2_L2CTX_HOST_BDIDX 0x00000004
366 (((sb_id) > 0) ? (((sb_id) + 7) << BNX2_L2CTX_L5_STATUSB_NUM_SHIFT) : 0)
368 (((sb_id) > 0) ? (((sb_id) + 7) << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT) : 0)
369 #define BNX2_L2CTX_HOST_BSEQ 0x00000008
370 #define BNX2_L2CTX_NX_BSEQ 0x0000000c
371 #define BNX2_L2CTX_NX_BDHADDR_HI 0x00000010
372 #define BNX2_L2CTX_NX_BDHADDR_LO 0x00000014
373 #define BNX2_L2CTX_NX_BDIDX 0x00000018
375 #define BNX2_L2CTX_HOST_PG_BDIDX 0x00000044
376 #define BNX2_L2CTX_PG_BUF_SIZE 0x00000048
377 #define BNX2_L2CTX_RBDC_KEY 0x0000004c
378 #define BNX2_L2CTX_RBDC_JUMBO_KEY 0x3ffe
379 #define BNX2_L2CTX_NX_PG_BDHADDR_HI 0x00000050
380 #define BNX2_L2CTX_NX_PG_BDHADDR_LO 0x00000054
386 #define BNX2_PCICFG_MSI_CONTROL 0x00000058
389 #define BNX2_PCICFG_MISC_CONFIG 0x00000068
401 #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16)
402 #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24)
403 #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28)
405 #define BNX2_PCICFG_MISC_STATUS 0x0000006c
406 #define BNX2_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0)
410 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4)
411 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4)
417 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070
418 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
419 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
420 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
421 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
422 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
423 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
424 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
425 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
426 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
427 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
430 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
431 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
436 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
437 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
446 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
448 #define BNX2_PCICFG_REG_WINDOW_ADDRESS 0x00000078
449 #define BNX2_PCICFG_REG_WINDOW_ADDRESS_VAL (0xfffffL<<2)
451 #define BNX2_PCICFG_REG_WINDOW 0x00000080
452 #define BNX2_PCICFG_INT_ACK_CMD 0x00000084
453 #define BNX2_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0)
457 #define BNX2_PCICFG_INT_ACK_CMD_INTERRUPT_NUM (0xfL<<24)
460 #define BNX2_PCICFG_STATUS_BIT_SET_CMD 0x00000088
461 #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c
462 #define BNX2_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090
463 #define BNX2_PCICFG_MAILBOX_QUEUE_DATA 0x00000094
465 #define BNX2_PCICFG_DEVICE_CONTROL 0x000000b4
470 * offset: 0x400
472 #define BNX2_PCI_GRC_WINDOW_ADDR 0x00000400
473 #define BNX2_PCI_GRC_WINDOW_ADDR_VALUE (0x1ffL<<13)
476 #define BNX2_PCI_GRC_WINDOW2_BASE 0xc000
477 #define BNX2_PCI_GRC_WINDOW3_BASE 0xe000
479 #define BNX2_PCI_CONFIG_1 0x00000404
480 #define BNX2_PCI_CONFIG_1_RESERVED0 (0xffL<<0)
481 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8)
482 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8)
490 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11)
491 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11)
499 #define BNX2_PCI_CONFIG_1_RESERVED1 (0x3ffffL<<14)
501 #define BNX2_PCI_CONFIG_2 0x00000408
502 #define BNX2_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
503 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
504 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
505 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
506 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
507 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
508 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
509 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
510 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
511 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
512 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
513 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
514 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
515 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
516 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
517 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
518 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
523 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
524 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
540 #define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16)
541 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21)
542 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21)
549 #define BNX2_PCI_CONFIG_2_RESERVED0 (0x3fL<<26)
551 #define BNX2_PCI_CONFIG_2_RESERVED0_XI (0x7fffL<<17)
553 #define BNX2_PCI_CONFIG_3 0x0000040c
554 #define BNX2_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
555 #define BNX2_PCI_CONFIG_3_REG_STICKY_BYTE (0xffL<<8)
559 #define BNX2_PCI_CONFIG_3_PM_STATE (0x3L<<27)
563 #define BNX2_PCI_PM_DATA_A 0x00000410
564 #define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0)
565 #define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8)
566 #define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16)
567 #define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24)
569 #define BNX2_PCI_PM_DATA_B 0x00000414
570 #define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0)
571 #define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8)
572 #define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16)
573 #define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24)
575 #define BNX2_PCI_SWAP_DIAG0 0x00000418
576 #define BNX2_PCI_SWAP_DIAG1 0x0000041c
577 #define BNX2_PCI_EXP_ROM_ADDR 0x00000420
578 #define BNX2_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2)
581 #define BNX2_PCI_EXP_ROM_DATA 0x00000424
582 #define BNX2_PCI_VPD_INTF 0x00000428
583 #define BNX2_PCI_VPD_INTF_INTF_REQ (1L<<0)
585 #define BNX2_PCI_VPD_ADDR_FLAG 0x0000042c
586 #define BNX2_PCI_VPD_ADDR_FLAG_MSK 0x0000ffff
587 #define BNX2_PCI_VPD_ADDR_FLAG_SL 0L
588 #define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fffL<<2)
591 #define BNX2_PCI_VPD_DATA 0x00000430
592 #define BNX2_PCI_ID_VAL1 0x00000434
593 #define BNX2_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0)
594 #define BNX2_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16)
596 #define BNX2_PCI_ID_VAL2 0x00000438
597 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0)
598 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16)
600 #define BNX2_PCI_ID_VAL3 0x0000043c
601 #define BNX2_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0)
602 #define BNX2_PCI_ID_VAL3_REVISION_ID (0xffL<<24)
604 #define BNX2_PCI_ID_VAL4 0x00000440
605 #define BNX2_PCI_ID_VAL4_CAP_ENA (0xfL<<0)
606 #define BNX2_PCI_ID_VAL4_CAP_ENA_0 (0L<<0)
607 #define BNX2_PCI_ID_VAL4_CAP_ENA_1 (1L<<0)
608 #define BNX2_PCI_ID_VAL4_CAP_ENA_2 (2L<<0)
609 #define BNX2_PCI_ID_VAL4_CAP_ENA_3 (3L<<0)
610 #define BNX2_PCI_ID_VAL4_CAP_ENA_4 (4L<<0)
611 #define BNX2_PCI_ID_VAL4_CAP_ENA_5 (5L<<0)
612 #define BNX2_PCI_ID_VAL4_CAP_ENA_6 (6L<<0)
613 #define BNX2_PCI_ID_VAL4_CAP_ENA_7 (7L<<0)
614 #define BNX2_PCI_ID_VAL4_CAP_ENA_8 (8L<<0)
615 #define BNX2_PCI_ID_VAL4_CAP_ENA_9 (9L<<0)
616 #define BNX2_PCI_ID_VAL4_CAP_ENA_10 (10L<<0)
617 #define BNX2_PCI_ID_VAL4_CAP_ENA_11 (11L<<0)
618 #define BNX2_PCI_ID_VAL4_CAP_ENA_12 (12L<<0)
619 #define BNX2_PCI_ID_VAL4_CAP_ENA_13 (13L<<0)
620 #define BNX2_PCI_ID_VAL4_CAP_ENA_14 (14L<<0)
621 #define BNX2_PCI_ID_VAL4_CAP_ENA_15 (15L<<0)
622 #define BNX2_PCI_ID_VAL4_RESERVED0 (0x3L<<4)
623 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6)
624 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6)
629 #define BNX2_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9)
630 #define BNX2_PCI_ID_VAL4_MULTI_MSG_CAP (0x7L<<12)
634 #define BNX2_PCI_ID_VAL4_RESERVED2 (0x7L<<18)
635 #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21 (0x3L<<21)
636 #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B21 (0x3L<<23)
638 #define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10 (0x3L<<26)
640 #define BNX2_PCI_ID_VAL4_RESERVED3 (0x7L<<29)
641 #define BNX2_PCI_ID_VAL4_RESERVED3_XI (0xffffL<<16)
643 #define BNX2_PCI_ID_VAL5 0x00000444
644 #define BNX2_PCI_ID_VAL5_D1_SUPPORT (1L<<0)
650 #define BNX2_PCI_ID_VAL5_RESERVED0_TE (0x3ffffffL<<6)
651 #define BNX2_PCI_ID_VAL5_PM_VERSION_XI (0x7L<<6)
653 #define BNX2_PCI_ID_VAL5_RESERVED0_XI (0x3fffffL<<10)
655 #define BNX2_PCI_PCIX_EXTENDED_STATUS 0x00000448
658 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16)
659 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24)
661 #define BNX2_PCI_ID_VAL6 0x0000044c
662 #define BNX2_PCI_ID_VAL6_MAX_LAT (0xffL<<0)
663 #define BNX2_PCI_ID_VAL6_MIN_GNT (0xffL<<8)
664 #define BNX2_PCI_ID_VAL6_BIST (0xffL<<16)
665 #define BNX2_PCI_ID_VAL6_RESERVED0 (0xffL<<24)
667 #define BNX2_PCI_MSI_DATA 0x00000450
668 #define BNX2_PCI_MSI_DATA_MSI_DATA (0xffffL<<0)
670 #define BNX2_PCI_MSI_ADDR_H 0x00000454
671 #define BNX2_PCI_MSI_ADDR_L 0x00000458
672 #define BNX2_PCI_MSI_ADDR_L_VAL (0x3fffffffL<<2)
674 #define BNX2_PCI_CFG_ACCESS_CMD 0x0000045c
675 #define BNX2_PCI_CFG_ACCESS_CMD_ADR (0x3fL<<2)
677 #define BNX2_PCI_CFG_ACCESS_CMD_WR_REQ (0xfL<<28)
679 #define BNX2_PCI_CFG_ACCESS_DATA 0x00000460
680 #define BNX2_PCI_MSI_MASK 0x00000464
681 #define BNX2_PCI_MSI_MASK_MSI_MASK (0xffffffffL<<0)
683 #define BNX2_PCI_MSI_PEND 0x00000468
684 #define BNX2_PCI_MSI_PEND_MSI_PEND (0xffffffffL<<0)
686 #define BNX2_PCI_PM_DATA_C 0x0000046c
687 #define BNX2_PCI_PM_DATA_C_PM_DATA_8_PRG (0xffL<<0)
688 #define BNX2_PCI_PM_DATA_C_RESERVED0 (0xffffffL<<8)
690 #define BNX2_PCI_MSIX_CONTROL 0x000004c0
691 #define BNX2_PCI_MSIX_CONTROL_MSIX_TBL_SIZ (0x7ffL<<0)
692 #define BNX2_PCI_MSIX_CONTROL_RESERVED0 (0x1fffffL<<11)
694 #define BNX2_PCI_MSIX_TBL_OFF_BIR 0x000004c4
695 #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR (0x7L<<0)
696 #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF (0x1fffffffL<<3)
698 #define BNX2_PCI_MSIX_PBA_OFF_BIT 0x000004c8
699 #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR (0x7L<<0)
700 #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF (0x1fffffffL<<3)
702 #define BNX2_PCI_PCIE_CAPABILITY 0x000004d0
703 #define BNX2_PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM (0x1fL<<0)
706 #define BNX2_PCI_DEVICE_CAPABILITY 0x000004d4
707 #define BNX2_PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED (0x7L<<0)
709 #define BNX2_PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY (0x7L<<6)
710 #define BNX2_PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY (0x7L<<9)
713 #define BNX2_PCI_LINK_CAPABILITY 0x000004dc
714 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED (0xfL<<0)
715 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001 (1L<<0)
716 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010 (1L<<0)
717 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_WIDTH (0x1fL<<4)
719 #define BNX2_PCI_LINK_CAPABILITY_ASPM_SUPPORT (0x3L<<10)
720 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT (0x7L<<12)
723 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT (0x7L<<15)
726 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT (0x7L<<18)
729 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT (0x7L<<21)
732 #define BNX2_PCI_LINK_CAPABILITY_PORT_NUM (0xffL<<24)
734 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2 0x000004e4
735 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP (0xfL<<0)
737 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED (0x7ffffffL<<5)
739 #define BNX2_PCI_PCIE_LINK_CAPABILITY_2 0x000004e8
740 #define BNX2_PCI_PCIE_LINK_CAPABILITY_2_RESERVED (0xffffffffL<<0)
742 #define BNX2_PCI_GRC_WINDOW1_ADDR 0x00000610
743 #define BNX2_PCI_GRC_WINDOW1_ADDR_VALUE (0x1ffL<<13)
745 #define BNX2_PCI_GRC_WINDOW2_ADDR 0x00000614
746 #define BNX2_PCI_GRC_WINDOW2_ADDR_VALUE (0x1ffL<<13)
748 #define BNX2_PCI_GRC_WINDOW3_ADDR 0x00000618
749 #define BNX2_PCI_GRC_WINDOW3_ADDR_VALUE (0x1ffL<<13)
751 #define BNX2_MSIX_TABLE_ADDR 0x318000
752 #define BNX2_MSIX_PBA_ADDR 0x31c000
756 * offset: 0x800
758 #define BNX2_MISC_COMMAND 0x00000800
759 #define BNX2_MISC_COMMAND_ENABLE_ALL (1L<<0)
767 #define BNX2_MISC_COMMAND_CS16_ERR_LOC (0xfL<<12)
768 #define BNX2_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16)
776 #define BNX2_MISC_CFG 0x00000804
777 #define BNX2_MISC_CFG_GRC_TMOUT (1L<<0)
778 #define BNX2_MISC_CFG_NVM_WR_EN (0x3L<<1)
779 #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
788 #define BNX2_MISC_CFG_LEDMODE (0x7L<<8)
789 #define BNX2_MISC_CFG_LEDMODE_MAC (0L<<8)
799 #define BNX2_MISC_CFG_LEDMODE_XI (0xfL<<8)
800 #define BNX2_MISC_CFG_LEDMODE_MAC_XI (0L<<8)
819 #define BNX2_MISC_ID 0x00000808
820 #define BNX2_MISC_ID_BOND_ID (0xfL<<0)
821 #define BNX2_MISC_ID_BOND_ID_X (0L<<0)
822 #define BNX2_MISC_ID_BOND_ID_C (3L<<0)
823 #define BNX2_MISC_ID_BOND_ID_S (12L<<0)
824 #define BNX2_MISC_ID_CHIP_METAL (0xffL<<4)
825 #define BNX2_MISC_ID_CHIP_REV (0xfL<<12)
826 #define BNX2_MISC_ID_CHIP_NUM (0xffffL<<16)
828 #define BNX2_MISC_ENABLE_STATUS_BITS 0x0000080c
829 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0)
858 #define BNX2_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
860 #define BNX2_MISC_ENABLE_SET_BITS 0x00000810
861 #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
890 #define BNX2_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
892 #define BNX2_MISC_ENABLE_CLR_BITS 0x00000814
893 #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
922 #define BNX2_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
924 #define BNX2_MISC_CLOCK_CONTROL_BITS 0x00000818
925 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
926 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
927 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
928 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
929 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
930 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
931 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
932 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
933 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
934 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
937 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
938 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
942 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI (0x7L<<8)
944 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
945 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
950 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI (0xfL<<12)
955 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_TE (0xfffL<<20)
957 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI (0x3fL<<18)
958 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI (0x7L<<24)
960 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI (0xfL<<28)
962 #define BNX2_MISC_SPIO 0x0000081c
963 #define BNX2_MISC_SPIO_VALUE (0xffL<<0)
964 #define BNX2_MISC_SPIO_SET (0xffL<<8)
965 #define BNX2_MISC_SPIO_CLR (0xffL<<16)
966 #define BNX2_MISC_SPIO_FLOAT (0xffL<<24)
968 #define BNX2_MISC_SPIO_INT 0x00000820
969 #define BNX2_MISC_SPIO_INT_INT_STATE_TE (0xfL<<0)
970 #define BNX2_MISC_SPIO_INT_OLD_VALUE_TE (0xfL<<8)
971 #define BNX2_MISC_SPIO_INT_OLD_SET_TE (0xfL<<16)
972 #define BNX2_MISC_SPIO_INT_OLD_CLR_TE (0xfL<<24)
973 #define BNX2_MISC_SPIO_INT_INT_STATE_XI (0xffL<<0)
974 #define BNX2_MISC_SPIO_INT_OLD_VALUE_XI (0xffL<<8)
975 #define BNX2_MISC_SPIO_INT_OLD_SET_XI (0xffL<<16)
976 #define BNX2_MISC_SPIO_INT_OLD_CLR_XI (0xffL<<24)
978 #define BNX2_MISC_CONFIG_LFSR 0x00000824
979 #define BNX2_MISC_CONFIG_LFSR_DIV (0xffffL<<0)
981 #define BNX2_MISC_LFSR_MASK_BITS 0x00000828
982 #define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1011 #define BNX2_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
1013 #define BNX2_MISC_ARB_REQ0 0x0000082c
1014 #define BNX2_MISC_ARB_REQ1 0x00000830
1015 #define BNX2_MISC_ARB_REQ2 0x00000834
1016 #define BNX2_MISC_ARB_REQ3 0x00000838
1017 #define BNX2_MISC_ARB_REQ4 0x0000083c
1018 #define BNX2_MISC_ARB_FREE0 0x00000840
1019 #define BNX2_MISC_ARB_FREE1 0x00000844
1020 #define BNX2_MISC_ARB_FREE2 0x00000848
1021 #define BNX2_MISC_ARB_FREE3 0x0000084c
1022 #define BNX2_MISC_ARB_FREE4 0x00000850
1023 #define BNX2_MISC_ARB_REQ_STATUS0 0x00000854
1024 #define BNX2_MISC_ARB_REQ_STATUS1 0x00000858
1025 #define BNX2_MISC_ARB_REQ_STATUS2 0x0000085c
1026 #define BNX2_MISC_ARB_REQ_STATUS3 0x00000860
1027 #define BNX2_MISC_ARB_REQ_STATUS4 0x00000864
1028 #define BNX2_MISC_ARB_GNT0 0x00000868
1029 #define BNX2_MISC_ARB_GNT0_0 (0x7L<<0)
1030 #define BNX2_MISC_ARB_GNT0_1 (0x7L<<4)
1031 #define BNX2_MISC_ARB_GNT0_2 (0x7L<<8)
1032 #define BNX2_MISC_ARB_GNT0_3 (0x7L<<12)
1033 #define BNX2_MISC_ARB_GNT0_4 (0x7L<<16)
1034 #define BNX2_MISC_ARB_GNT0_5 (0x7L<<20)
1035 #define BNX2_MISC_ARB_GNT0_6 (0x7L<<24)
1036 #define BNX2_MISC_ARB_GNT0_7 (0x7L<<28)
1038 #define BNX2_MISC_ARB_GNT1 0x0000086c
1039 #define BNX2_MISC_ARB_GNT1_8 (0x7L<<0)
1040 #define BNX2_MISC_ARB_GNT1_9 (0x7L<<4)
1041 #define BNX2_MISC_ARB_GNT1_10 (0x7L<<8)
1042 #define BNX2_MISC_ARB_GNT1_11 (0x7L<<12)
1043 #define BNX2_MISC_ARB_GNT1_12 (0x7L<<16)
1044 #define BNX2_MISC_ARB_GNT1_13 (0x7L<<20)
1045 #define BNX2_MISC_ARB_GNT1_14 (0x7L<<24)
1046 #define BNX2_MISC_ARB_GNT1_15 (0x7L<<28)
1048 #define BNX2_MISC_ARB_GNT2 0x00000870
1049 #define BNX2_MISC_ARB_GNT2_16 (0x7L<<0)
1050 #define BNX2_MISC_ARB_GNT2_17 (0x7L<<4)
1051 #define BNX2_MISC_ARB_GNT2_18 (0x7L<<8)
1052 #define BNX2_MISC_ARB_GNT2_19 (0x7L<<12)
1053 #define BNX2_MISC_ARB_GNT2_20 (0x7L<<16)
1054 #define BNX2_MISC_ARB_GNT2_21 (0x7L<<20)
1055 #define BNX2_MISC_ARB_GNT2_22 (0x7L<<24)
1056 #define BNX2_MISC_ARB_GNT2_23 (0x7L<<28)
1058 #define BNX2_MISC_ARB_GNT3 0x00000874
1059 #define BNX2_MISC_ARB_GNT3_24 (0x7L<<0)
1060 #define BNX2_MISC_ARB_GNT3_25 (0x7L<<4)
1061 #define BNX2_MISC_ARB_GNT3_26 (0x7L<<8)
1062 #define BNX2_MISC_ARB_GNT3_27 (0x7L<<12)
1063 #define BNX2_MISC_ARB_GNT3_28 (0x7L<<16)
1064 #define BNX2_MISC_ARB_GNT3_29 (0x7L<<20)
1065 #define BNX2_MISC_ARB_GNT3_30 (0x7L<<24)
1066 #define BNX2_MISC_ARB_GNT3_31 (0x7L<<28)
1068 #define BNX2_MISC_RESERVED1 0x00000878
1069 #define BNX2_MISC_RESERVED1_MISC_RESERVED1_VALUE (0x3fL<<0)
1071 #define BNX2_MISC_RESERVED2 0x0000087c
1072 #define BNX2_MISC_RESERVED2_PCIE_DIS (1L<<0)
1075 #define BNX2_MISC_SM_ASF_CONTROL 0x00000880
1076 #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
1086 #define BNX2_MISC_SM_ASF_CONTROL_RES (0x3L<<10)
1091 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x7fL<<16)
1092 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x7fL<<23)
1096 #define BNX2_MISC_SMB_IN 0x00000884
1097 #define BNX2_MISC_SMB_IN_DAT_IN (0xffL<<0)
1101 #define BNX2_MISC_SMB_IN_STATUS (0x7L<<11)
1102 #define BNX2_MISC_SMB_IN_STATUS_OK (0x0L<<11)
1103 #define BNX2_MISC_SMB_IN_STATUS_PEC (0x1L<<11)
1104 #define BNX2_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11)
1105 #define BNX2_MISC_SMB_IN_STATUS_STOP (0x3L<<11)
1106 #define BNX2_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11)
1108 #define BNX2_MISC_SMB_OUT 0x00000888
1109 #define BNX2_MISC_SMB_OUT_DAT_OUT (0xffL<<0)
1116 #define BNX2_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14)
1117 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20)
1118 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
1126 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20)
1133 #define BNX2_MISC_SMB_WATCHDOG 0x0000088c
1134 #define BNX2_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0)
1136 #define BNX2_MISC_SMB_HEARTBEAT 0x00000890
1137 #define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0)
1139 #define BNX2_MISC_SMB_POLL_ASF 0x00000894
1140 #define BNX2_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0)
1142 #define BNX2_MISC_SMB_POLL_LEGACY 0x00000898
1143 #define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0)
1145 #define BNX2_MISC_SMB_RETRAN 0x0000089c
1146 #define BNX2_MISC_SMB_RETRAN_RETRAN (0xffL<<0)
1148 #define BNX2_MISC_SMB_TIMESTAMP 0x000008a0
1149 #define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0)
1151 #define BNX2_MISC_PERR_ENA0 0x000008a4
1152 #define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0)
1184 #define BNX2_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI (1L<<0)
1217 #define BNX2_MISC_PERR_ENA1 0x000008a8
1218 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
1250 #define BNX2_MISC_PERR_ENA1_RBDC_PERR_EN_XI (1L<<0)
1280 #define BNX2_MISC_PERR_ENA2 0x000008ac
1281 #define BNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
1290 #define BNX2_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI (1L<<0)
1298 #define BNX2_MISC_DEBUG_VECTOR_SEL 0x000008b0
1299 #define BNX2_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0)
1300 #define BNX2_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12)
1301 #define BNX2_MISC_DEBUG_VECTOR_SEL_1_XI (0xfffL<<15)
1303 #define BNX2_MISC_VREG_CONTROL 0x000008b4
1304 #define BNX2_MISC_VREG_CONTROL_1_2 (0xfL<<0)
1305 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_XI (0xfL<<0)
1306 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI (0L<<0)
1307 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI (1L<<0)
1308 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI (2L<<0)
1309 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI (3L<<0)
1310 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI (4L<<0)
1311 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI (5L<<0)
1312 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI (6L<<0)
1313 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI (7L<<0)
1314 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI (8L<<0)
1315 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI (9L<<0)
1316 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI (10L<<0)
1317 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI (11L<<0)
1318 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI (12L<<0)
1319 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI (13L<<0)
1320 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI (14L<<0)
1321 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI (15L<<0)
1322 #define BNX2_MISC_VREG_CONTROL_2_5 (0xfL<<4)
1323 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS14 (0L<<4)
1339 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT (0xfL<<8)
1340 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14 (0L<<8)
1357 #define BNX2_MISC_FINAL_CLK_CTL_VAL 0x000008b8
1358 #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6)
1360 #define BNX2_MISC_GP_HW_CTL0 0x000008bc
1361 #define BNX2_MISC_GP_HW_CTL0_TX_DRIVE (1L<<0)
1368 #define BNX2_MISC_GP_HW_CTL0_RESERVED1_XI (0x7L<<4)
1373 #define BNX2_MISC_GP_HW_CTL0_RESERVED2_XI (0x7L<<8)
1379 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI (0xfL<<16)
1380 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA (0L<<16)
1388 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT (0x3L<<22)
1389 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P (0L<<22)
1393 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT (0x3L<<24)
1394 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P (0L<<24)
1398 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ (0x3L<<26)
1399 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA (0L<<26)
1403 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ (0x3L<<28)
1404 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA (0L<<28)
1408 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ (0x3L<<30)
1409 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57 (0L<<30)
1414 #define BNX2_MISC_GP_HW_CTL1 0x000008c0
1415 #define BNX2_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE (1L<<0)
1419 #define BNX2_MISC_GP_HW_CTL1_RESERVED_SOFT_XI (0xffffL<<0)
1420 #define BNX2_MISC_GP_HW_CTL1_RESERVED_HARD_XI (0xffffL<<16)
1422 #define BNX2_MISC_NEW_HW_CTL 0x000008c4
1423 #define BNX2_MISC_NEW_HW_CTL_MAIN_POR_BYPASS (1L<<0)
1427 #define BNX2_MISC_NEW_HW_CTL_RESERVED_SHARED (0xfffL<<4)
1428 #define BNX2_MISC_NEW_HW_CTL_RESERVED_SPLIT (0xffffL<<16)
1430 #define BNX2_MISC_NEW_CORE_CTL 0x000008c8
1431 #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0)
1434 #define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2)
1435 #define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16)
1437 #define BNX2_MISC_ECO_HW_CTL 0x000008cc
1438 #define BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN (1L<<0)
1439 #define BNX2_MISC_ECO_HW_CTL_RESERVED_SOFT (0x7fffL<<1)
1440 #define BNX2_MISC_ECO_HW_CTL_RESERVED_HARD (0xffffL<<16)
1442 #define BNX2_MISC_ECO_CORE_CTL 0x000008d0
1443 #define BNX2_MISC_ECO_CORE_CTL_RESERVED_SOFT (0xffffL<<0)
1444 #define BNX2_MISC_ECO_CORE_CTL_RESERVED_HARD (0xffffL<<16)
1446 #define BNX2_MISC_PPIO 0x000008d4
1447 #define BNX2_MISC_PPIO_VALUE (0xfL<<0)
1448 #define BNX2_MISC_PPIO_SET (0xfL<<8)
1449 #define BNX2_MISC_PPIO_CLR (0xfL<<16)
1450 #define BNX2_MISC_PPIO_FLOAT (0xfL<<24)
1452 #define BNX2_MISC_PPIO_INT 0x000008d8
1453 #define BNX2_MISC_PPIO_INT_INT_STATE (0xfL<<0)
1454 #define BNX2_MISC_PPIO_INT_OLD_VALUE (0xfL<<8)
1455 #define BNX2_MISC_PPIO_INT_OLD_SET (0xfL<<16)
1456 #define BNX2_MISC_PPIO_INT_OLD_CLR (0xfL<<24)
1458 #define BNX2_MISC_RESET_NUMS 0x000008dc
1459 #define BNX2_MISC_RESET_NUMS_NUM_HARD_RESETS (0x7L<<0)
1460 #define BNX2_MISC_RESET_NUMS_NUM_PCIE_RESETS (0x7L<<4)
1461 #define BNX2_MISC_RESET_NUMS_NUM_PERSTB_RESETS (0x7L<<8)
1462 #define BNX2_MISC_RESET_NUMS_NUM_CMN_RESETS (0x7L<<12)
1463 #define BNX2_MISC_RESET_NUMS_NUM_PORT_RESETS (0x7L<<16)
1465 #define BNX2_MISC_CS16_ERR 0x000008e0
1466 #define BNX2_MISC_CS16_ERR_ENA_PCI (1L<<0)
1485 #define BNX2_MISC_SPIO_EVENT 0x000008e4
1486 #define BNX2_MISC_SPIO_EVENT_ENABLE (0xffL<<0)
1488 #define BNX2_MISC_PPIO_EVENT 0x000008e8
1489 #define BNX2_MISC_PPIO_EVENT_ENABLE (0xfL<<0)
1491 #define BNX2_MISC_DUAL_MEDIA_CTRL 0x000008ec
1492 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID (0xffL<<0)
1493 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_X (0L<<0)
1494 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C (3L<<0)
1495 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S (12L<<0)
1496 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP (0x7L<<8)
1507 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL (0x7L<<21)
1510 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ (0xfL<<26)
1516 #define BNX2_MISC_OTP_CMD1 0x000008f0
1517 #define BNX2_MISC_OTP_CMD1_FMODE (0x7L<<0)
1518 #define BNX2_MISC_OTP_CMD1_FMODE_IDLE (0L<<0)
1519 #define BNX2_MISC_OTP_CMD1_FMODE_WRITE (1L<<0)
1520 #define BNX2_MISC_OTP_CMD1_FMODE_INIT (2L<<0)
1521 #define BNX2_MISC_OTP_CMD1_FMODE_SET (3L<<0)
1522 #define BNX2_MISC_OTP_CMD1_FMODE_RST (4L<<0)
1523 #define BNX2_MISC_OTP_CMD1_FMODE_VERIFY (5L<<0)
1524 #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED0 (6L<<0)
1525 #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED1 (7L<<0)
1529 #define BNX2_MISC_OTP_CMD1_PCOUNT (0x7L<<16)
1531 #define BNX2_MISC_OTP_CMD1_VSEL (0xfL<<20)
1532 #define BNX2_MISC_OTP_CMD1_TM (0x7L<<27)
1536 #define BNX2_MISC_OTP_CMD2 0x000008f4
1537 #define BNX2_MISC_OTP_CMD2_OTP_ROM_ADDR (0x3ffL<<0)
1538 #define BNX2_MISC_OTP_CMD2_DOSEL (0x7fL<<16)
1539 #define BNX2_MISC_OTP_CMD2_DOSEL_0 (0L<<16)
1543 #define BNX2_MISC_OTP_STATUS 0x000008f8
1544 #define BNX2_MISC_OTP_STATUS_DATA (0xffL<<0)
1550 #define BNX2_MISC_OTP_SHIFT1_CMD 0x000008fc
1551 #define BNX2_MISC_OTP_SHIFT1_CMD_RESET_MODE_N (1L<<0)
1555 #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT (0x1fL<<8)
1557 #define BNX2_MISC_OTP_SHIFT1_DATA 0x00000900
1558 #define BNX2_MISC_OTP_SHIFT2_CMD 0x00000904
1559 #define BNX2_MISC_OTP_SHIFT2_CMD_RESET_MODE_N (1L<<0)
1563 #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT (0x1fL<<8)
1565 #define BNX2_MISC_OTP_SHIFT2_DATA 0x00000908
1566 #define BNX2_MISC_BIST_CS0 0x0000090c
1567 #define BNX2_MISC_BIST_CS0_MBIST_EN (1L<<0)
1568 #define BNX2_MISC_BIST_CS0_BIST_SETUP (0x3L<<1)
1574 #define BNX2_MISC_BIST_MEMSTATUS0 0x00000910
1575 #define BNX2_MISC_BIST_CS1 0x00000914
1576 #define BNX2_MISC_BIST_CS1_MBIST_EN (1L<<0)
1577 #define BNX2_MISC_BIST_CS1_BIST_SETUP (0x3L<<1)
1582 #define BNX2_MISC_BIST_MEMSTATUS1 0x00000918
1583 #define BNX2_MISC_BIST_CS2 0x0000091c
1584 #define BNX2_MISC_BIST_CS2_MBIST_EN (1L<<0)
1585 #define BNX2_MISC_BIST_CS2_BIST_SETUP (0x3L<<1)
1590 #define BNX2_MISC_BIST_MEMSTATUS2 0x00000920
1591 #define BNX2_MISC_BIST_CS3 0x00000924
1592 #define BNX2_MISC_BIST_CS3_MBIST_EN (1L<<0)
1593 #define BNX2_MISC_BIST_CS3_BIST_SETUP (0x3L<<1)
1598 #define BNX2_MISC_BIST_MEMSTATUS3 0x00000928
1599 #define BNX2_MISC_BIST_CS4 0x0000092c
1600 #define BNX2_MISC_BIST_CS4_MBIST_EN (1L<<0)
1601 #define BNX2_MISC_BIST_CS4_BIST_SETUP (0x3L<<1)
1606 #define BNX2_MISC_BIST_MEMSTATUS4 0x00000930
1607 #define BNX2_MISC_BIST_CS5 0x00000934
1608 #define BNX2_MISC_BIST_CS5_MBIST_EN (1L<<0)
1609 #define BNX2_MISC_BIST_CS5_BIST_SETUP (0x3L<<1)
1614 #define BNX2_MISC_BIST_MEMSTATUS5 0x00000938
1615 #define BNX2_MISC_MEM_TM0 0x0000093c
1616 #define BNX2_MISC_MEM_TM0_PCIE_REPLAY_TM (0xfL<<0)
1617 #define BNX2_MISC_MEM_TM0_MCP_SCPAD (0xfL<<8)
1618 #define BNX2_MISC_MEM_TM0_UMP_TM (0xffL<<16)
1619 #define BNX2_MISC_MEM_TM0_HB_MEM_TM (0xfL<<24)
1621 #define BNX2_MISC_USPLL_CTRL 0x00000940
1622 #define BNX2_MISC_USPLL_CTRL_PH_DET_DIS (1L<<0)
1624 #define BNX2_MISC_USPLL_CTRL_LCPX (0x3fL<<2)
1625 #define BNX2_MISC_USPLL_CTRL_RX (0x3L<<8)
1627 #define BNX2_MISC_USPLL_CTRL_VCO_MG (0x3L<<11)
1628 #define BNX2_MISC_USPLL_CTRL_KVCO_XF (0x7L<<13)
1629 #define BNX2_MISC_USPLL_CTRL_KVCO_XS (0x7L<<16)
1631 #define BNX2_MISC_USPLL_CTRL_TESTD_SEL (0x7L<<20)
1633 #define BNX2_MISC_USPLL_CTRL_TESTA_SEL (0x3L<<24)
1639 #define BNX2_MISC_PERR_STATUS0 0x00000944
1640 #define BNX2_MISC_PERR_STATUS0_COM_DMAE_PERR (1L<<0)
1673 #define BNX2_MISC_PERR_STATUS1 0x00000948
1674 #define BNX2_MISC_PERR_STATUS1_RBDC_PERR (1L<<0)
1704 #define BNX2_MISC_PERR_STATUS2 0x0000094c
1705 #define BNX2_MISC_PERR_STATUS2_TGT_FIFO_PERR (1L<<0)
1713 #define BNX2_MISC_LCPLL_CTRL0 0x00000950
1714 #define BNX2_MISC_LCPLL_CTRL0_OAC (0x7L<<0)
1715 #define BNX2_MISC_LCPLL_CTRL0_OAC_NEGTWENTY (0L<<0)
1716 #define BNX2_MISC_LCPLL_CTRL0_OAC_ZERO (1L<<0)
1717 #define BNX2_MISC_LCPLL_CTRL0_OAC_TWENTY (3L<<0)
1718 #define BNX2_MISC_LCPLL_CTRL0_OAC_FORTY (7L<<0)
1719 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL (0x7L<<3)
1720 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_360 (0L<<3)
1724 #define BNX2_MISC_LCPLL_CTRL0_BIAS_CTRL (0x3L<<6)
1725 #define BNX2_MISC_LCPLL_CTRL0_PLL_OBSERVE (0x7L<<8)
1726 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL (0x3L<<11)
1727 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_0 (0L<<11)
1746 #define BNX2_MISC_LCPLL_CTRL1 0x00000954
1747 #define BNX2_MISC_LCPLL_CTRL1_CAPSELECTM (0x1fL<<0)
1752 #define BNX2_MISC_LCPLL_STATUS 0x00000958
1753 #define BNX2_MISC_LCPLL_STATUS_FREQDONE_SM (1L<<0)
1757 #define BNX2_MISC_LCPLL_STATUS_PLLSTATE (0x7L<<4)
1758 #define BNX2_MISC_LCPLL_STATUS_CAPSTATE (0x7L<<7)
1759 #define BNX2_MISC_LCPLL_STATUS_CAPSELECT (0x1fL<<10)
1761 #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0 (0L<<15)
1764 #define BNX2_MISC_OSCFUNDS_CTRL 0x0000095c
1766 #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF (0L<<5)
1768 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM (0x3L<<6)
1769 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0 (0L<<6)
1773 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ (0x3L<<8)
1774 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0 (0L<<8)
1778 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ (0x3L<<10)
1779 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0 (0L<<10)
1787 * offset: 0x6400
1789 #define BNX2_NVM_COMMAND 0x00006400
1790 #define BNX2_NVM_COMMAND_RST (1L<<0)
1805 #define BNX2_NVM_STATUS 0x00006404
1806 #define BNX2_NVM_STATUS_PI_FSM_STATE (0xfL<<0)
1807 #define BNX2_NVM_STATUS_EE_FSM_STATE (0xfL<<4)
1808 #define BNX2_NVM_STATUS_EQ_FSM_STATE (0xfL<<8)
1809 #define BNX2_NVM_STATUS_SPI_FSM_STATE_XI (0x1fL<<0)
1810 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI (0L<<0)
1811 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI (1L<<0)
1812 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI (2L<<0)
1813 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI (3L<<0)
1814 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI (4L<<0)
1815 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI (5L<<0)
1816 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI (6L<<0)
1817 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI (7L<<0)
1818 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI (8L<<0)
1819 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI (9L<<0)
1820 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI (10L<<0)
1821 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI (11L<<0)
1822 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI (12L<<0)
1823 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI (13L<<0)
1824 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI (14L<<0)
1825 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI (15L<<0)
1826 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI (16L<<0)
1827 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI (17L<<0)
1828 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI (18L<<0)
1829 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI (19L<<0)
1831 #define BNX2_NVM_WRITE 0x00006408
1832 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0)
1833 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
1834 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0)
1835 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0)
1836 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0)
1837 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0)
1838 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0)
1839 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0)
1840 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI_XI (1L<<0)
1841 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO_XI (2L<<0)
1842 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI (4L<<0)
1843 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI (8L<<0)
1845 #define BNX2_NVM_ADDR 0x0000640c
1846 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
1847 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
1848 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0)
1849 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0)
1850 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0)
1851 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0)
1852 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0)
1853 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0)
1854 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI_XI (1L<<0)
1855 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO_XI (2L<<0)
1856 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI (4L<<0)
1857 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI (8L<<0)
1859 #define BNX2_NVM_READ 0x00006410
1860 #define BNX2_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0)
1861 #define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
1862 #define BNX2_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0)
1863 #define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0)
1864 #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0)
1865 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0)
1866 #define BNX2_NVM_READ_NVM_READ_VALUE_SO (16L<<0)
1867 #define BNX2_NVM_READ_NVM_READ_VALUE_SI (32L<<0)
1868 #define BNX2_NVM_READ_NVM_READ_VALUE_SI_XI (1L<<0)
1869 #define BNX2_NVM_READ_NVM_READ_VALUE_SO_XI (2L<<0)
1870 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B_XI (4L<<0)
1871 #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK_XI (8L<<0)
1873 #define BNX2_NVM_CFG1 0x00006414
1874 #define BNX2_NVM_CFG1_FLASH_MODE (1L<<0)
1878 #define BNX2_NVM_CFG1_STATUS_BIT (0x7L<<4)
1879 #define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4)
1881 #define BNX2_NVM_CFG1_SPI_CLK_DIV (0xfL<<7)
1882 #define BNX2_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11)
1893 #define BNX2_NVM_CFG2 0x00006418
1894 #define BNX2_NVM_CFG2_ERASE_CMD (0xffL<<0)
1895 #define BNX2_NVM_CFG2_DUMMY (0xffL<<8)
1896 #define BNX2_NVM_CFG2_STATUS_CMD (0xffL<<16)
1897 #define BNX2_NVM_CFG2_READ_ID (0xffL<<24)
1899 #define BNX2_NVM_CFG3 0x0000641c
1900 #define BNX2_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0)
1901 #define BNX2_NVM_CFG3_WRITE_CMD (0xffL<<8)
1902 #define BNX2_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16)
1903 #define BNX2_NVM_CFG3_READ_CMD (0xffL<<24)
1905 #define BNX2_NVM_SW_ARB 0x00006420
1906 #define BNX2_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
1923 #define BNX2_NVM_ACCESS_ENABLE 0x00006424
1924 #define BNX2_NVM_ACCESS_ENABLE_EN (1L<<0)
1927 #define BNX2_NVM_WRITE1 0x00006428
1928 #define BNX2_NVM_WRITE1_WREN_CMD (0xffL<<0)
1929 #define BNX2_NVM_WRITE1_WRDI_CMD (0xffL<<8)
1930 #define BNX2_NVM_WRITE1_SR_DATA (0xffL<<16)
1932 #define BNX2_NVM_CFG4 0x0000642c
1933 #define BNX2_NVM_CFG4_FLASH_SIZE (0x7L<<0)
1934 #define BNX2_NVM_CFG4_FLASH_SIZE_1MBIT (0L<<0)
1935 #define BNX2_NVM_CFG4_FLASH_SIZE_2MBIT (1L<<0)
1936 #define BNX2_NVM_CFG4_FLASH_SIZE_4MBIT (2L<<0)
1937 #define BNX2_NVM_CFG4_FLASH_SIZE_8MBIT (3L<<0)
1938 #define BNX2_NVM_CFG4_FLASH_SIZE_16MBIT (4L<<0)
1939 #define BNX2_NVM_CFG4_FLASH_SIZE_32MBIT (5L<<0)
1940 #define BNX2_NVM_CFG4_FLASH_SIZE_64MBIT (6L<<0)
1941 #define BNX2_NVM_CFG4_FLASH_SIZE_128MBIT (7L<<0)
1943 #define BNX2_NVM_CFG4_FLASH_VENDOR_ST (0L<<3)
1945 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC (0x3L<<4)
1946 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8 (0L<<4)
1951 #define BNX2_NVM_CFG4_RESERVED (0x1ffffffL<<7)
1953 #define BNX2_NVM_RECONFIG 0x00006430
1954 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE (0xfL<<0)
1955 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ST (0L<<0)
1956 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL (1L<<0)
1957 #define BNX2_NVM_RECONFIG_RECONFIG_STRAP_VALUE (0xfL<<4)
1958 #define BNX2_NVM_RECONFIG_RESERVED (0x7fffffL<<8)
1965 * offset: 0xc00
1967 #define BNX2_DMA_COMMAND 0x00000c00
1968 #define BNX2_DMA_COMMAND_ENABLE (1L<<0)
1970 #define BNX2_DMA_STATUS 0x00000c04
1971 #define BNX2_DMA_STATUS_PAR_ERROR_STATE (1L<<0)
1982 #define BNX2_DMA_STATUS_GLOBAL_ERR_XI (1L<<0)
1985 #define BNX2_DMA_CONFIG 0x00000c08
1986 #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0)
1995 #define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12)
1996 #define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16)
1997 #define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20)
1999 #define BNX2_DMA_CONFIG_BIG_SIZE (0xfL<<24)
2000 #define BNX2_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24)
2001 #define BNX2_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24)
2002 #define BNX2_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24)
2003 #define BNX2_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24)
2004 #define BNX2_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24)
2005 #define BNX2_DMA_CONFIG_DAT_WBSWAP_MODE_XI (0x3L<<0)
2006 #define BNX2_DMA_CONFIG_CTL_WBSWAP_MODE_XI (0x3L<<4)
2007 #define BNX2_DMA_CONFIG_MAX_PL_XI (0x7L<<12)
2008 #define BNX2_DMA_CONFIG_MAX_PL_128B_XI (0L<<12)
2012 #define BNX2_DMA_CONFIG_MAX_RRS_XI (0x7L<<16)
2013 #define BNX2_DMA_CONFIG_MAX_RRS_128B_XI (0L<<16)
2022 #define BNX2_DMA_BLACKOUT 0x00000c0c
2023 #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0)
2024 #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8)
2025 #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16)
2027 #define BNX2_DMA_READ_MASTER_SETTING_0 0x00000c10
2028 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP (1L<<0)
2031 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_TRAFFIC_CLASS (0x7L<<4)
2036 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_TRAFFIC_CLASS (0x7L<<12)
2041 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_TRAFFIC_CLASS (0x7L<<20)
2046 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_TRAFFIC_CLASS (0x7L<<28)
2049 #define BNX2_DMA_READ_MASTER_SETTING_1 0x00000c14
2050 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP (1L<<0)
2053 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_TRAFFIC_CLASS (0x7L<<4)
2058 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_TRAFFIC_CLASS (0x7L<<12)
2061 #define BNX2_DMA_WRITE_MASTER_SETTING_0 0x00000c18
2062 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP (1L<<0)
2066 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_TRAFFIC_CLASS (0x7L<<4)
2072 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_TRAFFIC_CLASS (0x7L<<12)
2078 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_TRAFFIC_CLASS (0x7L<<28)
2081 #define BNX2_DMA_WRITE_MASTER_SETTING_1 0x00000c1c
2082 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP (1L<<0)
2086 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_TRAFFIC_CLASS (0x7L<<4)
2092 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_TRAFFIC_CLASS (0x7L<<12)
2095 #define BNX2_DMA_ARBITER 0x00000c20
2096 #define BNX2_DMA_ARBITER_NUM_READS (0x7L<<0)
2098 #define BNX2_DMA_ARBITER_WR_ARB_MODE_STRICT (0L<<4)
2100 #define BNX2_DMA_ARBITER_RD_ARB_MODE (0x3L<<5)
2101 #define BNX2_DMA_ARBITER_RD_ARB_MODE_STRICT (0L<<5)
2107 #define BNX2_DMA_ARBITER_OUSTD_READ_REQ (0xfL<<12)
2109 #define BNX2_DMA_ARB_TIMERS 0x00000c24
2110 #define BNX2_DMA_ARB_TIMERS_RD_DRR_WAIT_TIME (0xffL<<0)
2111 #define BNX2_DMA_ARB_TIMERS_TM_MIN_TIMEOUT (0xffL<<12)
2112 #define BNX2_DMA_ARB_TIMERS_TM_MAX_TIMEOUT (0xfffL<<20)
2114 #define BNX2_DMA_DEBUG_VECT_PEEK 0x00000c2c
2115 #define BNX2_DMA_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
2117 #define BNX2_DMA_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
2118 #define BNX2_DMA_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
2120 #define BNX2_DMA_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
2122 #define BNX2_DMA_TAG_RAM_00 0x00000c30
2123 #define BNX2_DMA_TAG_RAM_00_CHANNEL (0xfL<<0)
2124 #define BNX2_DMA_TAG_RAM_00_MASTER (0x7L<<4)
2125 #define BNX2_DMA_TAG_RAM_00_MASTER_CTX (0L<<4)
2131 #define BNX2_DMA_TAG_RAM_00_SWAP (0x3L<<7)
2132 #define BNX2_DMA_TAG_RAM_00_SWAP_CONFIG (0L<<7)
2138 #define BNX2_DMA_TAG_RAM_01 0x00000c34
2139 #define BNX2_DMA_TAG_RAM_01_CHANNEL (0xfL<<0)
2140 #define BNX2_DMA_TAG_RAM_01_MASTER (0x7L<<4)
2141 #define BNX2_DMA_TAG_RAM_01_MASTER_CTX (0L<<4)
2147 #define BNX2_DMA_TAG_RAM_01_SWAP (0x3L<<7)
2148 #define BNX2_DMA_TAG_RAM_01_SWAP_CONFIG (0L<<7)
2154 #define BNX2_DMA_TAG_RAM_02 0x00000c38
2155 #define BNX2_DMA_TAG_RAM_02_CHANNEL (0xfL<<0)
2156 #define BNX2_DMA_TAG_RAM_02_MASTER (0x7L<<4)
2157 #define BNX2_DMA_TAG_RAM_02_MASTER_CTX (0L<<4)
2163 #define BNX2_DMA_TAG_RAM_02_SWAP (0x3L<<7)
2164 #define BNX2_DMA_TAG_RAM_02_SWAP_CONFIG (0L<<7)
2170 #define BNX2_DMA_TAG_RAM_03 0x00000c3c
2171 #define BNX2_DMA_TAG_RAM_03_CHANNEL (0xfL<<0)
2172 #define BNX2_DMA_TAG_RAM_03_MASTER (0x7L<<4)
2173 #define BNX2_DMA_TAG_RAM_03_MASTER_CTX (0L<<4)
2179 #define BNX2_DMA_TAG_RAM_03_SWAP (0x3L<<7)
2180 #define BNX2_DMA_TAG_RAM_03_SWAP_CONFIG (0L<<7)
2186 #define BNX2_DMA_TAG_RAM_04 0x00000c40
2187 #define BNX2_DMA_TAG_RAM_04_CHANNEL (0xfL<<0)
2188 #define BNX2_DMA_TAG_RAM_04_MASTER (0x7L<<4)
2189 #define BNX2_DMA_TAG_RAM_04_MASTER_CTX (0L<<4)
2195 #define BNX2_DMA_TAG_RAM_04_SWAP (0x3L<<7)
2196 #define BNX2_DMA_TAG_RAM_04_SWAP_CONFIG (0L<<7)
2202 #define BNX2_DMA_TAG_RAM_05 0x00000c44
2203 #define BNX2_DMA_TAG_RAM_05_CHANNEL (0xfL<<0)
2204 #define BNX2_DMA_TAG_RAM_05_MASTER (0x7L<<4)
2205 #define BNX2_DMA_TAG_RAM_05_MASTER_CTX (0L<<4)
2211 #define BNX2_DMA_TAG_RAM_05_SWAP (0x3L<<7)
2212 #define BNX2_DMA_TAG_RAM_05_SWAP_CONFIG (0L<<7)
2218 #define BNX2_DMA_TAG_RAM_06 0x00000c48
2219 #define BNX2_DMA_TAG_RAM_06_CHANNEL (0xfL<<0)
2220 #define BNX2_DMA_TAG_RAM_06_MASTER (0x7L<<4)
2221 #define BNX2_DMA_TAG_RAM_06_MASTER_CTX (0L<<4)
2227 #define BNX2_DMA_TAG_RAM_06_SWAP (0x3L<<7)
2228 #define BNX2_DMA_TAG_RAM_06_SWAP_CONFIG (0L<<7)
2234 #define BNX2_DMA_TAG_RAM_07 0x00000c4c
2235 #define BNX2_DMA_TAG_RAM_07_CHANNEL (0xfL<<0)
2236 #define BNX2_DMA_TAG_RAM_07_MASTER (0x7L<<4)
2237 #define BNX2_DMA_TAG_RAM_07_MASTER_CTX (0L<<4)
2243 #define BNX2_DMA_TAG_RAM_07_SWAP (0x3L<<7)
2244 #define BNX2_DMA_TAG_RAM_07_SWAP_CONFIG (0L<<7)
2250 #define BNX2_DMA_TAG_RAM_08 0x00000c50
2251 #define BNX2_DMA_TAG_RAM_08_CHANNEL (0xfL<<0)
2252 #define BNX2_DMA_TAG_RAM_08_MASTER (0x7L<<4)
2253 #define BNX2_DMA_TAG_RAM_08_MASTER_CTX (0L<<4)
2259 #define BNX2_DMA_TAG_RAM_08_SWAP (0x3L<<7)
2260 #define BNX2_DMA_TAG_RAM_08_SWAP_CONFIG (0L<<7)
2266 #define BNX2_DMA_TAG_RAM_09 0x00000c54
2267 #define BNX2_DMA_TAG_RAM_09_CHANNEL (0xfL<<0)
2268 #define BNX2_DMA_TAG_RAM_09_MASTER (0x7L<<4)
2269 #define BNX2_DMA_TAG_RAM_09_MASTER_CTX (0L<<4)
2275 #define BNX2_DMA_TAG_RAM_09_SWAP (0x3L<<7)
2276 #define BNX2_DMA_TAG_RAM_09_SWAP_CONFIG (0L<<7)
2282 #define BNX2_DMA_TAG_RAM_10 0x00000c58
2283 #define BNX2_DMA_TAG_RAM_10_CHANNEL (0xfL<<0)
2284 #define BNX2_DMA_TAG_RAM_10_MASTER (0x7L<<4)
2285 #define BNX2_DMA_TAG_RAM_10_MASTER_CTX (0L<<4)
2291 #define BNX2_DMA_TAG_RAM_10_SWAP (0x3L<<7)
2292 #define BNX2_DMA_TAG_RAM_10_SWAP_CONFIG (0L<<7)
2298 #define BNX2_DMA_TAG_RAM_11 0x00000c5c
2299 #define BNX2_DMA_TAG_RAM_11_CHANNEL (0xfL<<0)
2300 #define BNX2_DMA_TAG_RAM_11_MASTER (0x7L<<4)
2301 #define BNX2_DMA_TAG_RAM_11_MASTER_CTX (0L<<4)
2307 #define BNX2_DMA_TAG_RAM_11_SWAP (0x3L<<7)
2308 #define BNX2_DMA_TAG_RAM_11_SWAP_CONFIG (0L<<7)
2314 #define BNX2_DMA_RCHAN_STAT_22 0x00000c60
2315 #define BNX2_DMA_RCHAN_STAT_30 0x00000c64
2316 #define BNX2_DMA_RCHAN_STAT_31 0x00000c68
2317 #define BNX2_DMA_RCHAN_STAT_32 0x00000c6c
2318 #define BNX2_DMA_RCHAN_STAT_40 0x00000c70
2319 #define BNX2_DMA_RCHAN_STAT_41 0x00000c74
2320 #define BNX2_DMA_RCHAN_STAT_42 0x00000c78
2321 #define BNX2_DMA_RCHAN_STAT_50 0x00000c7c
2322 #define BNX2_DMA_RCHAN_STAT_51 0x00000c80
2323 #define BNX2_DMA_RCHAN_STAT_52 0x00000c84
2324 #define BNX2_DMA_RCHAN_STAT_60 0x00000c88
2325 #define BNX2_DMA_RCHAN_STAT_61 0x00000c8c
2326 #define BNX2_DMA_RCHAN_STAT_62 0x00000c90
2327 #define BNX2_DMA_RCHAN_STAT_70 0x00000c94
2328 #define BNX2_DMA_RCHAN_STAT_71 0x00000c98
2329 #define BNX2_DMA_RCHAN_STAT_72 0x00000c9c
2330 #define BNX2_DMA_WCHAN_STAT_00 0x00000ca0
2331 #define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
2333 #define BNX2_DMA_WCHAN_STAT_01 0x00000ca4
2334 #define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
2336 #define BNX2_DMA_WCHAN_STAT_02 0x00000ca8
2337 #define BNX2_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0)
2342 #define BNX2_DMA_WCHAN_STAT_10 0x00000cac
2343 #define BNX2_DMA_WCHAN_STAT_11 0x00000cb0
2344 #define BNX2_DMA_WCHAN_STAT_12 0x00000cb4
2345 #define BNX2_DMA_WCHAN_STAT_20 0x00000cb8
2346 #define BNX2_DMA_WCHAN_STAT_21 0x00000cbc
2347 #define BNX2_DMA_WCHAN_STAT_22 0x00000cc0
2348 #define BNX2_DMA_WCHAN_STAT_30 0x00000cc4
2349 #define BNX2_DMA_WCHAN_STAT_31 0x00000cc8
2350 #define BNX2_DMA_WCHAN_STAT_32 0x00000ccc
2351 #define BNX2_DMA_WCHAN_STAT_40 0x00000cd0
2352 #define BNX2_DMA_WCHAN_STAT_41 0x00000cd4
2353 #define BNX2_DMA_WCHAN_STAT_42 0x00000cd8
2354 #define BNX2_DMA_WCHAN_STAT_50 0x00000cdc
2355 #define BNX2_DMA_WCHAN_STAT_51 0x00000ce0
2356 #define BNX2_DMA_WCHAN_STAT_52 0x00000ce4
2357 #define BNX2_DMA_WCHAN_STAT_60 0x00000ce8
2358 #define BNX2_DMA_WCHAN_STAT_61 0x00000cec
2359 #define BNX2_DMA_WCHAN_STAT_62 0x00000cf0
2360 #define BNX2_DMA_WCHAN_STAT_70 0x00000cf4
2361 #define BNX2_DMA_WCHAN_STAT_71 0x00000cf8
2362 #define BNX2_DMA_WCHAN_STAT_72 0x00000cfc
2363 #define BNX2_DMA_ARB_STAT_00 0x00000d00
2364 #define BNX2_DMA_ARB_STAT_00_MASTER (0xffffL<<0)
2365 #define BNX2_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16)
2366 #define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24)
2368 #define BNX2_DMA_ARB_STAT_01 0x00000d04
2369 #define BNX2_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0)
2370 #define BNX2_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4)
2371 #define BNX2_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8)
2372 #define BNX2_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12)
2373 #define BNX2_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16)
2374 #define BNX2_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20)
2375 #define BNX2_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24)
2376 #define BNX2_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28)
2378 #define BNX2_DMA_FUSE_CTRL0_CMD 0x00000f00
2379 #define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0)
2383 #define BNX2_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8)
2385 #define BNX2_DMA_FUSE_CTRL0_DATA 0x00000f04
2386 #define BNX2_DMA_FUSE_CTRL1_CMD 0x00000f08
2387 #define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0)
2391 #define BNX2_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8)
2393 #define BNX2_DMA_FUSE_CTRL1_DATA 0x00000f0c
2394 #define BNX2_DMA_FUSE_CTRL2_CMD 0x00000f10
2395 #define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0)
2399 #define BNX2_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8)
2401 #define BNX2_DMA_FUSE_CTRL2_DATA 0x00000f14
2406 * offset: 0x1000
2408 #define BNX2_CTX_COMMAND 0x00001000
2409 #define BNX2_CTX_COMMAND_ENABLED (1L<<0)
2413 #define BNX2_CTX_COMMAND_FLUSH_AHEAD (0x1fL<<8)
2415 #define BNX2_CTX_COMMAND_PAGE_SIZE (0xfL<<16)
2416 #define BNX2_CTX_COMMAND_PAGE_SIZE_256 (0L<<16)
2430 #define BNX2_CTX_STATUS 0x00001004
2431 #define BNX2_CTX_STATUS_LOCK_WAIT (1L<<0)
2444 #define BNX2_CTX_VIRT_ADDR 0x00001008
2445 #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6)
2447 #define BNX2_CTX_PAGE_TBL 0x0000100c
2448 #define BNX2_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6)
2450 #define BNX2_CTX_DATA_ADR 0x00001010
2451 #define BNX2_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2)
2453 #define BNX2_CTX_DATA 0x00001014
2454 #define BNX2_CTX_LOCK 0x00001018
2455 #define BNX2_CTX_LOCK_TYPE (0x7L<<0)
2456 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0)
2457 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0)
2458 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0)
2459 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0)
2460 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0)
2461 #define BNX2_CTX_LOCK_TYPE_VOID_XI (0L<<0)
2462 #define BNX2_CTX_LOCK_TYPE_PROTOCOL_XI (1L<<0)
2463 #define BNX2_CTX_LOCK_TYPE_TX_XI (2L<<0)
2464 #define BNX2_CTX_LOCK_TYPE_TIMER_XI (4L<<0)
2465 #define BNX2_CTX_LOCK_TYPE_COMPLETE_XI (7L<<0)
2466 #define BNX2_CTX_LOCK_CID_VALUE (0x3fffL<<7)
2468 #define BNX2_CTX_LOCK_MODE (0x7L<<27)
2469 #define BNX2_CTX_LOCK_MODE_UNLOCK (0x0L<<27)
2470 #define BNX2_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27)
2471 #define BNX2_CTX_LOCK_MODE_SURE (0x2L<<27)
2475 #define BNX2_CTX_CTX_CTRL 0x0000101c
2476 #define BNX2_CTX_CTX_CTRL_CTX_ADDR (0x7ffffL<<2)
2477 #define BNX2_CTX_CTX_CTRL_MOD_USAGE_CNT (0x3L<<21)
2479 #define BNX2_CTX_CTX_CTRL_PREFETCH_SIZE (0x3L<<24)
2484 #define BNX2_CTX_CTX_DATA 0x00001020
2485 #define BNX2_CTX_ACCESS_STATUS 0x00001040
2486 #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0)
2487 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10)
2488 #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12)
2489 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14)
2490 #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17)
2491 #define BNX2_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI (0x1fL<<0)
2492 #define BNX2_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI (0x1fL<<5)
2493 #define BNX2_CTX_ACCESS_STATUS_REQUEST_XI (0x3fffffL<<10)
2495 #define BNX2_CTX_DBG_LOCK_STATUS 0x00001044
2496 #define BNX2_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0)
2497 #define BNX2_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22)
2499 #define BNX2_CTX_CACHE_CTRL_STATUS 0x00001048
2500 #define BNX2_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW (1L<<0)
2503 #define BNX2_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT (0x3fL<<7)
2504 #define BNX2_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED (0x3fL<<13)
2517 #define BNX2_CTX_CACHE_CTRL_SM_STATUS 0x0000104c
2518 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_DWC (0x7L<<0)
2519 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC (0x7L<<3)
2520 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC (0x7L<<6)
2521 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC (0x7L<<9)
2522 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR (0x7fffL<<16)
2524 #define BNX2_CTX_CACHE_STATUS 0x00001050
2525 #define BNX2_CTX_CACHE_STATUS_HELD_ENTRIES (0x3ffL<<0)
2526 #define BNX2_CTX_CACHE_STATUS_MAX_HELD_ENTRIES (0x3ffL<<16)
2528 #define BNX2_CTX_DMA_STATUS 0x00001054
2529 #define BNX2_CTX_DMA_STATUS_RD_CHAN0_STATUS (0x3L<<0)
2530 #define BNX2_CTX_DMA_STATUS_RD_CHAN1_STATUS (0x3L<<2)
2531 #define BNX2_CTX_DMA_STATUS_RD_CHAN2_STATUS (0x3L<<4)
2532 #define BNX2_CTX_DMA_STATUS_RD_CHAN3_STATUS (0x3L<<6)
2533 #define BNX2_CTX_DMA_STATUS_RD_CHAN4_STATUS (0x3L<<8)
2534 #define BNX2_CTX_DMA_STATUS_RD_CHAN5_STATUS (0x3L<<10)
2535 #define BNX2_CTX_DMA_STATUS_RD_CHAN6_STATUS (0x3L<<12)
2536 #define BNX2_CTX_DMA_STATUS_RD_CHAN7_STATUS (0x3L<<14)
2537 #define BNX2_CTX_DMA_STATUS_RD_CHAN8_STATUS (0x3L<<16)
2538 #define BNX2_CTX_DMA_STATUS_RD_CHAN9_STATUS (0x3L<<18)
2539 #define BNX2_CTX_DMA_STATUS_RD_CHAN10_STATUS (0x3L<<20)
2541 #define BNX2_CTX_REP_STATUS 0x00001058
2542 #define BNX2_CTX_REP_STATUS_ERROR_ENTRY (0x3ffL<<0)
2543 #define BNX2_CTX_REP_STATUS_ERROR_CLIENT_ID (0x1fL<<10)
2548 #define BNX2_CTX_CKSUM_ERROR_STATUS 0x0000105c
2549 #define BNX2_CTX_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
2550 #define BNX2_CTX_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
2552 #define BNX2_CTX_CHNL_LOCK_STATUS_0 0x00001080
2553 #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0)
2554 #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14)
2557 #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE_XI (0x7L<<15)
2559 #define BNX2_CTX_CHNL_LOCK_STATUS_1 0x00001084
2560 #define BNX2_CTX_CHNL_LOCK_STATUS_2 0x00001088
2561 #define BNX2_CTX_CHNL_LOCK_STATUS_3 0x0000108c
2562 #define BNX2_CTX_CHNL_LOCK_STATUS_4 0x00001090
2563 #define BNX2_CTX_CHNL_LOCK_STATUS_5 0x00001094
2564 #define BNX2_CTX_CHNL_LOCK_STATUS_6 0x00001098
2565 #define BNX2_CTX_CHNL_LOCK_STATUS_7 0x0000109c
2566 #define BNX2_CTX_CHNL_LOCK_STATUS_8 0x000010a0
2567 #define BNX2_CTX_CHNL_LOCK_STATUS_9 0x000010a4
2569 #define BNX2_CTX_CACHE_DATA 0x000010c4
2570 #define BNX2_CTX_HOST_PAGE_TBL_CTRL 0x000010c8
2571 #define BNX2_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR (0x1ffL<<0)
2575 #define BNX2_CTX_HOST_PAGE_TBL_DATA0 0x000010cc
2576 #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID (1L<<0)
2577 #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALUE (0xffffffL<<8)
2579 #define BNX2_CTX_HOST_PAGE_TBL_DATA1 0x000010d0
2580 #define BNX2_CTX_CAM_CTRL 0x000010d4
2581 #define BNX2_CTX_CAM_CTRL_CAM_ADDR (0x3ffL<<0)
2591 * offset: 0x1400
2593 #define BNX2_EMAC_MODE 0x00001400
2594 #define BNX2_EMAC_MODE_RESET (1L<<0)
2596 #define BNX2_EMAC_MODE_PORT (0x3L<<2)
2597 #define BNX2_EMAC_MODE_PORT_NONE (0L<<2)
2614 #define BNX2_EMAC_STATUS 0x00001404
2627 #define BNX2_EMAC_ATTENTION_ENA 0x00001408
2636 #define BNX2_EMAC_LED 0x0000140c
2637 #define BNX2_EMAC_LED_OVERRIDE (1L<<0)
2650 #define BNX2_EMAC_LED_ACTIVITY_SEL (0x3L<<17)
2651 #define BNX2_EMAC_LED_ACTIVITY_SEL_0 (0L<<17)
2655 #define BNX2_EMAC_LED_BLNK_RATE (0xfffL<<19)
2658 #define BNX2_EMAC_MAC_MATCH0 0x00001410
2659 #define BNX2_EMAC_MAC_MATCH1 0x00001414
2660 #define BNX2_EMAC_MAC_MATCH2 0x00001418
2661 #define BNX2_EMAC_MAC_MATCH3 0x0000141c
2662 #define BNX2_EMAC_MAC_MATCH4 0x00001420
2663 #define BNX2_EMAC_MAC_MATCH5 0x00001424
2664 #define BNX2_EMAC_MAC_MATCH6 0x00001428
2665 #define BNX2_EMAC_MAC_MATCH7 0x0000142c
2666 #define BNX2_EMAC_MAC_MATCH8 0x00001430
2667 #define BNX2_EMAC_MAC_MATCH9 0x00001434
2668 #define BNX2_EMAC_MAC_MATCH10 0x00001438
2669 #define BNX2_EMAC_MAC_MATCH11 0x0000143c
2670 #define BNX2_EMAC_MAC_MATCH12 0x00001440
2671 #define BNX2_EMAC_MAC_MATCH13 0x00001444
2672 #define BNX2_EMAC_MAC_MATCH14 0x00001448
2673 #define BNX2_EMAC_MAC_MATCH15 0x0000144c
2674 #define BNX2_EMAC_MAC_MATCH16 0x00001450
2675 #define BNX2_EMAC_MAC_MATCH17 0x00001454
2676 #define BNX2_EMAC_MAC_MATCH18 0x00001458
2677 #define BNX2_EMAC_MAC_MATCH19 0x0000145c
2678 #define BNX2_EMAC_MAC_MATCH20 0x00001460
2679 #define BNX2_EMAC_MAC_MATCH21 0x00001464
2680 #define BNX2_EMAC_MAC_MATCH22 0x00001468
2681 #define BNX2_EMAC_MAC_MATCH23 0x0000146c
2682 #define BNX2_EMAC_MAC_MATCH24 0x00001470
2683 #define BNX2_EMAC_MAC_MATCH25 0x00001474
2684 #define BNX2_EMAC_MAC_MATCH26 0x00001478
2685 #define BNX2_EMAC_MAC_MATCH27 0x0000147c
2686 #define BNX2_EMAC_MAC_MATCH28 0x00001480
2687 #define BNX2_EMAC_MAC_MATCH29 0x00001484
2688 #define BNX2_EMAC_MAC_MATCH30 0x00001488
2689 #define BNX2_EMAC_MAC_MATCH31 0x0000148c
2690 #define BNX2_EMAC_BACKOFF_SEED 0x00001498
2691 #define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0)
2693 #define BNX2_EMAC_RX_MTU_SIZE 0x0000149c
2694 #define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0)
2697 #define BNX2_EMAC_SERDES_CNTL 0x000014a4
2698 #define BNX2_EMAC_SERDES_CNTL_RXR (0x7L<<0)
2699 #define BNX2_EMAC_SERDES_CNTL_RXG (0x3L<<3)
2701 #define BNX2_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7)
2712 #define BNX2_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20)
2713 #define BNX2_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22)
2715 #define BNX2_EMAC_SERDES_STATUS 0x000014a8
2716 #define BNX2_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0)
2719 #define BNX2_EMAC_MDIO_COMM 0x000014ac
2720 #define BNX2_EMAC_MDIO_COMM_DATA (0xffffL<<0)
2721 #define BNX2_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16)
2722 #define BNX2_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21)
2723 #define BNX2_EMAC_MDIO_COMM_COMMAND (0x3L<<26)
2724 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
2725 #define BNX2_EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
2738 #define BNX2_EMAC_MDIO_STATUS 0x000014b0
2739 #define BNX2_EMAC_MDIO_STATUS_LINK (1L<<0)
2742 #define BNX2_EMAC_MDIO_MODE 0x000014b4
2751 #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16)
2752 #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT_XI (0x3fL<<16)
2755 #define BNX2_EMAC_MDIO_AUTO_STATUS 0x000014b8
2756 #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
2758 #define BNX2_EMAC_TX_MODE 0x000014bc
2759 #define BNX2_EMAC_TX_MODE_RESET (1L<<0)
2767 #define BNX2_EMAC_TX_STATUS 0x000014c0
2768 #define BNX2_EMAC_TX_STATUS_XOFFED (1L<<0)
2775 #define BNX2_EMAC_TX_LENGTHS 0x000014c4
2776 #define BNX2_EMAC_TX_LENGTHS_SLOT (0xffL<<0)
2777 #define BNX2_EMAC_TX_LENGTHS_IPG (0xfL<<8)
2778 #define BNX2_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12)
2780 #define BNX2_EMAC_RX_MODE 0x000014c8
2781 #define BNX2_EMAC_RX_MODE_RESET (1L<<0)
2794 #define BNX2_EMAC_RX_STATUS 0x000014cc
2795 #define BNX2_EMAC_RX_STATUS_FFED (1L<<0)
2799 #define BNX2_EMAC_MULTICAST_HASH0 0x000014d0
2800 #define BNX2_EMAC_MULTICAST_HASH1 0x000014d4
2801 #define BNX2_EMAC_MULTICAST_HASH2 0x000014d8
2802 #define BNX2_EMAC_MULTICAST_HASH3 0x000014dc
2803 #define BNX2_EMAC_MULTICAST_HASH4 0x000014e0
2804 #define BNX2_EMAC_MULTICAST_HASH5 0x000014e4
2805 #define BNX2_EMAC_MULTICAST_HASH6 0x000014e8
2806 #define BNX2_EMAC_MULTICAST_HASH7 0x000014ec
2807 #define BNX2_EMAC_CKSUM_ERROR_STATUS 0x000014f0
2808 #define BNX2_EMAC_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
2809 #define BNX2_EMAC_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
2811 #define BNX2_EMAC_RX_STAT_IFHCINOCTETS 0x00001500
2812 #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504
2813 #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508
2814 #define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c
2815 #define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510
2816 #define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514
2817 #define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518
2818 #define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c
2819 #define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520
2820 #define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524
2821 #define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528
2822 #define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c
2823 #define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530
2824 #define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534
2825 #define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538
2826 #define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c
2827 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540
2828 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544
2829 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548
2830 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c
2831 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550
2832 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554
2833 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS 0x00001558
2834 #define BNX2_EMAC_RXMAC_DEBUG0 0x0000155c
2835 #define BNX2_EMAC_RXMAC_DEBUG1 0x00001560
2836 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
2843 #define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7)
2844 #define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23)
2846 #define BNX2_EMAC_RXMAC_DEBUG2 0x00001564
2847 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0)
2848 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0)
2849 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0)
2850 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0)
2851 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0)
2852 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0)
2853 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0)
2854 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0)
2855 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0)
2856 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3)
2857 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3)
2858 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3)
2859 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3)
2860 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3)
2861 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3)
2862 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3)
2863 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3)
2864 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3)
2865 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3)
2866 #define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7)
2870 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
2872 #define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19)
2873 #define BNX2_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23)
2875 #define BNX2_EMAC_RXMAC_DEBUG3 0x00001568
2876 #define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0)
2877 #define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16)
2879 #define BNX2_EMAC_RXMAC_DEBUG4 0x0000156c
2880 #define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0)
2881 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16)
2882 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16)
2883 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16)
2884 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16)
2885 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16)
2886 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16)
2887 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16)
2888 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16)
2889 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16)
2890 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16)
2891 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16)
2892 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16)
2893 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16)
2894 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16)
2895 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16)
2896 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16)
2897 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16)
2898 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16)
2899 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16)
2900 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16)
2901 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16)
2902 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16)
2903 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16)
2904 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16)
2905 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16)
2906 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16)
2907 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16)
2908 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16)
2909 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16)
2910 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16)
2911 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16)
2912 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16)
2913 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16)
2914 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16)
2915 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16)
2916 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16)
2917 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16)
2918 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16)
2919 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16)
2920 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16)
2921 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16)
2930 #define BNX2_EMAC_RXMAC_DEBUG5 0x00001570
2931 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0)
2932 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
2933 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0)
2934 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0)
2935 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0)
2936 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0)
2937 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0)
2938 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0)
2939 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4)
2940 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4)
2941 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4)
2942 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4)
2943 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4)
2944 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4)
2945 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4)
2946 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4)
2948 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8)
2954 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16)
2956 #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20)
2958 #define BNX2_EMAC_RX_STAT_FALSECARRIERERRORS 0x00001574
2959 #define BNX2_EMAC_RX_STAT_AC0 0x00001580
2960 #define BNX2_EMAC_RX_STAT_AC1 0x00001584
2961 #define BNX2_EMAC_RX_STAT_AC2 0x00001588
2962 #define BNX2_EMAC_RX_STAT_AC3 0x0000158c
2963 #define BNX2_EMAC_RX_STAT_AC4 0x00001590
2964 #define BNX2_EMAC_RX_STAT_AC5 0x00001594
2965 #define BNX2_EMAC_RX_STAT_AC6 0x00001598
2966 #define BNX2_EMAC_RX_STAT_AC7 0x0000159c
2967 #define BNX2_EMAC_RX_STAT_AC8 0x000015a0
2968 #define BNX2_EMAC_RX_STAT_AC9 0x000015a4
2969 #define BNX2_EMAC_RX_STAT_AC10 0x000015a8
2970 #define BNX2_EMAC_RX_STAT_AC11 0x000015ac
2971 #define BNX2_EMAC_RX_STAT_AC12 0x000015b0
2972 #define BNX2_EMAC_RX_STAT_AC13 0x000015b4
2973 #define BNX2_EMAC_RX_STAT_AC14 0x000015b8
2974 #define BNX2_EMAC_RX_STAT_AC15 0x000015bc
2975 #define BNX2_EMAC_RX_STAT_AC16 0x000015c0
2976 #define BNX2_EMAC_RX_STAT_AC17 0x000015c4
2977 #define BNX2_EMAC_RX_STAT_AC18 0x000015c8
2978 #define BNX2_EMAC_RX_STAT_AC19 0x000015cc
2979 #define BNX2_EMAC_RX_STAT_AC20 0x000015d0
2980 #define BNX2_EMAC_RX_STAT_AC21 0x000015d4
2981 #define BNX2_EMAC_RX_STAT_AC22 0x000015d8
2982 #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc
2983 #define BNX2_EMAC_RX_STAT_AC_28 0x000015f4
2984 #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600
2985 #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604
2986 #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608
2987 #define BNX2_EMAC_TX_STAT_OUTXONSENT 0x0000160c
2988 #define BNX2_EMAC_TX_STAT_OUTXOFFSENT 0x00001610
2989 #define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614
2990 #define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618
2991 #define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c
2992 #define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620
2993 #define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624
2994 #define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628
2995 #define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c
2996 #define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630
2997 #define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634
2998 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638
2999 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c
3000 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640
3001 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644
3002 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648
3003 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c
3004 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS 0x00001650
3005 #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654
3006 #define BNX2_EMAC_TXMAC_DEBUG0 0x00001658
3007 #define BNX2_EMAC_TXMAC_DEBUG1 0x0000165c
3008 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0)
3009 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0)
3010 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0)
3011 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0)
3012 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0)
3013 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0)
3014 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0)
3015 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0)
3016 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0)
3019 #define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6)
3025 #define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15)
3026 #define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19)
3028 #define BNX2_EMAC_TXMAC_DEBUG2 0x00001660
3029 #define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0)
3030 #define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10)
3031 #define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26)
3034 #define BNX2_EMAC_TXMAC_DEBUG3 0x00001664
3035 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0)
3036 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0)
3037 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0)
3038 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0)
3039 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0)
3040 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0)
3041 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0)
3042 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0)
3043 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0)
3044 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0)
3045 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0)
3046 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0)
3047 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0)
3048 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0)
3049 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0)
3050 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0)
3051 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4)
3052 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4)
3053 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4)
3054 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4)
3055 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4)
3056 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4)
3057 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4)
3058 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4)
3061 #define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9)
3062 #define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13)
3064 #define BNX2_EMAC_TXMAC_DEBUG4 0x00001668
3065 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0)
3066 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16)
3067 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16)
3068 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16)
3069 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16)
3070 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16)
3071 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16)
3072 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16)
3073 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16)
3074 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16)
3075 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16)
3076 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16)
3077 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16)
3078 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16)
3079 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16)
3093 #define BNX2_EMAC_TX_STAT_AC0 0x00001680
3094 #define BNX2_EMAC_TX_STAT_AC1 0x00001684
3095 #define BNX2_EMAC_TX_STAT_AC2 0x00001688
3096 #define BNX2_EMAC_TX_STAT_AC3 0x0000168c
3097 #define BNX2_EMAC_TX_STAT_AC4 0x00001690
3098 #define BNX2_EMAC_TX_STAT_AC5 0x00001694
3099 #define BNX2_EMAC_TX_STAT_AC6 0x00001698
3100 #define BNX2_EMAC_TX_STAT_AC7 0x0000169c
3101 #define BNX2_EMAC_TX_STAT_AC8 0x000016a0
3102 #define BNX2_EMAC_TX_STAT_AC9 0x000016a4
3103 #define BNX2_EMAC_TX_STAT_AC10 0x000016a8
3104 #define BNX2_EMAC_TX_STAT_AC11 0x000016ac
3105 #define BNX2_EMAC_TX_STAT_AC12 0x000016b0
3106 #define BNX2_EMAC_TX_STAT_AC13 0x000016b4
3107 #define BNX2_EMAC_TX_STAT_AC14 0x000016b8
3108 #define BNX2_EMAC_TX_STAT_AC15 0x000016bc
3109 #define BNX2_EMAC_TX_STAT_AC16 0x000016c0
3110 #define BNX2_EMAC_TX_STAT_AC17 0x000016c4
3111 #define BNX2_EMAC_TX_STAT_AC18 0x000016c8
3112 #define BNX2_EMAC_TX_STAT_AC19 0x000016cc
3113 #define BNX2_EMAC_TX_STAT_AC20 0x000016d0
3114 #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8
3115 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL 0x000016fc
3116 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC (0x7fL<<0)
3117 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM (0x7fL<<16)
3123 * offset: 0x1800
3125 #define BNX2_RPM_COMMAND 0x00001800
3126 #define BNX2_RPM_COMMAND_ENABLED (1L<<0)
3129 #define BNX2_RPM_STATUS 0x00001804
3130 #define BNX2_RPM_STATUS_MBUF_WAIT (1L<<0)
3133 #define BNX2_RPM_CONFIG 0x00001808
3134 #define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0)
3138 #define BNX2_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4)
3142 #define BNX2_RPM_MGMT_PKT_CTRL 0x0000180c
3143 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_SORT (0xfL<<0)
3144 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_RULE (0xfL<<4)
3148 #define BNX2_RPM_VLAN_MATCH0 0x00001810
3149 #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0)
3151 #define BNX2_RPM_VLAN_MATCH1 0x00001814
3152 #define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0)
3154 #define BNX2_RPM_VLAN_MATCH2 0x00001818
3155 #define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0)
3157 #define BNX2_RPM_VLAN_MATCH3 0x0000181c
3158 #define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0)
3160 #define BNX2_RPM_SORT_USER0 0x00001820
3161 #define BNX2_RPM_SORT_USER0_PM_EN (0xffffL<<0)
3166 #define BNX2_RPM_SORT_USER0_VLAN_EN (0xfL<<20)
3171 #define BNX2_RPM_SORT_USER1 0x00001824
3172 #define BNX2_RPM_SORT_USER1_PM_EN (0xffffL<<0)
3177 #define BNX2_RPM_SORT_USER1_VLAN_EN (0xfL<<20)
3181 #define BNX2_RPM_SORT_USER2 0x00001828
3182 #define BNX2_RPM_SORT_USER2_PM_EN (0xffffL<<0)
3187 #define BNX2_RPM_SORT_USER2_VLAN_EN (0xfL<<20)
3191 #define BNX2_RPM_SORT_USER3 0x0000182c
3192 #define BNX2_RPM_SORT_USER3_PM_EN (0xffffL<<0)
3197 #define BNX2_RPM_SORT_USER3_VLAN_EN (0xfL<<20)
3201 #define BNX2_RPM_STAT_L2_FILTER_DISCARDS 0x00001840
3202 #define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844
3203 #define BNX2_RPM_STAT_IFINFTQDISCARDS 0x00001848
3204 #define BNX2_RPM_STAT_IFINMBUFDISCARD 0x0000184c
3205 #define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850
3206 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0 0x00001854
3207 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN (0xffL<<0)
3208 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER (0xffL<<16)
3212 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1 0x00001858
3213 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN (0xffL<<0)
3214 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER (0xffL<<16)
3218 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2 0x0000185c
3219 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN (0xffL<<0)
3220 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER (0xffL<<16)
3224 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3 0x00001860
3225 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN (0xffL<<0)
3226 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER (0xffL<<16)
3230 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4 0x00001864
3231 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN (0xffL<<0)
3232 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER (0xffL<<16)
3236 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5 0x00001868
3237 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN (0xffL<<0)
3238 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER (0xffL<<16)
3242 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6 0x0000186c
3243 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN (0xffL<<0)
3244 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER (0xffL<<16)
3248 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7 0x00001870
3249 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN (0xffL<<0)
3250 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER (0xffL<<16)
3254 #define BNX2_RPM_STAT_AC0 0x00001880
3255 #define BNX2_RPM_STAT_AC1 0x00001884
3256 #define BNX2_RPM_STAT_AC2 0x00001888
3257 #define BNX2_RPM_STAT_AC3 0x0000188c
3258 #define BNX2_RPM_STAT_AC4 0x00001890
3259 #define BNX2_RPM_RC_CNTL_16 0x000018e0
3260 #define BNX2_RPM_RC_CNTL_16_OFFSET (0xffL<<0)
3261 #define BNX2_RPM_RC_CNTL_16_CLASS (0x7L<<8)
3264 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE (0x7L<<13)
3265 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_START (0L<<13)
3272 #define BNX2_RPM_RC_CNTL_16_COMP (0x3L<<16)
3273 #define BNX2_RPM_RC_CNTL_16_COMP_EQUAL (0L<<16)
3279 #define BNX2_RPM_RC_CNTL_16_CMDSEL (0x1fL<<20)
3287 #define BNX2_RPM_RC_VALUE_MASK_16 0x000018e4
3288 #define BNX2_RPM_RC_VALUE_MASK_16_VALUE (0xffffL<<0)
3289 #define BNX2_RPM_RC_VALUE_MASK_16_MASK (0xffffL<<16)
3291 #define BNX2_RPM_RC_CNTL_17 0x000018e8
3292 #define BNX2_RPM_RC_CNTL_17_OFFSET (0xffL<<0)
3293 #define BNX2_RPM_RC_CNTL_17_CLASS (0x7L<<8)
3296 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE (0x7L<<13)
3297 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_START (0L<<13)
3304 #define BNX2_RPM_RC_CNTL_17_COMP (0x3L<<16)
3305 #define BNX2_RPM_RC_CNTL_17_COMP_EQUAL (0L<<16)
3311 #define BNX2_RPM_RC_CNTL_17_CMDSEL (0x1fL<<20)
3319 #define BNX2_RPM_RC_VALUE_MASK_17 0x000018ec
3320 #define BNX2_RPM_RC_VALUE_MASK_17_VALUE (0xffffL<<0)
3321 #define BNX2_RPM_RC_VALUE_MASK_17_MASK (0xffffL<<16)
3323 #define BNX2_RPM_RC_CNTL_18 0x000018f0
3324 #define BNX2_RPM_RC_CNTL_18_OFFSET (0xffL<<0)
3325 #define BNX2_RPM_RC_CNTL_18_CLASS (0x7L<<8)
3328 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE (0x7L<<13)
3329 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_START (0L<<13)
3336 #define BNX2_RPM_RC_CNTL_18_COMP (0x3L<<16)
3337 #define BNX2_RPM_RC_CNTL_18_COMP_EQUAL (0L<<16)
3343 #define BNX2_RPM_RC_CNTL_18_CMDSEL (0x1fL<<20)
3351 #define BNX2_RPM_RC_VALUE_MASK_18 0x000018f4
3352 #define BNX2_RPM_RC_VALUE_MASK_18_VALUE (0xffffL<<0)
3353 #define BNX2_RPM_RC_VALUE_MASK_18_MASK (0xffffL<<16)
3355 #define BNX2_RPM_RC_CNTL_19 0x000018f8
3356 #define BNX2_RPM_RC_CNTL_19_OFFSET (0xffL<<0)
3357 #define BNX2_RPM_RC_CNTL_19_CLASS (0x7L<<8)
3360 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE (0x7L<<13)
3361 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_START (0L<<13)
3368 #define BNX2_RPM_RC_CNTL_19_COMP (0x3L<<16)
3369 #define BNX2_RPM_RC_CNTL_19_COMP_EQUAL (0L<<16)
3375 #define BNX2_RPM_RC_CNTL_19_CMDSEL (0x1fL<<20)
3383 #define BNX2_RPM_RC_VALUE_MASK_19 0x000018fc
3384 #define BNX2_RPM_RC_VALUE_MASK_19_VALUE (0xffffL<<0)
3385 #define BNX2_RPM_RC_VALUE_MASK_19_MASK (0xffffL<<16)
3387 #define BNX2_RPM_RC_CNTL_0 0x00001900
3388 #define BNX2_RPM_RC_CNTL_0_OFFSET (0xffL<<0)
3389 #define BNX2_RPM_RC_CNTL_0_CLASS (0x7L<<8)
3392 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13)
3393 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13)
3400 #define BNX2_RPM_RC_CNTL_0_COMP (0x3L<<16)
3401 #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16)
3407 #define BNX2_RPM_RC_CNTL_0_CMDSEL (0xfL<<20)
3409 #define BNX2_RPM_RC_CNTL_0_CMDSEL_XI (0x1fL<<20)
3417 #define BNX2_RPM_RC_VALUE_MASK_0 0x00001904
3418 #define BNX2_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0)
3419 #define BNX2_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16)
3421 #define BNX2_RPM_RC_CNTL_1 0x00001908
3422 #define BNX2_RPM_RC_CNTL_1_A (0x3ffffL<<0)
3423 #define BNX2_RPM_RC_CNTL_1_B (0xfffL<<19)
3424 #define BNX2_RPM_RC_CNTL_1_OFFSET_XI (0xffL<<0)
3425 #define BNX2_RPM_RC_CNTL_1_CLASS_XI (0x7L<<8)
3428 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_XI (0x7L<<13)
3429 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_START_XI (0L<<13)
3436 #define BNX2_RPM_RC_CNTL_1_COMP_XI (0x3L<<16)
3437 #define BNX2_RPM_RC_CNTL_1_COMP_EQUAL_XI (0L<<16)
3443 #define BNX2_RPM_RC_CNTL_1_CMDSEL_XI (0x1fL<<20)
3451 #define BNX2_RPM_RC_VALUE_MASK_1 0x0000190c
3452 #define BNX2_RPM_RC_VALUE_MASK_1_VALUE (0xffffL<<0)
3453 #define BNX2_RPM_RC_VALUE_MASK_1_MASK (0xffffL<<16)
3455 #define BNX2_RPM_RC_CNTL_2 0x00001910
3456 #define BNX2_RPM_RC_CNTL_2_A (0x3ffffL<<0)
3457 #define BNX2_RPM_RC_CNTL_2_B (0xfffL<<19)
3458 #define BNX2_RPM_RC_CNTL_2_OFFSET_XI (0xffL<<0)
3459 #define BNX2_RPM_RC_CNTL_2_CLASS_XI (0x7L<<8)
3462 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_XI (0x7L<<13)
3463 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_START_XI (0L<<13)
3470 #define BNX2_RPM_RC_CNTL_2_COMP_XI (0x3L<<16)
3471 #define BNX2_RPM_RC_CNTL_2_COMP_EQUAL_XI (0L<<16)
3477 #define BNX2_RPM_RC_CNTL_2_CMDSEL_XI (0x1fL<<20)
3485 #define BNX2_RPM_RC_VALUE_MASK_2 0x00001914
3486 #define BNX2_RPM_RC_VALUE_MASK_2_VALUE (0xffffL<<0)
3487 #define BNX2_RPM_RC_VALUE_MASK_2_MASK (0xffffL<<16)
3489 #define BNX2_RPM_RC_CNTL_3 0x00001918
3490 #define BNX2_RPM_RC_CNTL_3_A (0x3ffffL<<0)
3491 #define BNX2_RPM_RC_CNTL_3_B (0xfffL<<19)
3492 #define BNX2_RPM_RC_CNTL_3_OFFSET_XI (0xffL<<0)
3493 #define BNX2_RPM_RC_CNTL_3_CLASS_XI (0x7L<<8)
3496 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_XI (0x7L<<13)
3497 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_START_XI (0L<<13)
3504 #define BNX2_RPM_RC_CNTL_3_COMP_XI (0x3L<<16)
3505 #define BNX2_RPM_RC_CNTL_3_COMP_EQUAL_XI (0L<<16)
3511 #define BNX2_RPM_RC_CNTL_3_CMDSEL_XI (0x1fL<<20)
3519 #define BNX2_RPM_RC_VALUE_MASK_3 0x0000191c
3520 #define BNX2_RPM_RC_VALUE_MASK_3_VALUE (0xffffL<<0)
3521 #define BNX2_RPM_RC_VALUE_MASK_3_MASK (0xffffL<<16)
3523 #define BNX2_RPM_RC_CNTL_4 0x00001920
3524 #define BNX2_RPM_RC_CNTL_4_A (0x3ffffL<<0)
3525 #define BNX2_RPM_RC_CNTL_4_B (0xfffL<<19)
3526 #define BNX2_RPM_RC_CNTL_4_OFFSET_XI (0xffL<<0)
3527 #define BNX2_RPM_RC_CNTL_4_CLASS_XI (0x7L<<8)
3530 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_XI (0x7L<<13)
3531 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_START_XI (0L<<13)
3538 #define BNX2_RPM_RC_CNTL_4_COMP_XI (0x3L<<16)
3539 #define BNX2_RPM_RC_CNTL_4_COMP_EQUAL_XI (0L<<16)
3545 #define BNX2_RPM_RC_CNTL_4_CMDSEL_XI (0x1fL<<20)
3553 #define BNX2_RPM_RC_VALUE_MASK_4 0x00001924
3554 #define BNX2_RPM_RC_VALUE_MASK_4_VALUE (0xffffL<<0)
3555 #define BNX2_RPM_RC_VALUE_MASK_4_MASK (0xffffL<<16)
3557 #define BNX2_RPM_RC_CNTL_5 0x00001928
3558 #define BNX2_RPM_RC_CNTL_5_A (0x3ffffL<<0)
3559 #define BNX2_RPM_RC_CNTL_5_B (0xfffL<<19)
3560 #define BNX2_RPM_RC_CNTL_5_OFFSET_XI (0xffL<<0)
3561 #define BNX2_RPM_RC_CNTL_5_CLASS_XI (0x7L<<8)
3564 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_XI (0x7L<<13)
3565 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_START_XI (0L<<13)
3572 #define BNX2_RPM_RC_CNTL_5_COMP_XI (0x3L<<16)
3573 #define BNX2_RPM_RC_CNTL_5_COMP_EQUAL_XI (0L<<16)
3579 #define BNX2_RPM_RC_CNTL_5_CMDSEL_XI (0x1fL<<20)
3587 #define BNX2_RPM_RC_VALUE_MASK_5 0x0000192c
3588 #define BNX2_RPM_RC_VALUE_MASK_5_VALUE (0xffffL<<0)
3589 #define BNX2_RPM_RC_VALUE_MASK_5_MASK (0xffffL<<16)
3591 #define BNX2_RPM_RC_CNTL_6 0x00001930
3592 #define BNX2_RPM_RC_CNTL_6_A (0x3ffffL<<0)
3593 #define BNX2_RPM_RC_CNTL_6_B (0xfffL<<19)
3594 #define BNX2_RPM_RC_CNTL_6_OFFSET_XI (0xffL<<0)
3595 #define BNX2_RPM_RC_CNTL_6_CLASS_XI (0x7L<<8)
3598 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_XI (0x7L<<13)
3599 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_START_XI (0L<<13)
3606 #define BNX2_RPM_RC_CNTL_6_COMP_XI (0x3L<<16)
3607 #define BNX2_RPM_RC_CNTL_6_COMP_EQUAL_XI (0L<<16)
3613 #define BNX2_RPM_RC_CNTL_6_CMDSEL_XI (0x1fL<<20)
3621 #define BNX2_RPM_RC_VALUE_MASK_6 0x00001934
3622 #define BNX2_RPM_RC_VALUE_MASK_6_VALUE (0xffffL<<0)
3623 #define BNX2_RPM_RC_VALUE_MASK_6_MASK (0xffffL<<16)
3625 #define BNX2_RPM_RC_CNTL_7 0x00001938
3626 #define BNX2_RPM_RC_CNTL_7_A (0x3ffffL<<0)
3627 #define BNX2_RPM_RC_CNTL_7_B (0xfffL<<19)
3628 #define BNX2_RPM_RC_CNTL_7_OFFSET_XI (0xffL<<0)
3629 #define BNX2_RPM_RC_CNTL_7_CLASS_XI (0x7L<<8)
3632 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_XI (0x7L<<13)
3633 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_START_XI (0L<<13)
3640 #define BNX2_RPM_RC_CNTL_7_COMP_XI (0x3L<<16)
3641 #define BNX2_RPM_RC_CNTL_7_COMP_EQUAL_XI (0L<<16)
3647 #define BNX2_RPM_RC_CNTL_7_CMDSEL_XI (0x1fL<<20)
3655 #define BNX2_RPM_RC_VALUE_MASK_7 0x0000193c
3656 #define BNX2_RPM_RC_VALUE_MASK_7_VALUE (0xffffL<<0)
3657 #define BNX2_RPM_RC_VALUE_MASK_7_MASK (0xffffL<<16)
3659 #define BNX2_RPM_RC_CNTL_8 0x00001940
3660 #define BNX2_RPM_RC_CNTL_8_A (0x3ffffL<<0)
3661 #define BNX2_RPM_RC_CNTL_8_B (0xfffL<<19)
3662 #define BNX2_RPM_RC_CNTL_8_OFFSET_XI (0xffL<<0)
3663 #define BNX2_RPM_RC_CNTL_8_CLASS_XI (0x7L<<8)
3666 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_XI (0x7L<<13)
3667 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_START_XI (0L<<13)
3674 #define BNX2_RPM_RC_CNTL_8_COMP_XI (0x3L<<16)
3675 #define BNX2_RPM_RC_CNTL_8_COMP_EQUAL_XI (0L<<16)
3681 #define BNX2_RPM_RC_CNTL_8_CMDSEL_XI (0x1fL<<20)
3689 #define BNX2_RPM_RC_VALUE_MASK_8 0x00001944
3690 #define BNX2_RPM_RC_VALUE_MASK_8_VALUE (0xffffL<<0)
3691 #define BNX2_RPM_RC_VALUE_MASK_8_MASK (0xffffL<<16)
3693 #define BNX2_RPM_RC_CNTL_9 0x00001948
3694 #define BNX2_RPM_RC_CNTL_9_A (0x3ffffL<<0)
3695 #define BNX2_RPM_RC_CNTL_9_B (0xfffL<<19)
3696 #define BNX2_RPM_RC_CNTL_9_OFFSET_XI (0xffL<<0)
3697 #define BNX2_RPM_RC_CNTL_9_CLASS_XI (0x7L<<8)
3700 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_XI (0x7L<<13)
3701 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_START_XI (0L<<13)
3708 #define BNX2_RPM_RC_CNTL_9_COMP_XI (0x3L<<16)
3709 #define BNX2_RPM_RC_CNTL_9_COMP_EQUAL_XI (0L<<16)
3715 #define BNX2_RPM_RC_CNTL_9_CMDSEL_XI (0x1fL<<20)
3723 #define BNX2_RPM_RC_VALUE_MASK_9 0x0000194c
3724 #define BNX2_RPM_RC_VALUE_MASK_9_VALUE (0xffffL<<0)
3725 #define BNX2_RPM_RC_VALUE_MASK_9_MASK (0xffffL<<16)
3727 #define BNX2_RPM_RC_CNTL_10 0x00001950
3728 #define BNX2_RPM_RC_CNTL_10_A (0x3ffffL<<0)
3729 #define BNX2_RPM_RC_CNTL_10_B (0xfffL<<19)
3730 #define BNX2_RPM_RC_CNTL_10_OFFSET_XI (0xffL<<0)
3731 #define BNX2_RPM_RC_CNTL_10_CLASS_XI (0x7L<<8)
3734 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_XI (0x7L<<13)
3735 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_START_XI (0L<<13)
3742 #define BNX2_RPM_RC_CNTL_10_COMP_XI (0x3L<<16)
3743 #define BNX2_RPM_RC_CNTL_10_COMP_EQUAL_XI (0L<<16)
3749 #define BNX2_RPM_RC_CNTL_10_CMDSEL_XI (0x1fL<<20)
3757 #define BNX2_RPM_RC_VALUE_MASK_10 0x00001954
3758 #define BNX2_RPM_RC_VALUE_MASK_10_VALUE (0xffffL<<0)
3759 #define BNX2_RPM_RC_VALUE_MASK_10_MASK (0xffffL<<16)
3761 #define BNX2_RPM_RC_CNTL_11 0x00001958
3762 #define BNX2_RPM_RC_CNTL_11_A (0x3ffffL<<0)
3763 #define BNX2_RPM_RC_CNTL_11_B (0xfffL<<19)
3764 #define BNX2_RPM_RC_CNTL_11_OFFSET_XI (0xffL<<0)
3765 #define BNX2_RPM_RC_CNTL_11_CLASS_XI (0x7L<<8)
3768 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_XI (0x7L<<13)
3769 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_START_XI (0L<<13)
3776 #define BNX2_RPM_RC_CNTL_11_COMP_XI (0x3L<<16)
3777 #define BNX2_RPM_RC_CNTL_11_COMP_EQUAL_XI (0L<<16)
3783 #define BNX2_RPM_RC_CNTL_11_CMDSEL_XI (0x1fL<<20)
3791 #define BNX2_RPM_RC_VALUE_MASK_11 0x0000195c
3792 #define BNX2_RPM_RC_VALUE_MASK_11_VALUE (0xffffL<<0)
3793 #define BNX2_RPM_RC_VALUE_MASK_11_MASK (0xffffL<<16)
3795 #define BNX2_RPM_RC_CNTL_12 0x00001960
3796 #define BNX2_RPM_RC_CNTL_12_A (0x3ffffL<<0)
3797 #define BNX2_RPM_RC_CNTL_12_B (0xfffL<<19)
3798 #define BNX2_RPM_RC_CNTL_12_OFFSET_XI (0xffL<<0)
3799 #define BNX2_RPM_RC_CNTL_12_CLASS_XI (0x7L<<8)
3802 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_XI (0x7L<<13)
3803 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_START_XI (0L<<13)
3810 #define BNX2_RPM_RC_CNTL_12_COMP_XI (0x3L<<16)
3811 #define BNX2_RPM_RC_CNTL_12_COMP_EQUAL_XI (0L<<16)
3817 #define BNX2_RPM_RC_CNTL_12_CMDSEL_XI (0x1fL<<20)
3825 #define BNX2_RPM_RC_VALUE_MASK_12 0x00001964
3826 #define BNX2_RPM_RC_VALUE_MASK_12_VALUE (0xffffL<<0)
3827 #define BNX2_RPM_RC_VALUE_MASK_12_MASK (0xffffL<<16)
3829 #define BNX2_RPM_RC_CNTL_13 0x00001968
3830 #define BNX2_RPM_RC_CNTL_13_A (0x3ffffL<<0)
3831 #define BNX2_RPM_RC_CNTL_13_B (0xfffL<<19)
3832 #define BNX2_RPM_RC_CNTL_13_OFFSET_XI (0xffL<<0)
3833 #define BNX2_RPM_RC_CNTL_13_CLASS_XI (0x7L<<8)
3836 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_XI (0x7L<<13)
3837 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_START_XI (0L<<13)
3844 #define BNX2_RPM_RC_CNTL_13_COMP_XI (0x3L<<16)
3845 #define BNX2_RPM_RC_CNTL_13_COMP_EQUAL_XI (0L<<16)
3851 #define BNX2_RPM_RC_CNTL_13_CMDSEL_XI (0x1fL<<20)
3859 #define BNX2_RPM_RC_VALUE_MASK_13 0x0000196c
3860 #define BNX2_RPM_RC_VALUE_MASK_13_VALUE (0xffffL<<0)
3861 #define BNX2_RPM_RC_VALUE_MASK_13_MASK (0xffffL<<16)
3863 #define BNX2_RPM_RC_CNTL_14 0x00001970
3864 #define BNX2_RPM_RC_CNTL_14_A (0x3ffffL<<0)
3865 #define BNX2_RPM_RC_CNTL_14_B (0xfffL<<19)
3866 #define BNX2_RPM_RC_CNTL_14_OFFSET_XI (0xffL<<0)
3867 #define BNX2_RPM_RC_CNTL_14_CLASS_XI (0x7L<<8)
3870 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_XI (0x7L<<13)
3871 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_START_XI (0L<<13)
3878 #define BNX2_RPM_RC_CNTL_14_COMP_XI (0x3L<<16)
3879 #define BNX2_RPM_RC_CNTL_14_COMP_EQUAL_XI (0L<<16)
3885 #define BNX2_RPM_RC_CNTL_14_CMDSEL_XI (0x1fL<<20)
3893 #define BNX2_RPM_RC_VALUE_MASK_14 0x00001974
3894 #define BNX2_RPM_RC_VALUE_MASK_14_VALUE (0xffffL<<0)
3895 #define BNX2_RPM_RC_VALUE_MASK_14_MASK (0xffffL<<16)
3897 #define BNX2_RPM_RC_CNTL_15 0x00001978
3898 #define BNX2_RPM_RC_CNTL_15_A (0x3ffffL<<0)
3899 #define BNX2_RPM_RC_CNTL_15_B (0xfffL<<19)
3900 #define BNX2_RPM_RC_CNTL_15_OFFSET_XI (0xffL<<0)
3901 #define BNX2_RPM_RC_CNTL_15_CLASS_XI (0x7L<<8)
3904 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_XI (0x7L<<13)
3905 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_START_XI (0L<<13)
3912 #define BNX2_RPM_RC_CNTL_15_COMP_XI (0x3L<<16)
3913 #define BNX2_RPM_RC_CNTL_15_COMP_EQUAL_XI (0L<<16)
3919 #define BNX2_RPM_RC_CNTL_15_CMDSEL_XI (0x1fL<<20)
3927 #define BNX2_RPM_RC_VALUE_MASK_15 0x0000197c
3928 #define BNX2_RPM_RC_VALUE_MASK_15_VALUE (0xffffL<<0)
3929 #define BNX2_RPM_RC_VALUE_MASK_15_MASK (0xffffL<<16)
3931 #define BNX2_RPM_RC_CONFIG 0x00001980
3932 #define BNX2_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0)
3933 #define BNX2_RPM_RC_CONFIG_RULE_ENABLE_XI (0xfffffL<<0)
3934 #define BNX2_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24)
3937 #define BNX2_RPM_DEBUG0 0x00001984
3938 #define BNX2_RPM_DEBUG0_FM_BCNT (0xffffL<<0)
3954 #define BNX2_RPM_DEBUG1 0x00001988
3955 #define BNX2_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0)
3956 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0)
3957 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0)
3958 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0)
3959 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0)
3960 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0)
3961 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0)
3962 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0)
3963 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0)
3964 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0)
3965 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0)
3966 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0)
3967 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0)
3968 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0)
3969 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0)
3970 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0)
3971 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0)
3972 #define BNX2_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16)
3978 #define BNX2_RPM_DEBUG2 0x0000198c
3979 #define BNX2_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0)
3980 #define BNX2_RPM_DEBUG2_IP_BCNT (0xffL<<16)
3990 #define BNX2_RPM_DEBUG3 0x00001990
3991 #define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0)
3999 #define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16)
4003 #define BNX2_RPM_DEBUG3_FTQ_FSM (0x3L<<24)
4004 #define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24)
4005 #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24)
4006 #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24)
4007 #define BNX2_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26)
4008 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26)
4009 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26)
4010 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26)
4011 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26)
4012 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26)
4013 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26)
4014 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26)
4015 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26)
4017 #define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29)
4020 #define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30)
4021 #define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30)
4024 #define BNX2_RPM_DEBUG4 0x00001994
4025 #define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0)
4026 #define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25)
4027 #define BNX2_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28)
4030 #define BNX2_RPM_DEBUG5 0x00001998
4031 #define BNX2_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0)
4032 #define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5)
4033 #define BNX2_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10)
4034 #define BNX2_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15)
4048 #define BNX2_RPM_DEBUG6 0x0000199c
4049 #define BNX2_RPM_DEBUG6_ACPI_VEC (0xffffL<<0)
4050 #define BNX2_RPM_DEBUG6_VEC (0xffffL<<16)
4052 #define BNX2_RPM_DEBUG7 0x000019a0
4053 #define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0)
4055 #define BNX2_RPM_DEBUG8 0x000019a4
4056 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0)
4057 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0)
4058 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0)
4059 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0)
4060 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0)
4061 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0)
4062 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0)
4063 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0)
4064 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0)
4065 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0)
4066 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0)
4067 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0)
4080 #define BNX2_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16)
4081 #define BNX2_RPM_DEBUG8_BYTE_CTR (0xffL<<24)
4083 #define BNX2_RPM_DEBUG9 0x000019a8
4084 #define BNX2_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0)
4086 #define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4)
4091 #define BNX2_RPM_DEBUG9_BEMEM_R_XI (0x1fL<<0)
4095 #define BNX2_RPM_DEBUG9_WD64_CT_XI (0x1fL<<8)
4096 #define BNX2_RPM_DEBUG9_EOF_VLDBYTE_XI (0x7L<<13)
4097 #define BNX2_RPM_DEBUG9_ACPI_RDE_PAT_ID_XI (0xfL<<16)
4098 #define BNX2_RPM_DEBUG9_CALCRC_RESULT_XI (0x3ffL<<20)
4102 #define BNX2_RPM_ACPI_DBG_BUF_W00 0x000019c0
4103 #define BNX2_RPM_ACPI_DBG_BUF_W01 0x000019c4
4104 #define BNX2_RPM_ACPI_DBG_BUF_W02 0x000019c8
4105 #define BNX2_RPM_ACPI_DBG_BUF_W03 0x000019cc
4106 #define BNX2_RPM_ACPI_DBG_BUF_W10 0x000019d0
4107 #define BNX2_RPM_ACPI_DBG_BUF_W11 0x000019d4
4108 #define BNX2_RPM_ACPI_DBG_BUF_W12 0x000019d8
4109 #define BNX2_RPM_ACPI_DBG_BUF_W13 0x000019dc
4110 #define BNX2_RPM_ACPI_DBG_BUF_W20 0x000019e0
4111 #define BNX2_RPM_ACPI_DBG_BUF_W21 0x000019e4
4112 #define BNX2_RPM_ACPI_DBG_BUF_W22 0x000019e8
4113 #define BNX2_RPM_ACPI_DBG_BUF_W23 0x000019ec
4114 #define BNX2_RPM_ACPI_DBG_BUF_W30 0x000019f0
4115 #define BNX2_RPM_ACPI_DBG_BUF_W31 0x000019f4
4116 #define BNX2_RPM_ACPI_DBG_BUF_W32 0x000019f8
4117 #define BNX2_RPM_ACPI_DBG_BUF_W33 0x000019fc
4118 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL 0x00001a00
4119 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_BYTE_ADDRESS (0xffffL<<0)
4125 #define BNX2_RPM_ACPI_PATTERN_CTRL 0x00001a04
4126 #define BNX2_RPM_ACPI_PATTERN_CTRL_PATTERN_ID (0xfL<<0)
4130 #define BNX2_RPM_ACPI_DATA 0x00001a08
4131 #define BNX2_RPM_ACPI_DATA_PATTERN_BE (0xffffffffL<<0)
4133 #define BNX2_RPM_ACPI_PATTERN_LEN0 0x00001a0c
4134 #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN3 (0xffL<<0)
4135 #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN2 (0xffL<<8)
4136 #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN1 (0xffL<<16)
4137 #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN0 (0xffL<<24)
4139 #define BNX2_RPM_ACPI_PATTERN_LEN1 0x00001a10
4140 #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN7 (0xffL<<0)
4141 #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN6 (0xffL<<8)
4142 #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN5 (0xffL<<16)
4143 #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN4 (0xffL<<24)
4145 #define BNX2_RPM_ACPI_PATTERN_CRC0 0x00001a18
4146 #define BNX2_RPM_ACPI_PATTERN_CRC0_PATTERN_CRC0 (0xffffffffL<<0)
4148 #define BNX2_RPM_ACPI_PATTERN_CRC1 0x00001a1c
4149 #define BNX2_RPM_ACPI_PATTERN_CRC1_PATTERN_CRC1 (0xffffffffL<<0)
4151 #define BNX2_RPM_ACPI_PATTERN_CRC2 0x00001a20
4152 #define BNX2_RPM_ACPI_PATTERN_CRC2_PATTERN_CRC2 (0xffffffffL<<0)
4154 #define BNX2_RPM_ACPI_PATTERN_CRC3 0x00001a24
4155 #define BNX2_RPM_ACPI_PATTERN_CRC3_PATTERN_CRC3 (0xffffffffL<<0)
4157 #define BNX2_RPM_ACPI_PATTERN_CRC4 0x00001a28
4158 #define BNX2_RPM_ACPI_PATTERN_CRC4_PATTERN_CRC4 (0xffffffffL<<0)
4160 #define BNX2_RPM_ACPI_PATTERN_CRC5 0x00001a2c
4161 #define BNX2_RPM_ACPI_PATTERN_CRC5_PATTERN_CRC5 (0xffffffffL<<0)
4163 #define BNX2_RPM_ACPI_PATTERN_CRC6 0x00001a30
4164 #define BNX2_RPM_ACPI_PATTERN_CRC6_PATTERN_CRC6 (0xffffffffL<<0)
4166 #define BNX2_RPM_ACPI_PATTERN_CRC7 0x00001a34
4167 #define BNX2_RPM_ACPI_PATTERN_CRC7_PATTERN_CRC7 (0xffffffffL<<0)
4172 * offset: 0x2000
4174 #define BNX2_RLUP_RSS_CONFIG 0x0000201c
4175 #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_XI (0x3L<<0)
4176 #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI (0L<<0)
4177 #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI (1L<<0)
4178 #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_IP_ONLY_XI (2L<<0)
4179 #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_RES_XI (3L<<0)
4180 #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_XI (0x3L<<2)
4181 #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI (0L<<2)
4186 #define BNX2_RLUP_RSS_COMMAND 0x00002048
4187 #define BNX2_RLUP_RSS_COMMAND_RSS_IND_TABLE_ADDR (0xfUL<<0)
4188 #define BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK (0xffUL<<4)
4191 #define BNX2_RLUP_RSS_COMMAND_HASH_MASK (0x7UL<<14)
4193 #define BNX2_RLUP_RSS_DATA 0x0000204c
4198 * offset: 0x200000
4200 #define BNX2_RBUF_COMMAND 0x00200000
4201 #define BNX2_RBUF_COMMAND_ENABLED (1L<<0)
4212 #define BNX2_RBUF_STATUS1 0x00200004
4213 #define BNX2_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0)
4215 #define BNX2_RBUF_STATUS2 0x00200008
4216 #define BNX2_RBUF_STATUS2_FREE_TAIL (0x1ffL<<0)
4217 #define BNX2_RBUF_STATUS2_FREE_HEAD (0x1ffL<<16)
4219 #define BNX2_RBUF_CONFIG 0x0020000c
4220 #define BNX2_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0)
4223 #define BNX2_RBUF_CONFIG_XON_TRIP (0x3ffL<<16)
4230 #define BNX2_RBUF_FW_BUF_ALLOC 0x00200010
4231 #define BNX2_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7)
4235 #define BNX2_RBUF_FW_BUF_FREE 0x00200014
4236 #define BNX2_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0)
4237 #define BNX2_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7)
4238 #define BNX2_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16)
4242 #define BNX2_RBUF_FW_BUF_SEL 0x00200018
4243 #define BNX2_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0)
4244 #define BNX2_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7)
4245 #define BNX2_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16)
4248 #define BNX2_RBUF_CONFIG2 0x0020001c
4249 #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0)
4252 #define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16)
4259 #define BNX2_RBUF_CONFIG3 0x00200020
4260 #define BNX2_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0)
4263 #define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16)
4270 #define BNX2_RBUF_PKT_DATA 0x00208000
4271 #define BNX2_RBUF_CLIST_DATA 0x00210000
4272 #define BNX2_RBUF_BUF_DATA 0x00220000
4277 * offset: 0x2800
4279 #define BNX2_RV2P_COMMAND 0x00002800
4280 #define BNX2_RV2P_COMMAND_ENABLED (1L<<0)
4293 #define BNX2_RV2P_STATUS 0x00002804
4294 #define BNX2_RV2P_STATUS_ALWAYS_0 (1L<<0)
4302 #define BNX2_RV2P_CONFIG 0x00002808
4303 #define BNX2_RV2P_CONFIG_STALL_PROC1 (1L<<0)
4317 #define BNX2_RV2P_CONFIG_PAGE_SIZE (0xfL<<24)
4318 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24)
4332 #define BNX2_RV2P_GEN_BFR_ADDR_0 0x00002810
4333 #define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16)
4335 #define BNX2_RV2P_GEN_BFR_ADDR_1 0x00002814
4336 #define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16)
4338 #define BNX2_RV2P_GEN_BFR_ADDR_2 0x00002818
4339 #define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16)
4341 #define BNX2_RV2P_GEN_BFR_ADDR_3 0x0000281c
4342 #define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16)
4344 #define BNX2_RV2P_INSTR_HIGH 0x00002830
4345 #define BNX2_RV2P_INSTR_HIGH_HIGH (0x1fL<<0)
4347 #define BNX2_RV2P_INSTR_LOW 0x00002834
4348 #define BNX2_RV2P_INSTR_LOW_LOW (0xffffffffL<<0)
4350 #define BNX2_RV2P_PROC1_ADDR_CMD 0x00002838
4351 #define BNX2_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0)
4354 #define BNX2_RV2P_PROC2_ADDR_CMD 0x0000283c
4355 #define BNX2_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0)
4358 #define BNX2_RV2P_PROC1_GRC_DEBUG 0x00002840
4359 #define BNX2_RV2P_PROC2_GRC_DEBUG 0x00002844
4360 #define BNX2_RV2P_GRC_PROC_DEBUG 0x00002848
4361 #define BNX2_RV2P_DEBUG_VECT_PEEK 0x0000284c
4362 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4364 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4365 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4367 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4369 #define BNX2_RV2P_MPFE_PFE_CTL 0x00002afc
4370 #define BNX2_RV2P_MPFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
4371 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE (0xfL<<4)
4372 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
4388 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_COUNT (0xfL<<12)
4389 #define BNX2_RV2P_MPFE_PFE_CTL_OFFSET (0x1ffL<<16)
4391 #define BNX2_RV2P_RV2PPQ 0x00002b40
4392 #define BNX2_RV2P_PFTQ_CMD 0x00002b78
4393 #define BNX2_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0)
4395 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10)
4405 #define BNX2_RV2P_PFTQ_CTL 0x00002b7c
4406 #define BNX2_RV2P_PFTQ_CTL_INTERVENE (1L<<0)
4409 #define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4410 #define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4412 #define BNX2_RV2P_RV2PTQ 0x00002b80
4413 #define BNX2_RV2P_TFTQ_CMD 0x00002bb8
4414 #define BNX2_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0)
4416 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10)
4426 #define BNX2_RV2P_TFTQ_CTL 0x00002bbc
4427 #define BNX2_RV2P_TFTQ_CTL_INTERVENE (1L<<0)
4430 #define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4431 #define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4433 #define BNX2_RV2P_RV2PMQ 0x00002bc0
4434 #define BNX2_RV2P_MFTQ_CMD 0x00002bf8
4435 #define BNX2_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0)
4437 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10)
4447 #define BNX2_RV2P_MFTQ_CTL 0x00002bfc
4448 #define BNX2_RV2P_MFTQ_CTL_INTERVENE (1L<<0)
4451 #define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4452 #define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4458 * offset: 0x3c00
4460 #define BNX2_MQ_COMMAND 0x00003c00
4461 #define BNX2_MQ_COMMAND_ENABLED (1L<<0)
4471 #define BNX2_MQ_STATUS 0x00003c04
4477 #define BNX2_MQ_CONFIG 0x00003c08
4478 #define BNX2_MQ_CONFIG_TX_HIGH_PRI (1L<<0)
4482 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4)
4483 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
4488 #define BNX2_MQ_CONFIG_MAX_DEPTH (0x7fL<<8)
4489 #define BNX2_MQ_CONFIG_CUR_DEPTH (0x7fL<<20)
4491 #define BNX2_MQ_ENQUEUE1 0x00003c0c
4492 #define BNX2_MQ_ENQUEUE1_OFFSET (0x3fL<<2)
4493 #define BNX2_MQ_ENQUEUE1_CID (0x3fffL<<8)
4494 #define BNX2_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24)
4497 #define BNX2_MQ_ENQUEUE2 0x00003c10
4498 #define BNX2_MQ_BAD_WR_ADDR 0x00003c14
4499 #define BNX2_MQ_BAD_RD_ADDR 0x00003c18
4500 #define BNX2_MQ_KNL_BYP_WIND_START 0x00003c1c
4501 #define BNX2_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12)
4503 #define BNX2_MQ_KNL_WIND_END 0x00003c20
4504 #define BNX2_MQ_KNL_WIND_END_VALUE (0xffffffL<<8)
4506 #define BNX2_MQ_KNL_WRITE_MASK1 0x00003c24
4507 #define BNX2_MQ_KNL_TX_MASK1 0x00003c28
4508 #define BNX2_MQ_KNL_CMD_MASK1 0x00003c2c
4509 #define BNX2_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30
4510 #define BNX2_MQ_KNL_RX_V2P_MASK1 0x00003c34
4511 #define BNX2_MQ_KNL_WRITE_MASK2 0x00003c38
4512 #define BNX2_MQ_KNL_TX_MASK2 0x00003c3c
4513 #define BNX2_MQ_KNL_CMD_MASK2 0x00003c40
4514 #define BNX2_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44
4515 #define BNX2_MQ_KNL_RX_V2P_MASK2 0x00003c48
4516 #define BNX2_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c
4517 #define BNX2_MQ_KNL_BYP_TX_MASK1 0x00003c50
4518 #define BNX2_MQ_KNL_BYP_CMD_MASK1 0x00003c54
4519 #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58
4520 #define BNX2_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c
4521 #define BNX2_MQ_KNL_BYP_WRITE_MASK2 0x00003c60
4522 #define BNX2_MQ_KNL_BYP_TX_MASK2 0x00003c64
4523 #define BNX2_MQ_KNL_BYP_CMD_MASK2 0x00003c68
4524 #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c
4525 #define BNX2_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70
4526 #define BNX2_MQ_MEM_WR_ADDR 0x00003c74
4527 #define BNX2_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0)
4529 #define BNX2_MQ_MEM_WR_DATA0 0x00003c78
4530 #define BNX2_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0)
4532 #define BNX2_MQ_MEM_WR_DATA1 0x00003c7c
4533 #define BNX2_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0)
4535 #define BNX2_MQ_MEM_WR_DATA2 0x00003c80
4536 #define BNX2_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0)
4537 #define BNX2_MQ_MEM_WR_DATA2_VALUE_XI (0x7fffffffL<<0)
4539 #define BNX2_MQ_MEM_RD_ADDR 0x00003c84
4540 #define BNX2_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0)
4542 #define BNX2_MQ_MEM_RD_DATA0 0x00003c88
4543 #define BNX2_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0)
4545 #define BNX2_MQ_MEM_RD_DATA1 0x00003c8c
4546 #define BNX2_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0)
4548 #define BNX2_MQ_MEM_RD_DATA2 0x00003c90
4549 #define BNX2_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
4550 #define BNX2_MQ_MEM_RD_DATA2_VALUE_XI (0x7fffffffL<<0)
4552 #define BNX2_MQ_MAP_L2_3 0x00003d2c
4553 #define BNX2_MQ_MAP_L2_3_MQ_OFFSET (0xffL<<0)
4554 #define BNX2_MQ_MAP_L2_3_SZ (0x3L<<8)
4555 #define BNX2_MQ_MAP_L2_3_CTX_OFFSET (0x2ffL<<10)
4556 #define BNX2_MQ_MAP_L2_3_BIN_OFFSET (0x7L<<23)
4557 #define BNX2_MQ_MAP_L2_3_ARM (0x3L<<26)
4558 #define BNX2_MQ_MAP_L2_3_ENA (0x1L<<31)
4559 #define BNX2_MQ_MAP_L2_3_DEFAULT 0x82004646
4561 #define BNX2_MQ_MAP_L2_5 0x00003d34
4562 #define BNX2_MQ_MAP_L2_5_ARM (0x3L<<26)
4566 * offset: 0x4c00
4568 #define BNX2_TSCH_TSS_CFG 0x00004c1c
4569 #define BNX2_TSCH_TSS_CFG_TSS_START_CID (0x7ffL<<8)
4570 #define BNX2_TSCH_TSS_CFG_NUM_OF_TSS_CON (0xfL<<24)
4576 * offset: 0x5000
4578 #define BNX2_TBDR_COMMAND 0x00005000
4579 #define BNX2_TBDR_COMMAND_ENABLE (1L<<0)
4583 #define BNX2_TBDR_STATUS 0x00005004
4584 #define BNX2_TBDR_STATUS_DMA_WAIT (1L<<0)
4592 #define BNX2_TBDR_CONFIG 0x00005008
4593 #define BNX2_TBDR_CONFIG_MAX_BDS (0xffL<<0)
4597 #define BNX2_TBDR_CONFIG_PAGE_SIZE (0xfL<<24)
4598 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24)
4612 #define BNX2_TBDR_DEBUG_VECT_PEEK 0x0000500c
4613 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4615 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4616 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4618 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4620 #define BNX2_TBDR_CKSUM_ERROR_STATUS 0x00005010
4621 #define BNX2_TBDR_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
4622 #define BNX2_TBDR_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
4624 #define BNX2_TBDR_TBDRQ 0x000053c0
4625 #define BNX2_TBDR_FTQ_CMD 0x000053f8
4626 #define BNX2_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0)
4628 #define BNX2_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10)
4638 #define BNX2_TBDR_FTQ_CTL 0x000053fc
4639 #define BNX2_TBDR_FTQ_CTL_INTERVENE (1L<<0)
4642 #define BNX2_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4643 #define BNX2_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4648 * offset: 0x5400
4650 #define BNX2_TBDC_COMMAND 0x5400
4651 #define BNX2_TBDC_COMMAND_CMD_ENABLED (1UL<<0)
4661 #define BNX2_TBDC_STATUS 0x5404
4662 #define BNX2_TBDC_STATUS_FREE_CNT (0x3fUL<<0)
4664 #define BNX2_TBDC_BD_ADDR 0x5424
4666 #define BNX2_TBDC_BIDX 0x542c
4667 #define BNX2_TBDC_BDIDX_BDIDX (0xffffUL<<0)
4668 #define BNX2_TBDC_BDIDX_CMD (0xffUL<<24)
4670 #define BNX2_TBDC_CID 0x5430
4672 #define BNX2_TBDC_CAM_OPCODE 0x5434
4673 #define BNX2_TBDC_CAM_OPCODE_OPCODE (0x7UL<<0)
4674 #define BNX2_TBDC_CAM_OPCODE_OPCODE_SEARCH (0UL<<0)
4675 #define BNX2_TBDC_CAM_OPCODE_OPCODE_CACHE_WRITE (1UL<<0)
4676 #define BNX2_TBDC_CAM_OPCODE_OPCODE_INVALIDATE (2UL<<0)
4677 #define BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_WRITE (4UL<<0)
4678 #define BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ (5UL<<0)
4679 #define BNX2_TBDC_CAM_OPCODE_OPCODE_RAM_WRITE (6UL<<0)
4680 #define BNX2_TBDC_CAM_OPCODE_OPCODE_RAM_READ (7UL<<0)
4685 #define BNX2_TBDC_CAM_OPCODE_CAM_VALIDS (0xffUL<<8)
4690 * offset: 0x5c00
4692 #define BNX2_TDMA_COMMAND 0x00005c00
4693 #define BNX2_TDMA_COMMAND_ENABLED (1L<<0)
4705 #define BNX2_TDMA_STATUS 0x00005c04
4706 #define BNX2_TDMA_STATUS_DMA_WAIT (1L<<0)
4712 #define BNX2_TDMA_STATUS_MAX_IFIFO_DEPTH (0x3fL<<20)
4716 #define BNX2_TDMA_CONFIG 0x00005c08
4717 #define BNX2_TDMA_CONFIG_ONE_DMA (1L<<0)
4719 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN (0x3L<<2)
4720 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_0 (0L<<2)
4724 #define BNX2_TDMA_CONFIG_LIMIT_SZ (0xfL<<4)
4725 #define BNX2_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4)
4726 #define BNX2_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4)
4727 #define BNX2_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4)
4728 #define BNX2_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4)
4729 #define BNX2_TDMA_CONFIG_LINE_SZ (0xfL<<8)
4730 #define BNX2_TDMA_CONFIG_LINE_SZ_64 (0L<<8)
4738 #define BNX2_TDMA_CONFIG_OFIFO_CMP_3 (0L<<19)
4740 #define BNX2_TDMA_CONFIG_FIFO_CMP (0xfL<<20)
4741 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_XI (0x7L<<20)
4742 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_0_XI (0L<<20)
4749 #define BNX2_TDMA_CONFIG_BYTES_OST_XI (0x7L<<24)
4750 #define BNX2_TDMA_CONFIG_BYTES_OST_512_XI (0L<<24)
4757 #define BNX2_TDMA_CONFIG_LCL_MRRS_XI (0x7L<<28)
4758 #define BNX2_TDMA_CONFIG_LCL_MRRS_128_XI (0L<<28)
4766 #define BNX2_TDMA_PAYLOAD_PROD 0x00005c0c
4767 #define BNX2_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3)
4769 #define BNX2_TDMA_DBG_WATCHDOG 0x00005c10
4770 #define BNX2_TDMA_DBG_TRIGGER 0x00005c14
4771 #define BNX2_TDMA_DMAD_FSM 0x00005c80
4772 #define BNX2_TDMA_DMAD_FSM_BD_INVLD (1L<<0)
4773 #define BNX2_TDMA_DMAD_FSM_PUSH (0xfL<<4)
4774 #define BNX2_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8)
4777 #define BNX2_TDMA_DMAD_FSM_DMAD (0x7L<<20)
4778 #define BNX2_TDMA_DMAD_FSM_BD (0xfL<<24)
4780 #define BNX2_TDMA_DMAD_STATUS 0x00005c84
4781 #define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0)
4782 #define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4)
4783 #define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8)
4784 #define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12)
4786 #define BNX2_TDMA_DR_INTF_FSM 0x00005c88
4787 #define BNX2_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0)
4788 #define BNX2_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4)
4789 #define BNX2_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8)
4790 #define BNX2_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12)
4791 #define BNX2_TDMA_DR_INTF_FSM_DMAD (0x7L<<16)
4793 #define BNX2_TDMA_DR_INTF_STATUS 0x00005c8c
4794 #define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0)
4795 #define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4)
4796 #define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8)
4797 #define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12)
4798 #define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16)
4800 #define BNX2_TDMA_PUSH_FSM 0x00005c90
4801 #define BNX2_TDMA_BD_IF_DEBUG 0x00005c94
4802 #define BNX2_TDMA_DMAD_IF_DEBUG 0x00005c98
4803 #define BNX2_TDMA_CTX_IF_DEBUG 0x00005c9c
4804 #define BNX2_TDMA_TPBUF_IF_DEBUG 0x00005ca0
4805 #define BNX2_TDMA_DR_IF_DEBUG 0x00005ca4
4806 #define BNX2_TDMA_TPATQ_IF_DEBUG 0x00005ca8
4807 #define BNX2_TDMA_TDMA_ILOCK_CKSUM 0x00005cac
4808 #define BNX2_TDMA_TDMA_ILOCK_CKSUM_CALCULATED (0xffffL<<0)
4809 #define BNX2_TDMA_TDMA_ILOCK_CKSUM_EXPECTED (0xffffL<<16)
4811 #define BNX2_TDMA_TDMA_PCIE_CKSUM 0x00005cb0
4812 #define BNX2_TDMA_TDMA_PCIE_CKSUM_CALCULATED (0xffffL<<0)
4813 #define BNX2_TDMA_TDMA_PCIE_CKSUM_EXPECTED (0xffffL<<16)
4815 #define BNX2_TDMA_TDMAQ 0x00005fc0
4816 #define BNX2_TDMA_FTQ_CMD 0x00005ff8
4817 #define BNX2_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0)
4819 #define BNX2_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10)
4829 #define BNX2_TDMA_FTQ_CTL 0x00005ffc
4830 #define BNX2_TDMA_FTQ_CTL_INTERVENE (1L<<0)
4833 #define BNX2_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4834 #define BNX2_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4840 * offset: 0x6800
4842 #define BNX2_HC_COMMAND 0x00006800
4843 #define BNX2_HC_COMMAND_ENABLE (1L<<0)
4848 #define BNX2_HC_COMMAND_FORCE_INT (0x3L<<19)
4849 #define BNX2_HC_COMMAND_FORCE_INT_NULL (0L<<19)
4857 #define BNX2_HC_STATUS 0x00006804
4858 #define BNX2_HC_STATUS_MASTER_ABORT (1L<<0)
4869 #define BNX2_HC_CONFIG 0x00006808
4870 #define BNX2_HC_CONFIG_COLLECT_STATS (1L<<0)
4877 #define BNX2_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8)
4882 #define BNX2_HC_CONFIG_PER_COLLECT_LIMIT (0xfL<<20)
4883 #define BNX2_HC_CONFIG_SB_ADDR_INC (0x7L<<24)
4884 #define BNX2_HC_CONFIG_SB_ADDR_INC_64B (0L<<24)
4896 #define BNX2_HC_ATTN_BITS_ENABLE 0x0000680c
4897 #define BNX2_HC_STATUS_ADDR_L 0x00006810
4898 #define BNX2_HC_STATUS_ADDR_H 0x00006814
4899 #define BNX2_HC_STATISTICS_ADDR_L 0x00006818
4900 #define BNX2_HC_STATISTICS_ADDR_H 0x0000681c
4901 #define BNX2_HC_TX_QUICK_CONS_TRIP 0x00006820
4902 #define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
4903 #define BNX2_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16)
4905 #define BNX2_HC_COMP_PROD_TRIP 0x00006824
4906 #define BNX2_HC_COMP_PROD_TRIP_VALUE (0xffL<<0)
4907 #define BNX2_HC_COMP_PROD_TRIP_INT (0xffL<<16)
4909 #define BNX2_HC_RX_QUICK_CONS_TRIP 0x00006828
4910 #define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
4911 #define BNX2_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16)
4913 #define BNX2_HC_RX_TICKS 0x0000682c
4914 #define BNX2_HC_RX_TICKS_VALUE (0x3ffL<<0)
4915 #define BNX2_HC_RX_TICKS_INT (0x3ffL<<16)
4917 #define BNX2_HC_TX_TICKS 0x00006830
4918 #define BNX2_HC_TX_TICKS_VALUE (0x3ffL<<0)
4919 #define BNX2_HC_TX_TICKS_INT (0x3ffL<<16)
4921 #define BNX2_HC_COM_TICKS 0x00006834
4922 #define BNX2_HC_COM_TICKS_VALUE (0x3ffL<<0)
4923 #define BNX2_HC_COM_TICKS_INT (0x3ffL<<16)
4925 #define BNX2_HC_CMD_TICKS 0x00006838
4926 #define BNX2_HC_CMD_TICKS_VALUE (0x3ffL<<0)
4927 #define BNX2_HC_CMD_TICKS_INT (0x3ffL<<16)
4929 #define BNX2_HC_PERIODIC_TICKS 0x0000683c
4930 #define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0)
4931 #define BNX2_HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS (0xffffL<<16)
4933 #define BNX2_HC_STAT_COLLECT_TICKS 0x00006840
4934 #define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4)
4936 #define BNX2_HC_STATS_TICKS 0x00006844
4937 #define BNX2_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8)
4939 #define BNX2_HC_STATS_INTERRUPT_STATUS 0x00006848
4940 #define BNX2_HC_STATS_INTERRUPT_STATUS_SB_STATUS (0x1ffL<<0)
4941 #define BNX2_HC_STATS_INTERRUPT_STATUS_INT_STATUS (0x1ffL<<16)
4943 #define BNX2_HC_STAT_MEM_DATA 0x0000684c
4944 #define BNX2_HC_STAT_GEN_SEL_0 0x00006850
4945 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0)
4946 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0)
4947 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0)
4948 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0)
4949 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0)
4950 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0)
4951 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0)
4952 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0)
4953 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0)
4954 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0)
4955 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0)
4956 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0)
4957 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0)
4958 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0)
4959 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0)
4960 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0)
4961 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0)
4962 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0)
4963 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0)
4964 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0)
4965 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0)
4966 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0)
4967 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0)
4968 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0)
4969 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0)
4970 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0)
4971 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0)
4972 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0)
4973 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0)
4974 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0)
4975 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0)
4976 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0)
4977 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0)
4978 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0)
4979 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0)
4980 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0)
4981 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0)
4982 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0)
4983 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0)
4984 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0)
4985 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0)
4986 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0)
4987 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0)
4988 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0)
4989 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0)
4990 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0)
4991 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0)
4992 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0)
4993 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0)
4994 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0)
4995 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0)
4996 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0)
4997 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0)
4998 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0)
4999 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0)
5000 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0)
5001 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0)
5002 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0)
5003 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0)
5004 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0)
5005 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0)
5006 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0)
5007 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0)
5008 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0)
5009 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0)
5010 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0)
5011 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0)
5012 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0)
5013 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0)
5014 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0)
5015 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0)
5016 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0)
5017 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0)
5018 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0)
5019 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0)
5020 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0)
5021 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0)
5022 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0)
5023 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0)
5024 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0)
5025 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0)
5026 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0)
5027 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0)
5028 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0)
5029 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0)
5030 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0)
5031 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0)
5032 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0)
5033 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0)
5034 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0)
5035 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0)
5036 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0)
5037 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0)
5038 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0)
5039 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0)
5040 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0)
5041 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0)
5042 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0)
5043 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0)
5044 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0)
5045 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0)
5046 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0)
5047 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0)
5048 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0)
5049 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0)
5050 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0)
5051 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0)
5052 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0)
5053 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0)
5054 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0)
5055 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0)
5056 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0)
5057 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0)
5058 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0)
5059 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0)
5060 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0)
5061 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0)
5062 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0)
5063 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0)
5064 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0)
5065 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0)
5066 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0)
5067 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0)
5068 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8)
5069 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16)
5070 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24)
5071 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_XI (0xffL<<0)
5072 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI (52L<<0)
5073 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI (57L<<0)
5074 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI (58L<<0)
5075 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI (85L<<0)
5076 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI (86L<<0)
5077 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI (87L<<0)
5078 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI (88L<<0)
5079 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI (89L<<0)
5080 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI (90L<<0)
5081 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI (91L<<0)
5082 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI (92L<<0)
5083 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI (93L<<0)
5084 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI (94L<<0)
5085 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI (123L<<0)
5086 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI (124L<<0)
5087 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI (125L<<0)
5088 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI (126L<<0)
5089 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI (128L<<0)
5090 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI (129L<<0)
5091 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI (130L<<0)
5092 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI (131L<<0)
5093 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI (132L<<0)
5094 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI (133L<<0)
5095 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI (134L<<0)
5096 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI (135L<<0)
5097 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI (136L<<0)
5098 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI (137L<<0)
5099 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI (138L<<0)
5100 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI (139L<<0)
5101 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI (140L<<0)
5102 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI (141L<<0)
5103 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI (142L<<0)
5104 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI (143L<<0)
5105 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI (144L<<0)
5106 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI (145L<<0)
5107 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI (146L<<0)
5108 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI (147L<<0)
5109 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI (148L<<0)
5110 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI (149L<<0)
5111 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI (150L<<0)
5112 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI (151L<<0)
5113 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI (152L<<0)
5114 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI (153L<<0)
5115 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI (154L<<0)
5116 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI (155L<<0)
5117 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI (156L<<0)
5118 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI (157L<<0)
5119 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI (158L<<0)
5120 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI (159L<<0)
5121 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI (160L<<0)
5122 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI (161L<<0)
5123 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI (162L<<0)
5124 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI (163L<<0)
5125 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI (164L<<0)
5126 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI (165L<<0)
5127 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI (166L<<0)
5128 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI (167L<<0)
5129 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI (168L<<0)
5130 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI (169L<<0)
5131 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI (170L<<0)
5132 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI (171L<<0)
5133 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI (172L<<0)
5134 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI (173L<<0)
5135 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI (174L<<0)
5136 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI (175L<<0)
5137 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI (176L<<0)
5138 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI (177L<<0)
5139 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI (178L<<0)
5140 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1_XI (0xffL<<8)
5141 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2_XI (0xffL<<16)
5142 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3_XI (0xffL<<24)
5144 #define BNX2_HC_STAT_GEN_SEL_1 0x00006854
5145 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0)
5146 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8)
5147 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16)
5148 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24)
5149 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4_XI (0xffL<<0)
5150 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5_XI (0xffL<<8)
5151 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6_XI (0xffL<<16)
5152 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7_XI (0xffL<<24)
5154 #define BNX2_HC_STAT_GEN_SEL_2 0x00006858
5155 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0)
5156 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8)
5157 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16)
5158 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24)
5159 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8_XI (0xffL<<0)
5160 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9_XI (0xffL<<8)
5161 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10_XI (0xffL<<16)
5162 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11_XI (0xffL<<24)
5164 #define BNX2_HC_STAT_GEN_SEL_3 0x0000685c
5165 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0)
5166 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8)
5167 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16)
5168 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24)
5169 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12_XI (0xffL<<0)
5170 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13_XI (0xffL<<8)
5171 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14_XI (0xffL<<16)
5172 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15_XI (0xffL<<24)
5174 #define BNX2_HC_STAT_GEN_STAT0 0x00006888
5175 #define BNX2_HC_STAT_GEN_STAT1 0x0000688c
5176 #define BNX2_HC_STAT_GEN_STAT2 0x00006890
5177 #define BNX2_HC_STAT_GEN_STAT3 0x00006894
5178 #define BNX2_HC_STAT_GEN_STAT4 0x00006898
5179 #define BNX2_HC_STAT_GEN_STAT5 0x0000689c
5180 #define BNX2_HC_STAT_GEN_STAT6 0x000068a0
5181 #define BNX2_HC_STAT_GEN_STAT7 0x000068a4
5182 #define BNX2_HC_STAT_GEN_STAT8 0x000068a8
5183 #define BNX2_HC_STAT_GEN_STAT9 0x000068ac
5184 #define BNX2_HC_STAT_GEN_STAT10 0x000068b0
5185 #define BNX2_HC_STAT_GEN_STAT11 0x000068b4
5186 #define BNX2_HC_STAT_GEN_STAT12 0x000068b8
5187 #define BNX2_HC_STAT_GEN_STAT13 0x000068bc
5188 #define BNX2_HC_STAT_GEN_STAT14 0x000068c0
5189 #define BNX2_HC_STAT_GEN_STAT15 0x000068c4
5190 #define BNX2_HC_STAT_GEN_STAT_AC0 0x000068c8
5191 #define BNX2_HC_STAT_GEN_STAT_AC1 0x000068cc
5192 #define BNX2_HC_STAT_GEN_STAT_AC2 0x000068d0
5193 #define BNX2_HC_STAT_GEN_STAT_AC3 0x000068d4
5194 #define BNX2_HC_STAT_GEN_STAT_AC4 0x000068d8
5195 #define BNX2_HC_STAT_GEN_STAT_AC5 0x000068dc
5196 #define BNX2_HC_STAT_GEN_STAT_AC6 0x000068e0
5197 #define BNX2_HC_STAT_GEN_STAT_AC7 0x000068e4
5198 #define BNX2_HC_STAT_GEN_STAT_AC8 0x000068e8
5199 #define BNX2_HC_STAT_GEN_STAT_AC9 0x000068ec
5200 #define BNX2_HC_STAT_GEN_STAT_AC10 0x000068f0
5201 #define BNX2_HC_STAT_GEN_STAT_AC11 0x000068f4
5202 #define BNX2_HC_STAT_GEN_STAT_AC12 0x000068f8
5203 #define BNX2_HC_STAT_GEN_STAT_AC13 0x000068fc
5204 #define BNX2_HC_STAT_GEN_STAT_AC14 0x00006900
5205 #define BNX2_HC_STAT_GEN_STAT_AC15 0x00006904
5206 #define BNX2_HC_STAT_GEN_STAT_AC 0x000068c8
5207 #define BNX2_HC_VIS 0x00006908
5208 #define BNX2_HC_VIS_STAT_BUILD_STATE (0xfL<<0)
5209 #define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
5210 #define BNX2_HC_VIS_STAT_BUILD_STATE_START (1L<<0)
5211 #define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0)
5212 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0)
5213 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0)
5214 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0)
5215 #define BNX2_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0)
5216 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0)
5217 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0)
5218 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0)
5219 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0)
5220 #define BNX2_HC_VIS_DMA_STAT_STATE (0xfL<<8)
5221 #define BNX2_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8)
5232 #define BNX2_HC_VIS_DMA_MSI_STATE (0x7L<<12)
5233 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15)
5234 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15)
5238 #define BNX2_HC_VIS_1 0x0000690c
5240 #define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4)
5243 #define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5)
5246 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6)
5249 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7)
5251 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17)
5252 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17)
5260 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21)
5261 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21)
5264 #define BNX2_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23)
5266 #define BNX2_HC_VIS_1_STAT_CHAN_ID (0x7L<<24)
5269 #define BNX2_HC_DEBUG_VECT_PEEK 0x00006910
5270 #define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
5272 #define BNX2_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
5273 #define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
5275 #define BNX2_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
5277 #define BNX2_HC_COALESCE_NOW 0x00006914
5278 #define BNX2_HC_COALESCE_NOW_COAL_NOW (0x1ffL<<1)
5279 #define BNX2_HC_COALESCE_NOW_COAL_NOW_WO_INT (0x1ffL<<11)
5280 #define BNX2_HC_COALESCE_NOW_COAL_ON_NXT_EVENT (0x1ffL<<21)
5282 #define BNX2_HC_MSIX_BIT_VECTOR 0x00006918
5283 #define BNX2_HC_MSIX_BIT_VECTOR_VAL (0x1ffL<<0)
5285 #define BNX2_HC_SB_CONFIG_1 0x00006a00
5293 #define BNX2_HC_SB_CONFIG_1_PER_COLLECT_LIMIT (0xfL<<20)
5295 #define BNX2_HC_TX_QUICK_CONS_TRIP_1 0x00006a04
5296 #define BNX2_HC_TX_QUICK_CONS_TRIP_1_VALUE (0xffL<<0)
5297 #define BNX2_HC_TX_QUICK_CONS_TRIP_1_INT (0xffL<<16)
5299 #define BNX2_HC_COMP_PROD_TRIP_1 0x00006a08
5300 #define BNX2_HC_COMP_PROD_TRIP_1_VALUE (0xffL<<0)
5301 #define BNX2_HC_COMP_PROD_TRIP_1_INT (0xffL<<16)
5303 #define BNX2_HC_RX_QUICK_CONS_TRIP_1 0x00006a0c
5304 #define BNX2_HC_RX_QUICK_CONS_TRIP_1_VALUE (0xffL<<0)
5305 #define BNX2_HC_RX_QUICK_CONS_TRIP_1_INT (0xffL<<16)
5307 #define BNX2_HC_RX_TICKS_1 0x00006a10
5308 #define BNX2_HC_RX_TICKS_1_VALUE (0x3ffL<<0)
5309 #define BNX2_HC_RX_TICKS_1_INT (0x3ffL<<16)
5311 #define BNX2_HC_TX_TICKS_1 0x00006a14
5312 #define BNX2_HC_TX_TICKS_1_VALUE (0x3ffL<<0)
5313 #define BNX2_HC_TX_TICKS_1_INT (0x3ffL<<16)
5315 #define BNX2_HC_COM_TICKS_1 0x00006a18
5316 #define BNX2_HC_COM_TICKS_1_VALUE (0x3ffL<<0)
5317 #define BNX2_HC_COM_TICKS_1_INT (0x3ffL<<16)
5319 #define BNX2_HC_CMD_TICKS_1 0x00006a1c
5320 #define BNX2_HC_CMD_TICKS_1_VALUE (0x3ffL<<0)
5321 #define BNX2_HC_CMD_TICKS_1_INT (0x3ffL<<16)
5323 #define BNX2_HC_PERIODIC_TICKS_1 0x00006a20
5324 #define BNX2_HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS (0xffffL<<0)
5325 #define BNX2_HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5327 #define BNX2_HC_SB_CONFIG_2 0x00006a24
5335 #define BNX2_HC_SB_CONFIG_2_PER_COLLECT_LIMIT (0xfL<<20)
5337 #define BNX2_HC_TX_QUICK_CONS_TRIP_2 0x00006a28
5338 #define BNX2_HC_TX_QUICK_CONS_TRIP_2_VALUE (0xffL<<0)
5339 #define BNX2_HC_TX_QUICK_CONS_TRIP_2_INT (0xffL<<16)
5341 #define BNX2_HC_COMP_PROD_TRIP_2 0x00006a2c
5342 #define BNX2_HC_COMP_PROD_TRIP_2_VALUE (0xffL<<0)
5343 #define BNX2_HC_COMP_PROD_TRIP_2_INT (0xffL<<16)
5345 #define BNX2_HC_RX_QUICK_CONS_TRIP_2 0x00006a30
5346 #define BNX2_HC_RX_QUICK_CONS_TRIP_2_VALUE (0xffL<<0)
5347 #define BNX2_HC_RX_QUICK_CONS_TRIP_2_INT (0xffL<<16)
5349 #define BNX2_HC_RX_TICKS_2 0x00006a34
5350 #define BNX2_HC_RX_TICKS_2_VALUE (0x3ffL<<0)
5351 #define BNX2_HC_RX_TICKS_2_INT (0x3ffL<<16)
5353 #define BNX2_HC_TX_TICKS_2 0x00006a38
5354 #define BNX2_HC_TX_TICKS_2_VALUE (0x3ffL<<0)
5355 #define BNX2_HC_TX_TICKS_2_INT (0x3ffL<<16)
5357 #define BNX2_HC_COM_TICKS_2 0x00006a3c
5358 #define BNX2_HC_COM_TICKS_2_VALUE (0x3ffL<<0)
5359 #define BNX2_HC_COM_TICKS_2_INT (0x3ffL<<16)
5361 #define BNX2_HC_CMD_TICKS_2 0x00006a40
5362 #define BNX2_HC_CMD_TICKS_2_VALUE (0x3ffL<<0)
5363 #define BNX2_HC_CMD_TICKS_2_INT (0x3ffL<<16)
5365 #define BNX2_HC_PERIODIC_TICKS_2 0x00006a44
5366 #define BNX2_HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS (0xffffL<<0)
5367 #define BNX2_HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5369 #define BNX2_HC_SB_CONFIG_3 0x00006a48
5377 #define BNX2_HC_SB_CONFIG_3_PER_COLLECT_LIMIT (0xfL<<20)
5379 #define BNX2_HC_TX_QUICK_CONS_TRIP_3 0x00006a4c
5380 #define BNX2_HC_TX_QUICK_CONS_TRIP_3_VALUE (0xffL<<0)
5381 #define BNX2_HC_TX_QUICK_CONS_TRIP_3_INT (0xffL<<16)
5383 #define BNX2_HC_COMP_PROD_TRIP_3 0x00006a50
5384 #define BNX2_HC_COMP_PROD_TRIP_3_VALUE (0xffL<<0)
5385 #define BNX2_HC_COMP_PROD_TRIP_3_INT (0xffL<<16)
5387 #define BNX2_HC_RX_QUICK_CONS_TRIP_3 0x00006a54
5388 #define BNX2_HC_RX_QUICK_CONS_TRIP_3_VALUE (0xffL<<0)
5389 #define BNX2_HC_RX_QUICK_CONS_TRIP_3_INT (0xffL<<16)
5391 #define BNX2_HC_RX_TICKS_3 0x00006a58
5392 #define BNX2_HC_RX_TICKS_3_VALUE (0x3ffL<<0)
5393 #define BNX2_HC_RX_TICKS_3_INT (0x3ffL<<16)
5395 #define BNX2_HC_TX_TICKS_3 0x00006a5c
5396 #define BNX2_HC_TX_TICKS_3_VALUE (0x3ffL<<0)
5397 #define BNX2_HC_TX_TICKS_3_INT (0x3ffL<<16)
5399 #define BNX2_HC_COM_TICKS_3 0x00006a60
5400 #define BNX2_HC_COM_TICKS_3_VALUE (0x3ffL<<0)
5401 #define BNX2_HC_COM_TICKS_3_INT (0x3ffL<<16)
5403 #define BNX2_HC_CMD_TICKS_3 0x00006a64
5404 #define BNX2_HC_CMD_TICKS_3_VALUE (0x3ffL<<0)
5405 #define BNX2_HC_CMD_TICKS_3_INT (0x3ffL<<16)
5407 #define BNX2_HC_PERIODIC_TICKS_3 0x00006a68
5408 #define BNX2_HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS (0xffffL<<0)
5409 #define BNX2_HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5411 #define BNX2_HC_SB_CONFIG_4 0x00006a6c
5419 #define BNX2_HC_SB_CONFIG_4_PER_COLLECT_LIMIT (0xfL<<20)
5421 #define BNX2_HC_TX_QUICK_CONS_TRIP_4 0x00006a70
5422 #define BNX2_HC_TX_QUICK_CONS_TRIP_4_VALUE (0xffL<<0)
5423 #define BNX2_HC_TX_QUICK_CONS_TRIP_4_INT (0xffL<<16)
5425 #define BNX2_HC_COMP_PROD_TRIP_4 0x00006a74
5426 #define BNX2_HC_COMP_PROD_TRIP_4_VALUE (0xffL<<0)
5427 #define BNX2_HC_COMP_PROD_TRIP_4_INT (0xffL<<16)
5429 #define BNX2_HC_RX_QUICK_CONS_TRIP_4 0x00006a78
5430 #define BNX2_HC_RX_QUICK_CONS_TRIP_4_VALUE (0xffL<<0)
5431 #define BNX2_HC_RX_QUICK_CONS_TRIP_4_INT (0xffL<<16)
5433 #define BNX2_HC_RX_TICKS_4 0x00006a7c
5434 #define BNX2_HC_RX_TICKS_4_VALUE (0x3ffL<<0)
5435 #define BNX2_HC_RX_TICKS_4_INT (0x3ffL<<16)
5437 #define BNX2_HC_TX_TICKS_4 0x00006a80
5438 #define BNX2_HC_TX_TICKS_4_VALUE (0x3ffL<<0)
5439 #define BNX2_HC_TX_TICKS_4_INT (0x3ffL<<16)
5441 #define BNX2_HC_COM_TICKS_4 0x00006a84
5442 #define BNX2_HC_COM_TICKS_4_VALUE (0x3ffL<<0)
5443 #define BNX2_HC_COM_TICKS_4_INT (0x3ffL<<16)
5445 #define BNX2_HC_CMD_TICKS_4 0x00006a88
5446 #define BNX2_HC_CMD_TICKS_4_VALUE (0x3ffL<<0)
5447 #define BNX2_HC_CMD_TICKS_4_INT (0x3ffL<<16)
5449 #define BNX2_HC_PERIODIC_TICKS_4 0x00006a8c
5450 #define BNX2_HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS (0xffffL<<0)
5451 #define BNX2_HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5453 #define BNX2_HC_SB_CONFIG_5 0x00006a90
5461 #define BNX2_HC_SB_CONFIG_5_PER_COLLECT_LIMIT (0xfL<<20)
5463 #define BNX2_HC_TX_QUICK_CONS_TRIP_5 0x00006a94
5464 #define BNX2_HC_TX_QUICK_CONS_TRIP_5_VALUE (0xffL<<0)
5465 #define BNX2_HC_TX_QUICK_CONS_TRIP_5_INT (0xffL<<16)
5467 #define BNX2_HC_COMP_PROD_TRIP_5 0x00006a98
5468 #define BNX2_HC_COMP_PROD_TRIP_5_VALUE (0xffL<<0)
5469 #define BNX2_HC_COMP_PROD_TRIP_5_INT (0xffL<<16)
5471 #define BNX2_HC_RX_QUICK_CONS_TRIP_5 0x00006a9c
5472 #define BNX2_HC_RX_QUICK_CONS_TRIP_5_VALUE (0xffL<<0)
5473 #define BNX2_HC_RX_QUICK_CONS_TRIP_5_INT (0xffL<<16)
5475 #define BNX2_HC_RX_TICKS_5 0x00006aa0
5476 #define BNX2_HC_RX_TICKS_5_VALUE (0x3ffL<<0)
5477 #define BNX2_HC_RX_TICKS_5_INT (0x3ffL<<16)
5479 #define BNX2_HC_TX_TICKS_5 0x00006aa4
5480 #define BNX2_HC_TX_TICKS_5_VALUE (0x3ffL<<0)
5481 #define BNX2_HC_TX_TICKS_5_INT (0x3ffL<<16)
5483 #define BNX2_HC_COM_TICKS_5 0x00006aa8
5484 #define BNX2_HC_COM_TICKS_5_VALUE (0x3ffL<<0)
5485 #define BNX2_HC_COM_TICKS_5_INT (0x3ffL<<16)
5487 #define BNX2_HC_CMD_TICKS_5 0x00006aac
5488 #define BNX2_HC_CMD_TICKS_5_VALUE (0x3ffL<<0)
5489 #define BNX2_HC_CMD_TICKS_5_INT (0x3ffL<<16)
5491 #define BNX2_HC_PERIODIC_TICKS_5 0x00006ab0
5492 #define BNX2_HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS (0xffffL<<0)
5493 #define BNX2_HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5495 #define BNX2_HC_SB_CONFIG_6 0x00006ab4
5503 #define BNX2_HC_SB_CONFIG_6_PER_COLLECT_LIMIT (0xfL<<20)
5505 #define BNX2_HC_TX_QUICK_CONS_TRIP_6 0x00006ab8
5506 #define BNX2_HC_TX_QUICK_CONS_TRIP_6_VALUE (0xffL<<0)
5507 #define BNX2_HC_TX_QUICK_CONS_TRIP_6_INT (0xffL<<16)
5509 #define BNX2_HC_COMP_PROD_TRIP_6 0x00006abc
5510 #define BNX2_HC_COMP_PROD_TRIP_6_VALUE (0xffL<<0)
5511 #define BNX2_HC_COMP_PROD_TRIP_6_INT (0xffL<<16)
5513 #define BNX2_HC_RX_QUICK_CONS_TRIP_6 0x00006ac0
5514 #define BNX2_HC_RX_QUICK_CONS_TRIP_6_VALUE (0xffL<<0)
5515 #define BNX2_HC_RX_QUICK_CONS_TRIP_6_INT (0xffL<<16)
5517 #define BNX2_HC_RX_TICKS_6 0x00006ac4
5518 #define BNX2_HC_RX_TICKS_6_VALUE (0x3ffL<<0)
5519 #define BNX2_HC_RX_TICKS_6_INT (0x3ffL<<16)
5521 #define BNX2_HC_TX_TICKS_6 0x00006ac8
5522 #define BNX2_HC_TX_TICKS_6_VALUE (0x3ffL<<0)
5523 #define BNX2_HC_TX_TICKS_6_INT (0x3ffL<<16)
5525 #define BNX2_HC_COM_TICKS_6 0x00006acc
5526 #define BNX2_HC_COM_TICKS_6_VALUE (0x3ffL<<0)
5527 #define BNX2_HC_COM_TICKS_6_INT (0x3ffL<<16)
5529 #define BNX2_HC_CMD_TICKS_6 0x00006ad0
5530 #define BNX2_HC_CMD_TICKS_6_VALUE (0x3ffL<<0)
5531 #define BNX2_HC_CMD_TICKS_6_INT (0x3ffL<<16)
5533 #define BNX2_HC_PERIODIC_TICKS_6 0x00006ad4
5534 #define BNX2_HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS (0xffffL<<0)
5535 #define BNX2_HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5537 #define BNX2_HC_SB_CONFIG_7 0x00006ad8
5545 #define BNX2_HC_SB_CONFIG_7_PER_COLLECT_LIMIT (0xfL<<20)
5547 #define BNX2_HC_TX_QUICK_CONS_TRIP_7 0x00006adc
5548 #define BNX2_HC_TX_QUICK_CONS_TRIP_7_VALUE (0xffL<<0)
5549 #define BNX2_HC_TX_QUICK_CONS_TRIP_7_INT (0xffL<<16)
5551 #define BNX2_HC_COMP_PROD_TRIP_7 0x00006ae0
5552 #define BNX2_HC_COMP_PROD_TRIP_7_VALUE (0xffL<<0)
5553 #define BNX2_HC_COMP_PROD_TRIP_7_INT (0xffL<<16)
5555 #define BNX2_HC_RX_QUICK_CONS_TRIP_7 0x00006ae4
5556 #define BNX2_HC_RX_QUICK_CONS_TRIP_7_VALUE (0xffL<<0)
5557 #define BNX2_HC_RX_QUICK_CONS_TRIP_7_INT (0xffL<<16)
5559 #define BNX2_HC_RX_TICKS_7 0x00006ae8
5560 #define BNX2_HC_RX_TICKS_7_VALUE (0x3ffL<<0)
5561 #define BNX2_HC_RX_TICKS_7_INT (0x3ffL<<16)
5563 #define BNX2_HC_TX_TICKS_7 0x00006aec
5564 #define BNX2_HC_TX_TICKS_7_VALUE (0x3ffL<<0)
5565 #define BNX2_HC_TX_TICKS_7_INT (0x3ffL<<16)
5567 #define BNX2_HC_COM_TICKS_7 0x00006af0
5568 #define BNX2_HC_COM_TICKS_7_VALUE (0x3ffL<<0)
5569 #define BNX2_HC_COM_TICKS_7_INT (0x3ffL<<16)
5571 #define BNX2_HC_CMD_TICKS_7 0x00006af4
5572 #define BNX2_HC_CMD_TICKS_7_VALUE (0x3ffL<<0)
5573 #define BNX2_HC_CMD_TICKS_7_INT (0x3ffL<<16)
5575 #define BNX2_HC_PERIODIC_TICKS_7 0x00006af8
5576 #define BNX2_HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS (0xffffL<<0)
5577 #define BNX2_HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5579 #define BNX2_HC_SB_CONFIG_8 0x00006afc
5587 #define BNX2_HC_SB_CONFIG_8_PER_COLLECT_LIMIT (0xfL<<20)
5589 #define BNX2_HC_TX_QUICK_CONS_TRIP_8 0x00006b00
5590 #define BNX2_HC_TX_QUICK_CONS_TRIP_8_VALUE (0xffL<<0)
5591 #define BNX2_HC_TX_QUICK_CONS_TRIP_8_INT (0xffL<<16)
5593 #define BNX2_HC_COMP_PROD_TRIP_8 0x00006b04
5594 #define BNX2_HC_COMP_PROD_TRIP_8_VALUE (0xffL<<0)
5595 #define BNX2_HC_COMP_PROD_TRIP_8_INT (0xffL<<16)
5597 #define BNX2_HC_RX_QUICK_CONS_TRIP_8 0x00006b08
5598 #define BNX2_HC_RX_QUICK_CONS_TRIP_8_VALUE (0xffL<<0)
5599 #define BNX2_HC_RX_QUICK_CONS_TRIP_8_INT (0xffL<<16)
5601 #define BNX2_HC_RX_TICKS_8 0x00006b0c
5602 #define BNX2_HC_RX_TICKS_8_VALUE (0x3ffL<<0)
5603 #define BNX2_HC_RX_TICKS_8_INT (0x3ffL<<16)
5605 #define BNX2_HC_TX_TICKS_8 0x00006b10
5606 #define BNX2_HC_TX_TICKS_8_VALUE (0x3ffL<<0)
5607 #define BNX2_HC_TX_TICKS_8_INT (0x3ffL<<16)
5609 #define BNX2_HC_COM_TICKS_8 0x00006b14
5610 #define BNX2_HC_COM_TICKS_8_VALUE (0x3ffL<<0)
5611 #define BNX2_HC_COM_TICKS_8_INT (0x3ffL<<16)
5613 #define BNX2_HC_CMD_TICKS_8 0x00006b18
5614 #define BNX2_HC_CMD_TICKS_8_VALUE (0x3ffL<<0)
5615 #define BNX2_HC_CMD_TICKS_8_INT (0x3ffL<<16)
5617 #define BNX2_HC_PERIODIC_TICKS_8 0x00006b1c
5618 #define BNX2_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS (0xffffL<<0)
5619 #define BNX2_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5636 * offset: 0x40000
5638 #define BNX2_TXP_CPU_MODE 0x00045000
5639 #define BNX2_TXP_CPU_MODE_LOCAL_RST (1L<<0)
5651 #define BNX2_TXP_CPU_STATE 0x00045004
5652 #define BNX2_TXP_CPU_STATE_BREAKPOINT (1L<<0)
5667 #define BNX2_TXP_CPU_EVENT_MASK 0x00045008
5668 #define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
5680 #define BNX2_TXP_CPU_PROGRAM_COUNTER 0x0004501c
5681 #define BNX2_TXP_CPU_INSTRUCTION 0x00045020
5682 #define BNX2_TXP_CPU_DATA_ACCESS 0x00045024
5683 #define BNX2_TXP_CPU_INTERRUPT_ENABLE 0x00045028
5684 #define BNX2_TXP_CPU_INTERRUPT_VECTOR 0x0004502c
5685 #define BNX2_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030
5686 #define BNX2_TXP_CPU_HW_BREAKPOINT 0x00045034
5687 #define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5688 #define BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
5690 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK 0x00045038
5691 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
5693 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
5694 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
5696 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
5698 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR 0x00045048
5700 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
5702 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
5704 #define BNX2_TXP_CPU_REG_FILE 0x00045200
5705 #define BNX2_TXP_TXPQ 0x000453c0
5706 #define BNX2_TXP_FTQ_CMD 0x000453f8
5707 #define BNX2_TXP_FTQ_CMD_OFFSET (0x3ffL<<0)
5709 #define BNX2_TXP_FTQ_CMD_WR_TOP_0 (0L<<10)
5719 #define BNX2_TXP_FTQ_CTL 0x000453fc
5720 #define BNX2_TXP_FTQ_CTL_INTERVENE (1L<<0)
5723 #define BNX2_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
5724 #define BNX2_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
5726 #define BNX2_TXP_SCRATCH 0x00060000
5731 * offset: 0x80000
5733 #define BNX2_TPAT_CPU_MODE 0x00085000
5734 #define BNX2_TPAT_CPU_MODE_LOCAL_RST (1L<<0)
5746 #define BNX2_TPAT_CPU_STATE 0x00085004
5747 #define BNX2_TPAT_CPU_STATE_BREAKPOINT (1L<<0)
5762 #define BNX2_TPAT_CPU_EVENT_MASK 0x00085008
5763 #define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
5775 #define BNX2_TPAT_CPU_PROGRAM_COUNTER 0x0008501c
5776 #define BNX2_TPAT_CPU_INSTRUCTION 0x00085020
5777 #define BNX2_TPAT_CPU_DATA_ACCESS 0x00085024
5778 #define BNX2_TPAT_CPU_INTERRUPT_ENABLE 0x00085028
5779 #define BNX2_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c
5780 #define BNX2_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030
5781 #define BNX2_TPAT_CPU_HW_BREAKPOINT 0x00085034
5782 #define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5783 #define BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
5785 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038
5786 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
5788 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
5789 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
5791 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
5793 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048
5795 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
5797 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
5799 #define BNX2_TPAT_CPU_REG_FILE 0x00085200
5800 #define BNX2_TPAT_TPATQ 0x000853c0
5801 #define BNX2_TPAT_FTQ_CMD 0x000853f8
5802 #define BNX2_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0)
5804 #define BNX2_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10)
5814 #define BNX2_TPAT_FTQ_CTL 0x000853fc
5815 #define BNX2_TPAT_FTQ_CTL_INTERVENE (1L<<0)
5818 #define BNX2_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
5819 #define BNX2_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
5821 #define BNX2_TPAT_SCRATCH 0x000a0000
5826 * offset: 0xc0000
5828 #define BNX2_RXP_CPU_MODE 0x000c5000
5829 #define BNX2_RXP_CPU_MODE_LOCAL_RST (1L<<0)
5841 #define BNX2_RXP_CPU_STATE 0x000c5004
5842 #define BNX2_RXP_CPU_STATE_BREAKPOINT (1L<<0)
5857 #define BNX2_RXP_CPU_EVENT_MASK 0x000c5008
5858 #define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
5870 #define BNX2_RXP_CPU_PROGRAM_COUNTER 0x000c501c
5871 #define BNX2_RXP_CPU_INSTRUCTION 0x000c5020
5872 #define BNX2_RXP_CPU_DATA_ACCESS 0x000c5024
5873 #define BNX2_RXP_CPU_INTERRUPT_ENABLE 0x000c5028
5874 #define BNX2_RXP_CPU_INTERRUPT_VECTOR 0x000c502c
5875 #define BNX2_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030
5876 #define BNX2_RXP_CPU_HW_BREAKPOINT 0x000c5034
5877 #define BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5878 #define BNX2_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
5880 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038
5881 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
5883 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
5884 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
5886 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
5888 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048
5890 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
5892 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
5894 #define BNX2_RXP_CPU_REG_FILE 0x000c5200
5895 #define BNX2_RXP_PFE_PFE_CTL 0x000c537c
5896 #define BNX2_RXP_PFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
5897 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE (0xfL<<4)
5898 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
5914 #define BNX2_RXP_PFE_PFE_CTL_PFE_COUNT (0xfL<<12)
5915 #define BNX2_RXP_PFE_PFE_CTL_OFFSET (0x1ffL<<16)
5917 #define BNX2_RXP_RXPCQ 0x000c5380
5918 #define BNX2_RXP_CFTQ_CMD 0x000c53b8
5919 #define BNX2_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0)
5921 #define BNX2_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10)
5931 #define BNX2_RXP_CFTQ_CTL 0x000c53bc
5932 #define BNX2_RXP_CFTQ_CTL_INTERVENE (1L<<0)
5935 #define BNX2_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
5936 #define BNX2_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
5938 #define BNX2_RXP_RXPQ 0x000c53c0
5939 #define BNX2_RXP_FTQ_CMD 0x000c53f8
5940 #define BNX2_RXP_FTQ_CMD_OFFSET (0x3ffL<<0)
5942 #define BNX2_RXP_FTQ_CMD_WR_TOP_0 (0L<<10)
5952 #define BNX2_RXP_FTQ_CTL 0x000c53fc
5953 #define BNX2_RXP_FTQ_CTL_INTERVENE (1L<<0)
5956 #define BNX2_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
5957 #define BNX2_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
5959 #define BNX2_RXP_SCRATCH 0x000e0000
5960 #define BNX2_RXP_SCRATCH_RXP_FLOOD 0x000e0024
5961 #define BNX2_RXP_SCRATCH_RSS_TBL_SZ 0x000e0038
5962 #define BNX2_RXP_SCRATCH_RSS_TBL 0x000e003c
5968 * offset: 0x100000
5970 #define BNX2_COM_CKSUM_ERROR_STATUS 0x00100000
5971 #define BNX2_COM_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
5972 #define BNX2_COM_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
5974 #define BNX2_COM_CPU_MODE 0x00105000
5975 #define BNX2_COM_CPU_MODE_LOCAL_RST (1L<<0)
5987 #define BNX2_COM_CPU_STATE 0x00105004
5988 #define BNX2_COM_CPU_STATE_BREAKPOINT (1L<<0)
6003 #define BNX2_COM_CPU_EVENT_MASK 0x00105008
6004 #define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
6016 #define BNX2_COM_CPU_PROGRAM_COUNTER 0x0010501c
6017 #define BNX2_COM_CPU_INSTRUCTION 0x00105020
6018 #define BNX2_COM_CPU_DATA_ACCESS 0x00105024
6019 #define BNX2_COM_CPU_INTERRUPT_ENABLE 0x00105028
6020 #define BNX2_COM_CPU_INTERRUPT_VECTOR 0x0010502c
6021 #define BNX2_COM_CPU_INTERRUPT_SAVED_PC 0x00105030
6022 #define BNX2_COM_CPU_HW_BREAKPOINT 0x00105034
6023 #define BNX2_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
6024 #define BNX2_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
6026 #define BNX2_COM_CPU_DEBUG_VECT_PEEK 0x00105038
6027 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
6029 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
6030 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
6032 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
6034 #define BNX2_COM_CPU_LAST_BRANCH_ADDR 0x00105048
6036 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
6038 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
6040 #define BNX2_COM_CPU_REG_FILE 0x00105200
6041 #define BNX2_COM_COMTQ_PFE_PFE_CTL 0x001052bc
6042 #define BNX2_COM_COMTQ_PFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
6043 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE (0xfL<<4)
6044 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
6060 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_COUNT (0xfL<<12)
6061 #define BNX2_COM_COMTQ_PFE_PFE_CTL_OFFSET (0x1ffL<<16)
6063 #define BNX2_COM_COMXQ 0x00105340
6064 #define BNX2_COM_COMXQ_FTQ_CMD 0x00105378
6065 #define BNX2_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0)
6067 #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10)
6077 #define BNX2_COM_COMXQ_FTQ_CTL 0x0010537c
6078 #define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0)
6081 #define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
6082 #define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
6084 #define BNX2_COM_COMTQ 0x00105380
6085 #define BNX2_COM_COMTQ_FTQ_CMD 0x001053b8
6086 #define BNX2_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0)
6088 #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10)
6098 #define BNX2_COM_COMTQ_FTQ_CTL 0x001053bc
6099 #define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0)
6102 #define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
6103 #define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
6105 #define BNX2_COM_COMQ 0x001053c0
6106 #define BNX2_COM_COMQ_FTQ_CMD 0x001053f8
6107 #define BNX2_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0)
6109 #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10)
6119 #define BNX2_COM_COMQ_FTQ_CTL 0x001053fc
6120 #define BNX2_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0)
6123 #define BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
6124 #define BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
6126 #define BNX2_COM_SCRATCH 0x00120000
6128 #define BNX2_FW_RX_LOW_LATENCY 0x00120058
6129 #define BNX2_FW_RX_DROP_COUNT 0x00120084
6134 * offset: 0x180000
6136 #define BNX2_CP_CKSUM_ERROR_STATUS 0x00180000
6137 #define BNX2_CP_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
6138 #define BNX2_CP_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
6140 #define BNX2_CP_CPU_MODE 0x00185000
6141 #define BNX2_CP_CPU_MODE_LOCAL_RST (1L<<0)
6153 #define BNX2_CP_CPU_STATE 0x00185004
6154 #define BNX2_CP_CPU_STATE_BREAKPOINT (1L<<0)
6169 #define BNX2_CP_CPU_EVENT_MASK 0x00185008
6170 #define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
6182 #define BNX2_CP_CPU_PROGRAM_COUNTER 0x0018501c
6183 #define BNX2_CP_CPU_INSTRUCTION 0x00185020
6184 #define BNX2_CP_CPU_DATA_ACCESS 0x00185024
6185 #define BNX2_CP_CPU_INTERRUPT_ENABLE 0x00185028
6186 #define BNX2_CP_CPU_INTERRUPT_VECTOR 0x0018502c
6187 #define BNX2_CP_CPU_INTERRUPT_SAVED_PC 0x00185030
6188 #define BNX2_CP_CPU_HW_BREAKPOINT 0x00185034
6189 #define BNX2_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
6190 #define BNX2_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
6192 #define BNX2_CP_CPU_DEBUG_VECT_PEEK 0x00185038
6193 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
6195 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
6196 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
6198 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
6200 #define BNX2_CP_CPU_LAST_BRANCH_ADDR 0x00185048
6202 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
6204 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
6206 #define BNX2_CP_CPU_REG_FILE 0x00185200
6207 #define BNX2_CP_CPQ_PFE_PFE_CTL 0x001853bc
6208 #define BNX2_CP_CPQ_PFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
6209 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE (0xfL<<4)
6210 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
6226 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_COUNT (0xfL<<12)
6227 #define BNX2_CP_CPQ_PFE_PFE_CTL_OFFSET (0x1ffL<<16)
6229 #define BNX2_CP_CPQ 0x001853c0
6230 #define BNX2_CP_CPQ_FTQ_CMD 0x001853f8
6231 #define BNX2_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
6233 #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
6243 #define BNX2_CP_CPQ_FTQ_CTL 0x001853fc
6244 #define BNX2_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0)
6247 #define BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
6248 #define BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
6250 #define BNX2_CP_SCRATCH 0x001a0000
6252 #define BNX2_FW_MAX_ISCSI_CONN 0x001a0080
6257 * offset: 0x140000
6259 #define BNX2_MCP_MCP_CONTROL 0x00140080
6263 #define BNX2_MCP_MCP_ATTENTION_STATUS 0x00140084
6268 #define BNX2_MCP_MCP_HEARTBEAT_CONTROL 0x00140088
6271 #define BNX2_MCP_MCP_HEARTBEAT_STATUS 0x0014008c
6272 #define BNX2_MCP_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD (0x7ffL<<0)
6275 #define BNX2_MCP_MCP_HEARTBEAT 0x00140090
6276 #define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT (0x3fffffffL<<0)
6280 #define BNX2_MCP_WATCHDOG_RESET 0x00140094
6283 #define BNX2_MCP_WATCHDOG_CONTROL 0x00140098
6284 #define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_TIMEOUT (0xfffffffL<<0)
6289 #define BNX2_MCP_ACCESS_LOCK 0x0014009c
6292 #define BNX2_MCP_TOE_ID 0x001400a0
6295 #define BNX2_MCP_MAILBOX_CFG 0x001400a4
6296 #define BNX2_MCP_MAILBOX_CFG_MAILBOX_OFFSET (0x3fffL<<0)
6297 #define BNX2_MCP_MAILBOX_CFG_MAILBOX_SIZE (0xfffL<<20)
6299 #define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC 0x001400a8
6300 #define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET (0x3fffL<<0)
6301 #define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE (0xfffL<<20)
6303 #define BNX2_MCP_MCP_DOORBELL 0x001400ac
6306 #define BNX2_MCP_DRIVER_DOORBELL 0x001400b0
6309 #define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC 0x001400b4
6312 #define BNX2_MCP_CPU_MODE 0x00145000
6313 #define BNX2_MCP_CPU_MODE_LOCAL_RST (1L<<0)
6325 #define BNX2_MCP_CPU_STATE 0x00145004
6326 #define BNX2_MCP_CPU_STATE_BREAKPOINT (1L<<0)
6341 #define BNX2_MCP_CPU_EVENT_MASK 0x00145008
6342 #define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
6354 #define BNX2_MCP_CPU_PROGRAM_COUNTER 0x0014501c
6355 #define BNX2_MCP_CPU_INSTRUCTION 0x00145020
6356 #define BNX2_MCP_CPU_DATA_ACCESS 0x00145024
6357 #define BNX2_MCP_CPU_INTERRUPT_ENABLE 0x00145028
6358 #define BNX2_MCP_CPU_INTERRUPT_VECTOR 0x0014502c
6359 #define BNX2_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030
6360 #define BNX2_MCP_CPU_HW_BREAKPOINT 0x00145034
6361 #define BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
6362 #define BNX2_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
6364 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK 0x00145038
6365 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
6367 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
6368 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
6370 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
6372 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR 0x00145048
6374 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
6376 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
6378 #define BNX2_MCP_CPU_REG_FILE 0x00145200
6379 #define BNX2_MCP_MCPQ 0x001453c0
6380 #define BNX2_MCP_MCPQ_FTQ_CMD 0x001453f8
6381 #define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
6383 #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
6393 #define BNX2_MCP_MCPQ_FTQ_CTL 0x001453fc
6394 #define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0)
6397 #define BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
6398 #define BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
6400 #define BNX2_MCP_ROM 0x00150000
6401 #define BNX2_MCP_SCRATCH 0x00160000
6402 #define BNX2_MCP_STATE_P1 0x0016f9c8
6403 #define BNX2_MCP_STATE_P0 0x0016fdc8
6404 #define BNX2_MCP_STATE_P1_5708 0x001699c8
6405 #define BNX2_MCP_STATE_P0_5708 0x00169dc8
6408 #define BNX2_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000
6409 #define BNX2_SHM_HDR_SIGNATURE_SIG 0x53530000
6410 #define BNX2_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff
6411 #define BNX2_SHM_HDR_SIGNATURE_VER_ONE 0x00000001
6420 /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */
6421 #define PHY_BCM5706_PHY_ID 0x00206160
6423 #define PHY_ID(id) ((id) & 0xfffffff0)
6424 #define PHY_REV_ID(id) ((id) & 0xf)
6428 #define BCM5708S_BMCR_FORCE_2500 0x20
6430 #define BCM5708S_UP1 0xb
6432 #define BCM5708S_UP1_2G5 0x1
6434 #define BCM5708S_BLK_ADDR 0x1f
6436 #define BCM5708S_BLK_ADDR_DIG 0x0000
6437 #define BCM5708S_BLK_ADDR_DIG3 0x0002
6438 #define BCM5708S_BLK_ADDR_TX_MISC 0x0005
6441 #define BCM5708S_1000X_CTL1 0x10
6443 #define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001
6444 #define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010
6446 #define BCM5708S_1000X_CTL2 0x11
6448 #define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001
6450 #define BCM5708S_1000X_STAT1 0x14
6452 #define BCM5708S_1000X_STAT1_SGMII 0x0001
6453 #define BCM5708S_1000X_STAT1_LINK 0x0002
6454 #define BCM5708S_1000X_STAT1_FD 0x0004
6455 #define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018
6456 #define BCM5708S_1000X_STAT1_SPEED_10 0x0000
6457 #define BCM5708S_1000X_STAT1_SPEED_100 0x0008
6458 #define BCM5708S_1000X_STAT1_SPEED_1G 0x0010
6459 #define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018
6460 #define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020
6461 #define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040
6464 #define BCM5708S_DIG_3_0 0x10
6466 #define BCM5708S_DIG_3_0_USE_IEEE 0x0001
6469 #define BCM5708S_TX_ACTL1 0x15
6471 #define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30
6473 #define BCM5708S_TX_ACTL3 0x17
6475 #define MII_BNX2_EXT_STATUS 0x11
6478 #define MII_BNX2_AUX_CTL 0x18
6479 #define AUX_CTL_MISC_CTL 0x7007
6484 #define MII_BNX2_DSP_RW_PORT 0x15
6485 #define MII_BNX2_DSP_ADDRESS 0x17
6486 #define MII_BNX2_DSP_EXPAND_REG 0x0f00
6488 #define MII_EXPAND_REG1_RUDI_C 0x20
6491 #define MII_BNX2_MISC_SHADOW 0x1c
6492 #define MISC_SHDW_AN_DBG 0x6800
6493 #define MISC_SHDW_AN_DBG_NOSYNC 0x0002
6494 #define MISC_SHDW_AN_DBG_RUDI_INVALID 0x0100
6495 #define MISC_SHDW_MODE_CTL 0x7c00
6496 #define MISC_SHDW_MODE_CTL_SIG_DET 0x0010
6498 #define MII_BNX2_BLK_ADDR 0x1f
6499 #define MII_BNX2_BLK_ADDR_IEEE0 0x0000
6500 #define MII_BNX2_BLK_ADDR_GP_STATUS 0x8120
6501 #define MII_BNX2_GP_TOP_AN_STATUS1 0x1b
6502 #define MII_BNX2_GP_TOP_AN_SPEED_MSK 0x3f00
6503 #define MII_BNX2_GP_TOP_AN_SPEED_10 0x0000
6504 #define MII_BNX2_GP_TOP_AN_SPEED_100 0x0100
6505 #define MII_BNX2_GP_TOP_AN_SPEED_1G 0x0200
6506 #define MII_BNX2_GP_TOP_AN_SPEED_2_5G 0x0300
6507 #define MII_BNX2_GP_TOP_AN_SPEED_1GKV 0x0d00
6508 #define MII_BNX2_GP_TOP_AN_FD 0x8
6509 #define MII_BNX2_BLK_ADDR_SERDES_DIG 0x8300
6510 #define MII_BNX2_SERDES_DIG_1000XCTL1 0x10
6511 #define MII_BNX2_SD_1000XCTL1_FIBER 0x01
6512 #define MII_BNX2_SD_1000XCTL1_AUTODET 0x10
6513 #define MII_BNX2_SERDES_DIG_MISC1 0x18
6514 #define MII_BNX2_SD_MISC1_FORCE_MSK 0xf
6515 #define MII_BNX2_SD_MISC1_FORCE_2_5G 0x0
6516 #define MII_BNX2_SD_MISC1_FORCE 0x10
6517 #define MII_BNX2_BLK_ADDR_OVER1G 0x8320
6518 #define MII_BNX2_OVER1G_UP1 0x19
6519 #define MII_BNX2_BLK_ADDR_BAM_NXTPG 0x8350
6520 #define MII_BNX2_BAM_NXTPG_CTL 0x10
6521 #define MII_BNX2_NXTPG_CTL_BAM 0x1
6522 #define MII_BNX2_NXTPG_CTL_T2 0x2
6523 #define MII_BNX2_BLK_ADDR_CL73_USERB0 0x8370
6524 #define MII_BNX2_CL73_BAM_CTL1 0x12
6525 #define MII_BNX2_CL73_BAM_EN 0x8000
6526 #define MII_BNX2_CL73_BAM_STA_MGR_EN 0x4000
6527 #define MII_BNX2_CL73_BAM_NP_AFT_BP_EN 0x2000
6528 #define MII_BNX2_BLK_ADDR_AER 0xffd0
6529 #define MII_BNX2_AER_AER 0x1e
6530 #define MII_BNX2_AER_AER_AN_MMD 0x3800
6531 #define MII_BNX2_BLK_ADDR_COMBO_IEEEB0 0xffe0
6539 #define BNX2_MISC_ENABLE_DEFAULT 0x17ffffff
6600 #define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
6602 #define MAX_CID_CNT 0x4000
6604 #define INVALID_CID_ADDR 0xffffffff
6608 #define RX_CID 0
6666 #define BUFFERED_FLASH_TOTAL_SIZE 0x21000
6693 #define FLASH_BACKUP_STRAP_MASK (0xf << 26)
6702 #define BNX2_NV_BUFFERED 0x00000001
6703 #define BNX2_NV_TRANSLATE 0x00000002
6704 #define BNX2_NV_WREN 0x00000004
6796 #define BNX2_FLAG_PCIX 0x00000001
6797 #define BNX2_FLAG_PCI_32BIT 0x00000002
6798 #define BNX2_FLAG_MSIX_CAP 0x00000004
6799 #define BNX2_FLAG_NO_WOL 0x00000008
6800 #define BNX2_FLAG_USING_MSI 0x00000020
6801 #define BNX2_FLAG_ASF_ENABLE 0x00000040
6802 #define BNX2_FLAG_MSI_CAP 0x00000080
6803 #define BNX2_FLAG_ONE_SHOT_MSI 0x00000100
6804 #define BNX2_FLAG_PCIE 0x00000200
6805 #define BNX2_FLAG_USING_MSIX 0x00000400
6808 #define BNX2_FLAG_JUMBO_BROKEN 0x00000800
6809 #define BNX2_FLAG_CAN_KEEP_VLAN 0x00001000
6810 #define BNX2_FLAG_BROKEN_STATS 0x00002000
6845 #define BNX2_PHY_FLAG_SERDES 0x00000001
6846 #define BNX2_PHY_FLAG_CRC_FIX 0x00000002
6847 #define BNX2_PHY_FLAG_PARALLEL_DETECT 0x00000004
6848 #define BNX2_PHY_FLAG_2_5G_CAPABLE 0x00000008
6849 #define BNX2_PHY_FLAG_INT_MODE_MASK 0x00000300
6850 #define BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING 0x00000100
6851 #define BNX2_PHY_FLAG_INT_MODE_LINK_READY 0x00000200
6852 #define BNX2_PHY_FLAG_DIS_EARLY_DAC 0x00000400
6853 #define BNX2_PHY_FLAG_REMOTE_PHY_CAP 0x00000800
6854 #define BNX2_PHY_FLAG_FORCED_DOWN 0x00001000
6855 #define BNX2_PHY_FLAG_NO_PARALLEL 0x00002000
6856 #define BNX2_PHY_FLAG_MDIX 0x00004000
6866 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
6867 #define BNX2_CHIP(bp) (((bp)->chip_id) & 0xffff0000)
6868 #define BNX2_CHIP_5706 0x57060000
6869 #define BNX2_CHIP_5708 0x57080000
6870 #define BNX2_CHIP_5709 0x57090000
6872 #define BNX2_CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
6873 #define BNX2_CHIP_REV_Ax 0x00000000
6874 #define BNX2_CHIP_REV_Bx 0x00001000
6875 #define BNX2_CHIP_REV_Cx 0x00002000
6877 #define BNX2_CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
6878 #define BNX2_CHIP_BOND(bp) (((bp)->chip_id) & 0x0000000f)
6880 #define BNX2_CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
6881 #define BNX2_CHIP_ID_5706_A0 0x57060000
6882 #define BNX2_CHIP_ID_5706_A1 0x57060010
6883 #define BNX2_CHIP_ID_5706_A2 0x57060020
6884 #define BNX2_CHIP_ID_5708_A0 0x57080000
6885 #define BNX2_CHIP_ID_5708_B0 0x57081000
6886 #define BNX2_CHIP_ID_5708_B1 0x57081010
6887 #define BNX2_CHIP_ID_5709_A0 0x57090000
6888 #define BNX2_CHIP_ID_5709_A1 0x57090010
6891 #define BNX2_CHIP_BOND_SERDES_BIT 0x01
7065 #define RV2P_P1_FIXUP_PAGE_SIZE_IDX 0
7066 #define RV2P_BD_PAGE_SIZE_MSK 0xffff
7069 #define RV2P_PROC1 0
7086 #define BNX2_DRV_RESET_SIGNATURE 0x00000000
7087 #define BNX2_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */
7088 //#define DRV_RESET_SIGNATURE_MAGIC 0x47495352 /* RSIG */
7090 #define BNX2_DRV_MB 0x00000004
7091 #define BNX2_DRV_MSG_CODE 0xff000000
7092 #define BNX2_DRV_MSG_CODE_RESET 0x01000000
7093 #define BNX2_DRV_MSG_CODE_UNLOAD 0x02000000
7094 #define BNX2_DRV_MSG_CODE_SHUTDOWN 0x03000000
7095 #define BNX2_DRV_MSG_CODE_SUSPEND_WOL 0x04000000
7096 #define BNX2_DRV_MSG_CODE_FW_TIMEOUT 0x05000000
7097 #define BNX2_DRV_MSG_CODE_PULSE 0x06000000
7098 #define BNX2_DRV_MSG_CODE_DIAG 0x07000000
7099 #define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000
7100 #define BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000
7101 #define BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE 0x0d000000
7102 #define BNX2_DRV_MSG_CODE_CMD_SET_LINK 0x10000000
7104 #define BNX2_DRV_MSG_DATA 0x00ff0000
7105 #define BNX2_DRV_MSG_DATA_WAIT0 0x00010000
7106 #define BNX2_DRV_MSG_DATA_WAIT1 0x00020000
7107 #define BNX2_DRV_MSG_DATA_WAIT2 0x00030000
7108 #define BNX2_DRV_MSG_DATA_WAIT3 0x00040000
7110 #define BNX2_DRV_MSG_SEQ 0x0000ffff
7112 #define BNX2_FW_MB 0x00000008
7113 #define BNX2_FW_MSG_ACK 0x0000ffff
7114 #define BNX2_FW_MSG_STATUS_MASK 0x00ff0000
7115 #define BNX2_FW_MSG_STATUS_OK 0x00000000
7116 #define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000
7118 #define BNX2_LINK_STATUS 0x0000000c
7119 #define BNX2_LINK_STATUS_INIT_VALUE 0xffffffff
7120 #define BNX2_LINK_STATUS_LINK_UP 0x1
7121 #define BNX2_LINK_STATUS_LINK_DOWN 0x0
7122 #define BNX2_LINK_STATUS_SPEED_MASK 0x1e
7123 #define BNX2_LINK_STATUS_AN_INCOMPLETE (0<<1)
7153 #define BNX2_DRV_PULSE_MB 0x00000010
7154 #define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff
7159 #define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000
7161 #define BNX2_DRV_MB_ARG0 0x00000014
7162 #define BNX2_NETLINK_SET_LINK_SPEED_10HALF (1<<0)
7185 #define BNX2_DEV_INFO_SIGNATURE 0x00000020
7186 #define BNX2_DEV_INFO_SIGNATURE_MAGIC 0x44564900
7187 #define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00
7188 #define BNX2_DEV_INFO_FEATURE_CFG_VALID 0x01
7189 #define BNX2_DEV_INFO_SECONDARY_PORT 0x80
7190 #define BNX2_DEV_INFO_DRV_ALWAYS_ALIVE 0x40
7192 #define BNX2_SHARED_HW_CFG_PART_NUM 0x00000024
7194 #define BNX2_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034
7195 #define BNX2_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000
7196 #define BNX2_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000
7197 #define BNX2_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00
7198 #define BNX2_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff
7200 #define BNX2_SHARED_HW_CFG POWER_CONSUMED 0x00000038
7201 #define BNX2_SHARED_HW_CFG_CONFIG 0x0000003c
7202 #define BNX2_SHARED_HW_CFG_DESIGN_NIC 0
7203 #define BNX2_SHARED_HW_CFG_DESIGN_LOM 0x1
7204 #define BNX2_SHARED_HW_CFG_PHY_COPPER 0
7205 #define BNX2_SHARED_HW_CFG_PHY_FIBER 0x2
7206 #define BNX2_SHARED_HW_CFG_PHY_2_5G 0x20
7207 #define BNX2_SHARED_HW_CFG_PHY_BACKPLANE 0x40
7209 #define BNX2_SHARED_HW_CFG_LED_MODE_MASK 0x300
7210 #define BNX2_SHARED_HW_CFG_LED_MODE_MAC 0
7211 #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1 0x100
7212 #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2 0x200
7213 #define BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX 0x8000
7215 #define BNX2_SHARED_HW_CFG_CONFIG2 0x00000040
7216 #define BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000
7218 #define BNX2_DEV_INFO_BC_REV 0x0000004c
7220 #define BNX2_PORT_HW_CFG_MAC_UPPER 0x00000050
7221 #define BNX2_PORT_HW_CFG_UPPERMAC_MASK 0xffff
7223 #define BNX2_PORT_HW_CFG_MAC_LOWER 0x00000054
7224 #define BNX2_PORT_HW_CFG_CONFIG 0x00000058
7225 #define BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff
7226 #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000
7227 #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000
7228 #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000
7229 #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000
7231 #define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068
7232 #define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c
7233 #define BNX2_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070
7234 #define BNX2_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074
7235 #define BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078
7236 #define BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c
7238 #define BNX2_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4
7240 #define BNX2_DEV_INFO_FORMAT_REV 0x000000c4
7241 #define BNX2_DEV_INFO_FORMAT_REV_MASK 0xff000000
7244 #define BNX2_SHARED_FEATURE 0x000000c8
7245 #define BNX2_SHARED_FEATURE_MASK 0xffffffff
7247 #define BNX2_PORT_FEATURE 0x000000d8
7248 #define BNX2_PORT2_FEATURE 0x00000014c
7249 #define BNX2_PORT_FEATURE_WOL_ENABLED 0x01000000
7250 #define BNX2_PORT_FEATURE_MBA_ENABLED 0x02000000
7251 #define BNX2_PORT_FEATURE_ASF_ENABLED 0x04000000
7252 #define BNX2_PORT_FEATURE_IMD_ENABLED 0x08000000
7253 #define BNX2_PORT_FEATURE_BAR1_SIZE_MASK 0xf
7254 #define BNX2_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0
7255 #define BNX2_PORT_FEATURE_BAR1_SIZE_64K 0x1
7256 #define BNX2_PORT_FEATURE_BAR1_SIZE_128K 0x2
7257 #define BNX2_PORT_FEATURE_BAR1_SIZE_256K 0x3
7258 #define BNX2_PORT_FEATURE_BAR1_SIZE_512K 0x4
7259 #define BNX2_PORT_FEATURE_BAR1_SIZE_1M 0x5
7260 #define BNX2_PORT_FEATURE_BAR1_SIZE_2M 0x6
7261 #define BNX2_PORT_FEATURE_BAR1_SIZE_4M 0x7
7262 #define BNX2_PORT_FEATURE_BAR1_SIZE_8M 0x8
7263 #define BNX2_PORT_FEATURE_BAR1_SIZE_16M 0x9
7264 #define BNX2_PORT_FEATURE_BAR1_SIZE_32M 0xa
7265 #define BNX2_PORT_FEATURE_BAR1_SIZE_64M 0xb
7266 #define BNX2_PORT_FEATURE_BAR1_SIZE_128M 0xc
7267 #define BNX2_PORT_FEATURE_BAR1_SIZE_256M 0xd
7268 #define BNX2_PORT_FEATURE_BAR1_SIZE_512M 0xe
7269 #define BNX2_PORT_FEATURE_BAR1_SIZE_1G 0xf
7271 #define BNX2_PORT_FEATURE_WOL 0xdc
7272 #define BNX2_PORT2_FEATURE_WOL 0x150
7274 #define BNX2_PORT_FEATURE_WOL_DEFAULT_MASK 0x30
7275 #define BNX2_PORT_FEATURE_WOL_DEFAULT_DISABLE 0
7276 #define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10
7277 #define BNX2_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20
7278 #define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30
7279 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf
7280 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0
7287 #define BNX2_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40
7288 #define BNX2_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400
7289 #define BNX2_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800
7291 #define BNX2_PORT_FEATURE_MBA 0xe0
7292 #define BNX2_PORT2_FEATURE_MBA 0x154
7293 #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0
7294 #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3
7295 #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0
7299 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c
7300 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0
7301 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4
7302 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8
7303 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc
7304 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10
7305 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14
7306 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18
7307 #define BNX2_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40
7308 #define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0
7309 #define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80
7311 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00
7312 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0
7313 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100
7314 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200
7315 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300
7316 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400
7317 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500
7318 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600
7319 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700
7320 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800
7321 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900
7322 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00
7323 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00
7324 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00
7325 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00
7326 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00
7327 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00
7329 #define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000
7331 #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000
7332 #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0
7333 #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000
7334 #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000
7335 #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000
7337 #define BNX2_PORT_FEATURE_IMD 0xe4
7338 #define BNX2_PORT2_FEATURE_IMD 0x158
7339 #define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0
7342 #define BNX2_PORT_FEATURE_VLAN 0xe8
7343 #define BNX2_PORT2_FEATURE_VLAN 0x15c
7344 #define BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff
7345 #define BNX2_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000
7347 #define BNX2_MFW_VER_PTR 0x00000014c
7349 #define BNX2_BC_STATE_RESET_TYPE 0x000001c0
7350 #define BNX2_BC_STATE_RESET_TYPE_SIG 0x00005254
7351 #define BNX2_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff
7353 0x00010000)
7355 0x00020000)
7357 0x00030000)
7372 #define BNX2_BC_RESET_TYPE 0x000001c0
7374 #define BNX2_BC_STATE 0x000001c4
7375 #define BNX2_BC_STATE_ERR_MASK 0x0000ff00
7376 #define BNX2_BC_STATE_SIGN 0x42530000
7377 #define BNX2_BC_STATE_SIGN_MASK 0xffff0000
7378 #define BNX2_BC_STATE_BC1_START (BNX2_BC_STATE_SIGN | 0x1)
7379 #define BNX2_BC_STATE_GET_NVM_CFG1 (BNX2_BC_STATE_SIGN | 0x2)
7380 #define BNX2_BC_STATE_PROG_BAR (BNX2_BC_STATE_SIGN | 0x3)
7381 #define BNX2_BC_STATE_INIT_VID (BNX2_BC_STATE_SIGN | 0x4)
7382 #define BNX2_BC_STATE_GET_NVM_CFG2 (BNX2_BC_STATE_SIGN | 0x5)
7383 #define BNX2_BC_STATE_APPLY_WKARND (BNX2_BC_STATE_SIGN | 0x6)
7384 #define BNX2_BC_STATE_LOAD_BC2 (BNX2_BC_STATE_SIGN | 0x7)
7385 #define BNX2_BC_STATE_GOING_BC2 (BNX2_BC_STATE_SIGN | 0x8)
7386 #define BNX2_BC_STATE_GOING_DIAG (BNX2_BC_STATE_SIGN | 0x9)
7387 #define BNX2_BC_STATE_RT_FINAL_INIT (BNX2_BC_STATE_SIGN | 0x81)
7388 #define BNX2_BC_STATE_RT_WKARND (BNX2_BC_STATE_SIGN | 0x82)
7389 #define BNX2_BC_STATE_RT_DRV_PULSE (BNX2_BC_STATE_SIGN | 0x83)
7390 #define BNX2_BC_STATE_RT_FIOEVTS (BNX2_BC_STATE_SIGN | 0x84)
7391 #define BNX2_BC_STATE_RT_DRV_CMD (BNX2_BC_STATE_SIGN | 0x85)
7392 #define BNX2_BC_STATE_RT_LOW_POWER (BNX2_BC_STATE_SIGN | 0x86)
7393 #define BNX2_BC_STATE_RT_SET_WOL (BNX2_BC_STATE_SIGN | 0x87)
7394 #define BNX2_BC_STATE_RT_OTHER_FW (BNX2_BC_STATE_SIGN | 0x88)
7395 #define BNX2_BC_STATE_RT_GOING_D3 (BNX2_BC_STATE_SIGN | 0x89)
7396 #define BNX2_BC_STATE_ERR_BAD_VERSION (BNX2_BC_STATE_SIGN | 0x0100)
7397 #define BNX2_BC_STATE_ERR_BAD_BC2_CRC (BNX2_BC_STATE_SIGN | 0x0200)
7398 #define BNX2_BC_STATE_ERR_BC1_LOOP (BNX2_BC_STATE_SIGN | 0x0300)
7399 #define BNX2_BC_STATE_ERR_UNKNOWN_CMD (BNX2_BC_STATE_SIGN | 0x0400)
7400 #define BNX2_BC_STATE_ERR_DRV_DEAD (BNX2_BC_STATE_SIGN | 0x0500)
7401 #define BNX2_BC_STATE_ERR_NO_RXP (BNX2_BC_STATE_SIGN | 0x0600)
7402 #define BNX2_BC_STATE_ERR_TOO_MANY_RBUF (BNX2_BC_STATE_SIGN | 0x0700)
7404 #define BNX2_BC_STATE_CONDITION 0x000001c8
7405 #define BNX2_CONDITION_MFW_RUN_UNKNOWN 0x00000000
7406 #define BNX2_CONDITION_MFW_RUN_IPMI 0x00002000
7407 #define BNX2_CONDITION_MFW_RUN_UMP 0x00004000
7408 #define BNX2_CONDITION_MFW_RUN_NCSI 0x00006000
7409 #define BNX2_CONDITION_MFW_RUN_NONE 0x0000e000
7410 #define BNX2_CONDITION_MFW_RUN_MASK 0x0000e000
7411 #define BNX2_CONDITION_PM_STATE_MASK 0x00030000
7412 #define BNX2_CONDITION_PM_STATE_FULL 0x00030000
7413 #define BNX2_CONDITION_PM_STATE_PREP 0x00020000
7414 #define BNX2_CONDITION_PM_STATE_UNPREP 0x00010000
7416 #define BNX2_BC_STATE_DEBUG_CMD 0x1dc
7417 #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000
7418 #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000
7419 #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff
7420 #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff
7422 #define BNX2_FW_EVT_CODE_MB 0x354
7423 #define BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT 0x00000000
7424 #define BNX2_FW_EVT_CODE_LINK_EVENT 0x00000001
7426 #define BNX2_DRV_ACK_CAP_MB 0x364
7427 #define BNX2_DRV_ACK_CAP_SIGNATURE 0x35450000
7428 #define BNX2_CAPABILITY_SIGNATURE_MASK 0xFFFF0000
7430 #define BNX2_FW_CAP_MB 0x368
7431 #define BNX2_FW_CAP_SIGNATURE 0xaa550000
7432 #define BNX2_FW_ACK_DRV_SIGNATURE 0x52500000
7433 #define BNX2_FW_CAP_SIGNATURE_MASK 0xffff0000
7434 #define BNX2_FW_CAP_REMOTE_PHY_CAPABLE 0x00000001
7435 #define BNX2_FW_CAP_REMOTE_PHY_PRESENT 0x00000002
7436 #define BNX2_FW_CAP_MFW_CAN_KEEP_VLAN 0x00000008
7437 #define BNX2_FW_CAP_BC_CAN_KEEP_VLAN 0x00000010
7441 #define BNX2_RPHY_SIGNATURE 0x36c
7442 #define BNX2_RPHY_LOAD_SIGNATURE 0x5a5a5a5a
7444 #define BNX2_RPHY_FLAGS 0x370
7445 #define BNX2_RPHY_SERDES_LINK 0x374
7446 #define BNX2_RPHY_COPPER_LINK 0x378
7448 #define BNX2_ISCSI_INITIATOR 0x3dc
7449 #define BNX2_ISCSI_INITIATOR_EN 0x00080000
7451 #define BNX2_ISCSI_MAX_CONN 0x3e4
7452 #define BNX2_ISCSI_MAX_CONN_MASK 0xffff0000
7455 #define HOST_VIEW_SHMEM_BASE 0x167c00