atheros/atlx/atl1.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
4  * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
5  * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
8  * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
82 /* Wake-On-Lan control register */
89 /* WOL Length ( 2 DWORD ) */
215 /* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
265 /* Normal Interrupt mask without RX/TX enabled */
302 #define AUTONEG_ADVERTISE_SPEED_DEFAULT		0x002F	/* All but 1000-Half */
317 	u32 rx_len_err;		/* RX packets with length != actual size */
336 	/* tx */
337 	u32 tx_ok;		/* good TX packets */
338 	u32 tx_bcast;		/* good TX broadcast packets */
339 	u32 tx_mcast;		/* good TX multicast packets */
340 	u32 tx_pause;		/* TX pause frames */
341 	u32 tx_exc_defer;	/* TX packets deferred excessively */
342 	u32 tx_ctrl;		/* TX control frames, excluding pause frames */
343 	u32 tx_defer;		/* TX packets deferred */
345 	u32 tx_sz_64;		/* 64 byte TX packets */
351 	u32 tx_sz_1519_max;	/* 1519 byte to MTU TX packets */
352 	u32 tx_1_col;		/* packets TX after a single collision */
353 	u32 tx_2_col;		/* packets TX after multiple collisions */
354 	u32 tx_late_col;	/* TX packets with late collisions */
355 	u32 tx_abort_col;	/* TX packets aborted w/excessive collisions */
356 	u32 tx_underrun;	/* TX packets aborted due to TX FIFO underrun
360 	u32 tx_len_err;		/* TX packets where length != actual size */
361 	u32 tx_trunc;		/* TX packets truncated due to size > MTU */
431  * The L1 transmit packet descriptor is comprised of four 32-bit words.
434  *	+---------------------------------------+
436  *      +---------------------------------------+
438  *      +---------------------------------------+
440  *      +---------------------------------------+
442  *      +---------------------------------------+
444  * Words 0 and 1 combine to form a 64-bit buffer address.
463  *	10-+ 					10-+
464  *	11 |	IP hdr length (10:13)		11 |	IP hdr length (10:13)
465  *	12 |	(num 32-bit words)		12 |	(num 32-bit words)
466  *	13-+					13-+
467  *	14-+					14	Unused
468  *	15 |	TCP hdr length (14:17)		15	Unused
469  *	16 |	(num 32-bit words)		16-+
470  *	17-+					17 |
472  *	19-+					19 |	Payload offset
476  *	23 |					23-+
477  *	24 |					24-+
484  *	31-+					31-+
573 #define ATL1_GET_DESC(R, i, type)	(&(((type *)((R)->desc))[i]))
586 	unsigned int size;	/* length in bytes */
595 	u16 length;		/* rx buffer length */  member
604 	u16 size;		/* descriptor ring length in bytes */
616 	u16 size;		/* descriptor ring length in bytes */
627 	unsigned int size;	/* descriptor ring length in bytes */
665 	u64 tx_pause;		/* TX pause frames */
666 	u64 excecol;		/* TX packets w/ excessive collisions */
667 	u64 deffer;		/* TX packets deferred */
668 	u64 scc;		/* packets TX after a single collision */
669 	u64 mcc;		/* packets TX after multiple collisions */
670 	u64 latecol;		/* TX packets w/ late collisions */
671 	u64 tx_underrun;	/* TX packets aborted due to TX FIFO underrun
673 	u64 tx_trunc;		/* TX packets truncated due to size > MTU */
690 				 * control in half-duplex mode. In units of
691 				 * 8-bit time */
692 	u8 ipgt;		/* Desired back to back inter-packet gap.
693 				 * The default is 96-bit time */
697 	u8 ipgr1;		/* 64bit Carrier-Sense window */
698 	u8 ipgr2;		/* 96-bit IPG window */
699 	u8 tpd_burst;		/* Number of TPD to prefetch in cache-aligned
700 				 * burst. Each TPD is 16 bytes long */
701 	u8 rfd_burst;		/* Number of RFD to prefetch in cache-aligned
702 				 * burst. Each RFD is 12 bytes long */
705 				 * in a burst. Each RRD is 16 bytes long */
709 	u16 txf_burst;		/* Number of data bytes to read in a cache-
710 				 * aligned burst. Each SRAM entry is 8 bytes */
711 	u16 rx_jumbo_th;	/* Jumbo packet size for non-VLAN packet. VLAN
763 	/* TX */