atheros/atlx/atl1.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
4  * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
5  * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
8  * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
82 /* Wake-On-Lan control register */
89 /* WOL Length ( 2 DWORD ) */
165 /* Rx jumbo packet threshold and rrd  retirement timer */
215 /* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
265 /* Normal Interrupt mask without RX/TX enabled */
302 #define AUTONEG_ADVERTISE_SPEED_DEFAULT		0x002F	/* All but 1000-Half */
310 	/* rx */
311 	u32 rx_ok;		/* good RX packets */
312 	u32 rx_bcast;		/* good RX broadcast packets */
313 	u32 rx_mcast;		/* good RX multicast packets */
314 	u32 rx_pause;		/* RX pause frames */
315 	u32 rx_ctrl;		/* RX control packets other than pause frames */
316 	u32 rx_fcs_err;		/* RX packets with bad FCS */
317 	u32 rx_len_err;		/* RX packets with length != actual size */
319 	u32 rx_runt;		/* RX packets < 64 bytes with good FCS */
320 	u32 rx_frag;		/* RX packets < 64 bytes with bad FCS */
321 	u32 rx_sz_64;		/* 64 byte RX packets */
327 	u32 rx_sz_1519_max;	/* 1519 byte to MTU RX packets */
328 	u32 rx_sz_ov;		/* truncated RX packets > MTU */
329 	u32 rx_rxf_ov;		/* frames dropped due to RX FIFO overflow */
332 	u32 rx_bcast_byte_cnt;	/* RX broadcast bytes, excluding FCS */
333 	u32 rx_mcast_byte_cnt;	/* RX multicast bytes, excluding FCS */
360 	u32 tx_len_err;		/* TX packets where length != actual size */
431  * The L1 transmit packet descriptor is comprised of four 32-bit words.
434  *	+---------------------------------------+
436  *      +---------------------------------------+
438  *      +---------------------------------------+
440  *      +---------------------------------------+
442  *      +---------------------------------------+
444  * Words 0 and 1 combine to form a 64-bit buffer address.
463  *	10-+ 					10-+
464  *	11 |	IP hdr length (10:13)		11 |	IP hdr length (10:13)
465  *	12 |	(num 32-bit words)		12 |	(num 32-bit words)
466  *	13-+					13-+
467  *	14-+					14	Unused
468  *	15 |	TCP hdr length (14:17)		15	Unused
469  *	16 |	(num 32-bit words)		16-+
470  *	17-+					17 |
472  *	19-+					19 |	Payload offset
476  *	23 |					23-+
477  *	24 |					24-+
484  *	31-+					31-+
573 #define ATL1_GET_DESC(R, i, type)	(&(((type *)((R)->desc))[i]))
586 	unsigned int size;	/* length in bytes */
595 	u16 length;		/* rx buffer length */  member
604 	u16 size;		/* descriptor ring length in bytes */
616 	u16 size;		/* descriptor ring length in bytes */
627 	unsigned int size;	/* descriptor ring length in bytes */
690 				 * control in half-duplex mode. In units of
691 				 * 8-bit time */
692 	u8 ipgt;		/* Desired back to back inter-packet gap.
693 				 * The default is 96-bit time */
697 	u8 ipgr1;		/* 64bit Carrier-Sense window */
698 	u8 ipgr2;		/* 96-bit IPG window */
699 	u8 tpd_burst;		/* Number of TPD to prefetch in cache-aligned
700 				 * burst. Each TPD is 16 bytes long */
701 	u8 rfd_burst;		/* Number of RFD to prefetch in cache-aligned
702 				 * burst. Each RFD is 12 bytes long */
705 				 * in a burst. Each RRD is 16 bytes long */
709 	u16 txf_burst;		/* Number of data bytes to read in a cache-
710 				 * aligned burst. Each SRAM entry is 8 bytes */
711 	u16 rx_jumbo_th;	/* Jumbo packet size for non-VLAN packet. VLAN
767 	/* RX */