atheros/atl1c/atl1c_hw.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
6  * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
44 int atl1c_read_phy_core(struct atl1c_hw *hw, bool ext, u8 dev,
46 int atl1c_write_phy_core(struct atl1c_hw *hw, bool ext, u8 dev,
56 /* hw-ids */
152 						 * ->L0s not L1 */
200 						 * serdes, not sw to 25M */
308 					     * un-repairable  because
311 					     * stuck-to-x failure */
326 #define SERDES_PHYCLK_SEL_GTX		BIT(13)	/* 1:gtx_clk, 0:25M */
327 #define SERDES_PCIECLK_SEL_SRDS		BIT(12)	/* 1:serdes,0:25M */
332 #define SERDES_SELFB_PLL_SEL_CSR	BIT(6)	/* 0:state-machine,1:csr */
335 #define SERDES_SELFB_PLL_CSR_4		3	/* 4-12% OV-CLK */
336 #define SERDES_SELFB_PLL_CSR_0		2	/* 0-4% OV-CLK */
337 #define SERDES_SELFB_PLL_CSR_12		1	/* 12-18% OV-CLK */
338 #define SERDES_SELFB_PLL_CSR_18		0	/* 18-25% OV-CLK */
370 #define MAC_CTRL_BC_EN			BIT(26)
400 						 * inter-packet gap. The
401 						 * default is 96-bit time */
406 #define MAC_IPG_IFG_IPGR1_SHIFT     	16   	/* 64bit Carrier-Sense window */
408 #define MAC_IPG_IFG_IPGR2_SHIFT     	24    	/* 96-bit IPG window */
417 /* MAC Half-Duplex Control Register */
425 #define MAC_HALF_DUPLX_CTRL_NO_BACK_P   0x40000 /* No back-off on backpressure,
428 #define MAC_HALF_DUPLX_CTRL_ABEBE        0x80000 /* 1: Alternative Binary Exponential Back-off Enab…
431 …LX_CTRL_JAMIPG_SHIFT 24      /* IPG to start JAM for collision based flow control in half-duplex */
432 #define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK  0xf     /* mode. In unit of 8-bit time */
437 /* Wake-On-Lan control register */
444 #define WOL_PT2_MATCH			BIT(26)
498 #define REG_RFD_NIC_LEN			0x1510 /* In 8-bytes */
507 #define REG_SRAM_TRD_LEN            	0x151C /* In 8-bytes */
525  * pointer to prepare for the operation. This bit is then self-cleared
580 #define REG_TX_TSO_OFFLOAD_THRESH	0x1594 /* In 8-bytes */
584 #define	REG_TXF_WATER_MARK		0x1598 /* In 8-bytes */
608 #define RSS_MODE_SHIFT			26
631 #define RXD_DMA_THRESH_MASK		0x0FFF	/* In 8-bytes */
659 /* INT-triggle/SMB Control Register */
671 #define REG_TPD_PRI1_PIDX               0x15F0	/* 16bit,hi-tpd producer idx */
672 #define REG_TPD_PRI0_PIDX		0x15F2	/* 16bit,lo-tpd producer idx */
673 #define REG_TPD_PRI1_CIDX		0x15F4	/* 16bit,hi-tpd consumer idx */
674 #define REG_TPD_PRI0_CIDX		0x15F6	/* 16bit,lo-tpd consumer idx */
804 #define L1D_MPW_PHYID2			0xD01D  /* V1-V6 */
812 /* 1000BASE-T Control Register */
844 /* Cable-Detect-Test Control Register */
851 /* Cable-Detect-Test Status Register */