Lines Matching +full:0 +full:x8006
57 #define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062
58 #define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063
59 #define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */
60 #define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */
61 #define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */
62 #define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */
63 #define L2CB_V10 0xc0
64 #define L2CB_V11 0xc1
65 #define L2CB_V20 0xc0
66 #define L2CB_V21 0xc1
69 #define REG_DEVICE_CAP 0x5C
70 #define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
71 #define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
75 #define REG_LINK_CTRL 0x68
76 #define LINK_CTRL_L0S_EN 0x01
77 #define LINK_CTRL_L1_EN 0x02
78 #define LINK_CTRL_EXT_SYNC 0x80
80 #define REG_PCIE_IND_ACC_ADDR 0x80
81 #define REG_PCIE_IND_ACC_DATA 0x84
83 #define REG_DEV_SERIALNUM_CTRL 0x200
84 #define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */
85 #define REG_DEV_MAC_SEL_SHIFT 0
86 #define REG_DEV_SERIAL_NUM_EN_MASK 0x1
89 #define REG_TWSI_CTRL 0x218
90 #define TWSI_CTLR_FREQ_MASK 0x3UL
92 #define TWSI_CTRL_FREQ_100K 0
97 #define TWSI_CTRL_HW_LDSTAT BIT(12) /* 0:finish,1:in progress */
99 #define TWSI_CTRL_LD_OFFSET_MASK 0xFF
100 #define TWSI_CTRL_LD_OFFSET_SHIFT 0
102 #define REG_PCIE_DEV_MISC_CTRL 0x21C
103 #define PCIE_DEV_MISC_EXT_PIPE 0x2
104 #define PCIE_DEV_MISC_RETRY_BUFDIS 0x1
105 #define PCIE_DEV_MISC_SPIROM_EXIST 0x4
106 #define PCIE_DEV_MISC_SERDES_ENDIAN 0x8
107 #define PCIE_DEV_MISC_SERDES_SEL_DIN 0x10
109 #define REG_PCIE_PHYMISC 0x1000
111 #define PCIE_PHYMISC_NFTS_MASK 0xFFUL
114 #define REG_PCIE_PHYMISC2 0x1004
115 #define PCIE_PHYMISC2_L0S_TH_MASK 0x3UL
118 #define PCIE_PHYMISC2_CDR_BW_MASK 0x3UL
122 #define REG_TWSI_DEBUG 0x1108
125 #define REG_DMA_DBG 0x1114
126 #define DMA_DBG_VENDOR_MSG BIT(0)
128 #define REG_EEPROM_CTRL 0x12C0
129 #define EEPROM_CTRL_DATA_HI_MASK 0xFFFF
130 #define EEPROM_CTRL_DATA_HI_SHIFT 0
131 #define EEPROM_CTRL_ADDR_MASK 0x3FF
133 #define EEPROM_CTRL_ACK 0x40000000
134 #define EEPROM_CTRL_RW 0x80000000
136 #define REG_EEPROM_DATA_LO 0x12C4
138 #define REG_OTP_CTRL 0x12F0
141 #define REG_PM_CTRL 0x12F8
147 #define PM_CTRL_LCKDET_TIMER_MASK 0xFUL
149 #define PM_CTRL_LCKDET_TIMER_DEF 0xC
150 #define PM_CTRL_PM_REQ_TIMER_MASK 0xFUL
153 #define PM_CTRL_PM_REQ_TO_DEF 0xF
154 #define PMCTRL_TXL1_AFTER_L0S BIT(19) /* l1dv2.0+ */
155 #define L1D_PMCTRL_L1_ENTRY_TM_MASK 7UL /* l1dv2.0+, 3bits */
157 #define L1D_PMCTRL_L1_ENTRY_TM_DIS 0
165 #define PM_CTRL_L1_ENTRY_TIMER_MASK 0xFUL /* l1C 4bits */
168 #define L1C_PM_CTRL_L1_ENTRY_TM 0xF
169 #define PM_CTRL_RCVR_WT_TIMER BIT(15) /* 1:1us, 0:2ms */
170 #define PM_CTRL_CLK_PWM_VER1_1 BIT(14) /* 0:1.0a,1:1.1 */
173 #define PM_CTRL_RXL1_AFTER_L0S BIT(11) /* l1dv2.0+ */
174 #define L1D_PMCTRL_L0S_TIMER_MASK 7UL /* l1d2.0+, 3bits*/
176 #define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xFUL /* l1c, 4bits */
185 #define PM_CTRL_SPRSDWER_EN BIT(0)
187 #define REG_LTSSM_ID_CTRL 0x12FC
188 #define LTSSM_ID_EN_WRO 0x1000
192 #define REG_MASTER_CTRL 0x1400
194 #define MASTER_DEV_NUM_MASK 0x7FUL
196 #define MASTER_REV_NUM_MASK 0xFFUL
212 #define MASTER_CTRL_SOFT_RST BIT(0) /* RST MAC & DMA */
216 #define REG_MANUAL_TIMER_INIT 0x1404
219 #define REG_IRQ_MODRT_TIMER_INIT 0x1408
220 #define IRQ_MODRT_TIMER_MASK 0xffff
221 #define IRQ_MODRT_TX_TIMER_SHIFT 0
224 #define REG_GPHY_CTRL 0x140C
225 #define GPHY_CTRL_ADDR_MASK 0x1FUL
232 #define GPHY_CTRL_PHY_PLL_ON BIT(13) /* 1:pll always on, 0:can sw */
245 #define GPHY_CTRL_EXT_RESET BIT(0) /* 1:out of DSP RST status */
253 #define REG_IDLE_STATUS 0x1410
254 #define IDLE_STATUS_SFORCE_MASK 0xFUL
257 #define IDLE_STATUS_CALIB_RES_MASK 0x1FUL
259 #define IDLE_STATUS_CALIBERR_MASK 0xFUL
264 #define IDLE_STATUS_RXMAC_BUSY BIT(0)
272 #define REG_MDIO_CTRL 0x1414
277 #define MDIO_CTRL_CLK_SEL_MASK 0x7UL
279 #define MDIO_CTRL_CLK_25_4 0 /* 25MHz divide 4 */
288 #define MDIO_CTRL_OP_READ BIT(21) /* 1:read, 0:write */
289 #define MDIO_CTRL_REG_MASK 0x1FUL
291 #define MDIO_CTRL_DATA_MASK 0xFFFFUL
292 #define MDIO_CTRL_DATA_SHIFT 0
296 #define REG_MDIO_EXTN 0x1448
297 #define MDIO_EXTN_PORTAD_MASK 0x1FUL
299 #define MDIO_EXTN_DEVAD_MASK 0x1FUL
301 #define MDIO_EXTN_REG_MASK 0xFFFFUL
302 #define MDIO_EXTN_REG_SHIFT 0
305 #define REG_BIST0_CTRL 0x141c
306 #define BIST0_NOW 0x1
307 #define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is
312 #define BIST0_FUSE_FLAG 0x4
315 #define REG_BIST1_CTRL 0x1420
316 #define BIST1_NOW 0x1
317 #define BIST1_SRAM_FAIL 0x2
318 #define BIST1_FUSE_FLAG 0x4
321 #define REG_SERDES 0x1424
324 #define SERDES_SELFB_PLL_MASK 0x3UL
326 #define SERDES_PHYCLK_SEL_GTX BIT(13) /* 1:gtx_clk, 0:25M */
327 #define SERDES_PCIECLK_SEL_SRDS BIT(12) /* 1:serdes,0:25M */
332 #define SERDES_SELFB_PLL_SEL_CSR BIT(6) /* 0:state-machine,1:csr */
333 #define SERDES_SELFB_PLL_CSR_MASK 0x3UL
336 #define SERDES_SELFB_PLL_CSR_0 2 /* 0-4% OV-CLK */
338 #define SERDES_SELFB_PLL_CSR_18 0 /* 18-25% OV-CLK */
342 #define SERDES_LOCK_DETECT BIT(0)
344 #define REG_LPI_DECISN_TIMER 0x143C
345 #define L2CB_LPI_DESISN_TIMER 0x7D00
347 #define REG_LPI_CTRL 0x1440
349 #define LPI_CTRL_ENH_TO_MASK 0x1FFFUL
351 #define LPI_CTRL_ENH_TH_MASK 0x1FUL
358 #define LPI_CTRL_EN BIT(0)
360 #define REG_LPI_WAIT 0x1444
361 #define LPI_WAIT_TIMER_MASK 0xFFFFUL
362 #define LPI_WAIT_TIMER_SHIFT 0
365 #define REG_MAC_CTRL 0x1480
366 #define MAC_CTRL_SPEED_MODE_SW BIT(30) /* 0:phy,1:sw */
367 #define MAC_CTRL_HASH_ALG_CRC32 BIT(29) /* 1:legacy,0:lw_5b */
384 #define MAC_CTRL_PRMLEN_MASK 0xFUL
395 #define MAC_CTRL_TX_EN BIT(0)
398 #define REG_MAC_IPG_IFG 0x1484
399 #define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back
402 #define MAC_IPG_IFG_IPGT_MASK 0x7f
405 #define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */
407 #define MAC_IPG_IFG_IPGR1_MASK 0x7f
409 #define MAC_IPG_IFG_IPGR2_MASK 0x7f
412 #define REG_MAC_STA_ADDR 0x1488
415 #define REG_RX_HASH_TABLE 0x1490
418 #define REG_MAC_HALF_DUPLX_CTRL 0x1498
419 #define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */
420 #define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
422 #define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
423 #define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
424 #define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
425 #define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* No back-off on backpressure,
428 #define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enab…
430 #define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
432 #define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */
435 #define REG_MTU 0x149c
438 #define REG_WOL_CTRL 0x14a0
464 #define WOL_PATTERN_EN BIT(0)
467 #define REG_WOL_PTLEN1 0x14A4
468 #define WOL_PTLEN1_3_MASK 0xFFUL
470 #define WOL_PTLEN1_2_MASK 0xFFUL
472 #define WOL_PTLEN1_1_MASK 0xFFUL
474 #define WOL_PTLEN1_0_MASK 0xFFUL
475 #define WOL_PTLEN1_0_SHIFT 0
477 #define REG_WOL_PTLEN2 0x14A8
478 #define WOL_PTLEN2_7_MASK 0xFFUL
480 #define WOL_PTLEN2_6_MASK 0xFFUL
482 #define WOL_PTLEN2_5_MASK 0xFFUL
484 #define WOL_PTLEN2_4_MASK 0xFFUL
485 #define WOL_PTLEN2_4_SHIFT 0
488 #define RFDX_HEAD_ADDR_MASK 0x03FF
489 #define RFDX_HARD_ADDR_SHIFT 0
490 #define RFDX_TAIL_ADDR_MASK 0x03FF
493 #define REG_SRAM_RFD0_INFO 0x1500
494 #define REG_SRAM_RFD1_INFO 0x1504
495 #define REG_SRAM_RFD2_INFO 0x1508
496 #define REG_SRAM_RFD3_INFO 0x150C
498 #define REG_RFD_NIC_LEN 0x1510 /* In 8-bytes */
499 #define RFD_NIC_LEN_MASK 0x03FF
501 #define REG_SRAM_TRD_ADDR 0x1518
502 #define TPD_HEAD_ADDR_MASK 0x03FF
503 #define TPD_HEAD_ADDR_SHIFT 0
504 #define TPD_TAIL_ADDR_MASK 0x03FF
507 #define REG_SRAM_TRD_LEN 0x151C /* In 8-bytes */
508 #define TPD_NIC_LEN_MASK 0x03FF
510 #define REG_SRAM_RXF_ADDR 0x1520
511 #define REG_SRAM_RXF_LEN 0x1524
512 #define REG_SRAM_TXF_ADDR 0x1528
513 #define REG_SRAM_TXF_LEN 0x152C
514 #define REG_SRAM_TCPH_ADDR 0x1530
515 #define REG_SRAM_PKTH_ADDR 0x1532
520 #define REG_LOAD_PTR 0x1534
528 #define REG_RX_BASE_ADDR_HI 0x1540
529 #define REG_TX_BASE_ADDR_HI 0x1544
530 #define REG_RFD0_HEAD_ADDR_LO 0x1550
531 #define REG_RFD1_HEAD_ADDR_LO 0x1554
532 #define REG_RFD2_HEAD_ADDR_LO 0x1558
533 #define REG_RFD3_HEAD_ADDR_LO 0x155C
534 #define REG_RFD_RING_SIZE 0x1560
535 #define RFD_RING_SIZE_MASK 0x0FFF
536 #define REG_RX_BUF_SIZE 0x1564
537 #define RX_BUF_SIZE_MASK 0xFFFF
538 #define REG_RRD0_HEAD_ADDR_LO 0x1568
539 #define REG_RRD1_HEAD_ADDR_LO 0x156C
540 #define REG_RRD2_HEAD_ADDR_LO 0x1570
541 #define REG_RRD3_HEAD_ADDR_LO 0x1574
542 #define REG_RRD_RING_SIZE 0x1578
543 #define RRD_RING_SIZE_MASK 0x0FFF
544 #define REG_TPD_PRI1_ADDR_LO 0x157C
545 #define REG_TPD_PRI0_ADDR_LO 0x1580
546 #define REG_TPD_PRI2_ADDR_LO 0x1F10
547 #define REG_TPD_PRI3_ADDR_LO 0x1F14
549 #define REG_TPD_RING_SIZE 0x1584
550 #define TPD_RING_SIZE_MASK 0xFFFF
553 #define REG_TXQ_CTRL 0x1590
554 #define TXQ_TXF_BURST_NUM_MASK 0xFFFFUL
556 #define L1C_TXQ_TXF_BURST_PREF 0x200
557 #define L2CB_TXQ_TXF_BURST_PREF 0x40
563 #define TXQ_NUM_TPD_BURST_MASK 0xFUL
564 #define TXQ_NUM_TPD_BURST_SHIFT 0
580 #define REG_TX_TSO_OFFLOAD_THRESH 0x1594 /* In 8-bytes */
581 #define TX_TSO_OFFLOAD_THRESH_MASK 0x07FF
584 #define REG_TXF_WATER_MARK 0x1598 /* In 8-bytes */
585 #define TXF_WATER_MARK_MASK 0x0FFF
586 #define TXF_LOW_WATER_MARK_SHIFT 0
588 #define TXQ_CTRL_BURST_MODE_EN 0x80000000
590 #define REG_THRUPUT_MON_CTRL 0x159C
591 #define THRUPUT_MON_RATE_MASK 0x3
592 #define THRUPUT_MON_RATE_SHIFT 0
593 #define THRUPUT_MON_EN 0x80
596 #define REG_RXQ_CTRL 0x15A0
597 #define ASPM_THRUPUT_LIMIT_MASK 0x3
598 #define ASPM_THRUPUT_LIMIT_SHIFT 0
599 #define ASPM_THRUPUT_LIMIT_NO 0x00
600 #define ASPM_THRUPUT_LIMIT_1M 0x01
601 #define ASPM_THRUPUT_LIMIT_10M 0x02
602 #define ASPM_THRUPUT_LIMIT_100M 0x03
604 #define RXQ_RFD_BURST_NUM_MASK 0x003F
609 #define RSS_MODE_DIS 0
613 #define RSS_NIP_QUEUE_SEL BIT(28) /* 0:q0, 1:table */
618 #define REG_RFD_FREE_THRESH 0x15A4
619 #define RFD_FREE_THRESH_MASK 0x003F
620 #define RFD_FREE_HI_THRESH_SHIFT 0
624 #define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
625 #define RXQ_RXF_PAUSE_TH_HI_SHIFT 0
626 #define RXQ_RXF_PAUSE_TH_HI_MASK 0x0FFF
628 #define RXQ_RXF_PAUSE_TH_LO_MASK 0x0FFF
630 #define REG_RXD_DMA_CTRL 0x15AC
631 #define RXD_DMA_THRESH_MASK 0x0FFF /* In 8-bytes */
632 #define RXD_DMA_THRESH_SHIFT 0
633 #define RXD_DMA_DOWN_TIMER_MASK 0xFFFF
637 #define REG_DMA_CTRL 0x15C0
641 #define DMA_CTRL_WDLY_CNT_MASK 0xFUL
644 #define DMA_CTRL_RDLY_CNT_MASK 0x1FUL
647 #define DMA_CTRL_RREQ_PRI_DATA BIT(10) /* 0:tpd, 1:data */
652 #define L1C_CTRL_DMA_RCB_LEN128 BIT(3) /* 0:64bytes,1:128bytes */
654 #define DMA_CTRL_RORDER_MODE_SHIFT 0
660 #define REG_SMB_STAT_TIMER 0x15C4 /* 2us resolution */
661 #define SMB_STAT_TIMER_MASK 0xFFFFFF
662 #define REG_TINT_TPD_THRESH 0x15C8 /* tpd th to trig intrrupt */
665 #define MB_RFDX_PROD_IDX_MASK 0xFFFF
666 #define REG_MB_RFD0_PROD_IDX 0x15E0
667 #define REG_MB_RFD1_PROD_IDX 0x15E4
668 #define REG_MB_RFD2_PROD_IDX 0x15E8
669 #define REG_MB_RFD3_PROD_IDX 0x15EC
671 #define REG_TPD_PRI1_PIDX 0x15F0 /* 16bit,hi-tpd producer idx */
672 #define REG_TPD_PRI0_PIDX 0x15F2 /* 16bit,lo-tpd producer idx */
673 #define REG_TPD_PRI1_CIDX 0x15F4 /* 16bit,hi-tpd consumer idx */
674 #define REG_TPD_PRI0_CIDX 0x15F6 /* 16bit,lo-tpd consumer idx */
675 #define REG_TPD_PRI3_PIDX 0x1F18
676 #define REG_TPD_PRI2_PIDX 0x1F1A
677 #define REG_TPD_PRI3_CIDX 0x1F1C
678 #define REG_TPD_PRI2_CIDX 0x1F1E
681 #define REG_MB_RFD01_CONS_IDX 0x15F8
682 #define MB_RFD0_CONS_IDX_MASK 0x0000FFFF
683 #define MB_RFD1_CONS_IDX_MASK 0xFFFF0000
684 #define REG_MB_RFD23_CONS_IDX 0x15FC
685 #define MB_RFD2_CONS_IDX_MASK 0x0000FFFF
686 #define MB_RFD3_CONS_IDX_MASK 0xFFFF0000
689 #define REG_ISR 0x1600
690 #define ISR_SMB 0x00000001
691 #define ISR_TIMER 0x00000002
694 * in Table 51 Selene Master Control Register (Offset 0x1400).
696 #define ISR_MANUAL 0x00000004
697 #define ISR_HW_RXF_OV 0x00000008 /* RXF overflow interrupt */
698 #define ISR_RFD0_UR 0x00000010 /* RFD0 under run */
699 #define ISR_RFD1_UR 0x00000020
700 #define ISR_RFD2_UR 0x00000040
701 #define ISR_RFD3_UR 0x00000080
702 #define ISR_TXF_UR 0x00000100
703 #define ISR_DMAR_TO_RST 0x00000200
704 #define ISR_DMAW_TO_RST 0x00000400
705 #define ISR_TX_CREDIT 0x00000800
706 #define ISR_GPHY 0x00001000
708 #define ISR_GPHY_LPW 0x00002000
709 #define ISR_TXQ_TO_RST 0x00004000
710 #define ISR_TX_PKT_0 0x00008000
711 #define ISR_RX_PKT_0 0x00010000
712 #define ISR_RX_PKT_1 0x00020000
713 #define ISR_RX_PKT_2 0x00040000
714 #define ISR_RX_PKT_3 0x00080000
715 #define ISR_MAC_RX 0x00100000
716 #define ISR_MAC_TX 0x00200000
717 #define ISR_UR_DETECTED 0x00400000
718 #define ISR_FERR_DETECTED 0x00800000
719 #define ISR_NFERR_DETECTED 0x01000000
720 #define ISR_CERR_DETECTED 0x02000000
721 #define ISR_PHY_LINKDOWN 0x04000000
722 #define ISR_TX_PKT_1 0x10000000
723 #define ISR_TX_PKT_2 0x20000000
724 #define ISR_TX_PKT_3 0x40000000
725 #define ISR_DIS_INT 0x80000000
728 #define REG_IMR 0x1604
768 #define REG_INT_RETRIG_TIMER 0x1608
769 #define INT_RETRIG_TIMER_MASK 0xFFFF
771 #define REG_MAC_RX_STATUS_BIN 0x1700
772 #define REG_MAC_RX_STATUS_END 0x175c
773 #define REG_MAC_TX_STATUS_BIN 0x1760
774 #define REG_MAC_TX_STATUS_END 0x17c0
776 #define REG_CLK_GATING_CTRL 0x1814
777 #define CLK_GATING_DMAW_EN 0x0001
778 #define CLK_GATING_DMAR_EN 0x0002
779 #define CLK_GATING_TXQ_EN 0x0004
780 #define CLK_GATING_RXQ_EN 0x0008
781 #define CLK_GATING_TXMAC_EN 0x0010
782 #define CLK_GATING_RXMAC_EN 0x0020
792 #define REG_DEBUG_DATA0 0x1900
793 #define REG_DEBUG_DATA1 0x1904
795 #define REG_MT_MAGIC 0x1F00
796 #define REG_MT_MODE 0x1F04
797 #define REG_MT_SPEED 0x1F08
798 #define REG_MT_VERSION 0x1F0C
800 #define MT_MAGIC 0xaabb1234
801 #define MT_MODE_4Q BIT(0)
803 #define L1D_MPW_PHYID1 0xD01C /* V7 */
804 #define L1D_MPW_PHYID2 0xD01D /* V1-V6 */
805 #define L1D_MPW_PHYID3 0xD01E /* V8 */
813 #define GIGA_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port 0=DTE device */
815 #define GIGA_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */
816 #define GIGA_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value 0=Automatic Master/S…
817 #define GIGA_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
818 #define GIGA_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
819 #define GIGA_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
820 #define GIGA_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
821 #define GIGA_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
822 #define GIGA_CR_1000T_SPEED_MASK 0x0300
823 #define GIGA_CR_1000T_DEFAULT_CAP 0x0300
826 #define MII_GIGA_PSSR 0x11
827 #define GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
828 #define GIGA_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
829 #define GIGA_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
830 #define GIGA_PSSR_10MBS 0x0000 /* 00=10Mbs */
831 #define GIGA_PSSR_100MBS 0x4000 /* 01=100Mbs */
832 #define GIGA_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
835 #define MII_IER 0x12
836 #define IER_LINK_UP 0x0400
837 #define IER_LINK_DOWN 0x0800
840 #define MII_ISR 0x13
841 #define ISR_LINK_UP 0x0400
842 #define ISR_LINK_DOWN 0x0800
845 #define MII_CDTC 0x16
846 #define CDTC_EN_OFF 0 /* sc */
852 #define MII_CDTS 0x1C
855 #define CDTS_STATUS_NORMAL 0
860 #define MII_DBG_ADDR 0x1D
861 #define MII_DBG_DATA 0x1E
865 #define MIIDBG_ANACTRL 0x00
866 #define ANACTRL_CLK125M_DELAY_EN 0x8000
867 #define ANACTRL_VCO_FAST 0x4000
868 #define ANACTRL_VCO_SLOW 0x2000
869 #define ANACTRL_AFE_MODE_EN 0x1000
870 #define ANACTRL_LCKDET_PHY 0x800
871 #define ANACTRL_LCKDET_EN 0x400
872 #define ANACTRL_OEN_125M 0x200
873 #define ANACTRL_HBIAS_EN 0x100
874 #define ANACTRL_HB_EN 0x80
875 #define ANACTRL_SEL_HSP 0x40
876 #define ANACTRL_CLASSA_EN 0x20
879 #define ANACTRL_MANUSWON_SWR_2V 0
883 #define ANACTRL_MANUSWON_BW3_4M 0x2
884 #define ANACTRL_RESTART_CAL 0x1
885 #define ANACTRL_DEF 0x02EF
887 #define MIIDBG_SYSMODCTRL 0x04
888 #define SYSMODCTRL_IECHOADJ_PFMH_PHY 0x8000
889 #define SYSMODCTRL_IECHOADJ_BIASGEN 0x4000
890 #define SYSMODCTRL_IECHOADJ_PFML_PHY 0x2000
896 #define SYSMODCTRL_IECHOADJ_10BT_100MV 0x40 /* 1:100mv, 0:200mv */
899 #define SYSMODCTRL_IECHOADJ_VDFULBW 0x8
900 #define SYSMODCTRL_IECHOADJ_VDBIASHLF 0x4
901 #define SYSMODCTRL_IECHOADJ_VDAMPHLF 0x2
902 #define SYSMODCTRL_IECHOADJ_VDLANSW 0x1
903 #define SYSMODCTRL_IECHOADJ_DEF 0x88BB /* ???? */
906 #define SYSMODCTRL_IECHOADJ_CUR_ADD 0x8000
909 #define SYSMODCTRL_IECHOADJ_VOL_MASK 0xFU
913 #define SYSMODCTRL_IECHOADJ_VOL_10M17 0
914 #define SYSMODCTRL_IECHOADJ_BIAS1_MASK 0xFU
916 #define SYSMODCTRL_IECHOADJ_BIAS2_MASK 0xFU
917 #define SYSMODCTRL_IECHOADJ_BIAS2_SHIFT 0
918 #define L1D_SYSMODCTRL_IECHOADJ_DEF 0x4FBB
920 #define MIIDBG_SRDSYSMOD 0x05
921 #define SRDSYSMOD_LCKDET_EN 0x2000
922 #define SRDSYSMOD_PLL_EN 0x800
923 #define SRDSYSMOD_SEL_HSP 0x400
924 #define SRDSYSMOD_HLFTXDR 0x200
925 #define SRDSYSMOD_TXCLK_DELAY_EN 0x100
926 #define SRDSYSMOD_TXELECIDLE 0x80
927 #define SRDSYSMOD_DEEMP_EN 0x40
928 #define SRDSYSMOD_MS_PAD 0x4
929 #define SRDSYSMOD_CDR_ADC_VLTG 0x2
930 #define SRDSYSMOD_CDR_DAC_1MA 0x1
931 #define SRDSYSMOD_DEF 0x2C46
933 #define MIIDBG_CFGLPSPD 0x0A
936 #define CFGLPSPD_RSTCNT_CLK125SW 0x2000
938 #define MIIDBG_HIBNEG 0x0B
939 #define HIBNEG_PSHIB_EN 0x8000
940 #define HIBNEG_WAKE_BOTH 0x4000
941 #define HIBNEG_ONOFF_ANACHG_SUDEN 0x2000
942 #define HIBNEG_HIB_PULSE 0x1000
943 #define HIBNEG_GATE_25M_EN 0x800
944 #define HIBNEG_RST_80U 0x400
949 #define HIBNEG_BYPSS_BRKTIMER 0x10
950 #define HIBNEG_DEF 0xBC40
952 #define MIIDBG_TST10BTCFG 0x12
957 #define TST10BTCFG_DIV_MAN_MLT3_EN 0x800
958 #define TST10BTCFG_OFF_DAC_IDLE 0x400
959 #define TST10BTCFG_LPBK_DEEP 0x4 /* 1:deep,0:shallow */
960 #define TST10BTCFG_DEF 0x4C04
962 #define MIIDBG_AZ_ANADECT 0x15
963 #define AZ_ANADECT_10BTRX_TH 0x8000
964 #define AZ_ANADECT_BOTH_01CHNL 0x4000
965 #define AZ_ANADECT_INTV_MASK 0x3FU
967 #define AZ_ANADECT_THRESH_MASK 0xFU
969 #define AZ_ANADECT_CHNL_MASK 0xFU
970 #define AZ_ANADECT_CHNL_SHIFT 0
971 #define AZ_ANADECT_DEF 0x3220
972 #define AZ_ANADECT_LONG 0xb210
974 #define MIIDBG_MSE16DB 0x18 /* l1d */
975 #define L1D_MSE16DB_UP 0x05EA
976 #define L1D_MSE16DB_DOWN 0x02EA
978 #define MIIDBG_LEGCYPS 0x29
979 #define LEGCYPS_EN 0x8000
988 #define LEGCYPS_UNPLUG_DECT_EN 0x4
989 #define LEGCYPS_ECNC_PS_EN 0x1
990 #define L1D_LEGCYPS_DEF 0x129D
991 #define L1C_LEGCYPS_DEF 0x36DD
993 #define MIIDBG_TST100BTCFG 0x36
994 #define TST100BTCFG_NORMAL_BW_EN 0x8000
995 #define TST100BTCFG_BADLNK_BYPASS 0x4000
996 #define TST100BTCFG_SHORTCABL_TH_MASK 0x3FU
998 #define TST100BTCFG_LITCH_EN 0x80
999 #define TST100BTCFG_VLT_SW 0x40
1000 #define TST100BTCFG_LONGCABL_TH_MASK 0x3FU
1001 #define TST100BTCFG_LONGCABL_TH_SHIFT 0
1002 #define TST100BTCFG_DEF 0xE12C
1004 #define MIIDBG_VOLT_CTRL 0x3B /* only for l2cb 1 & 2 */
1005 #define VOLT_CTRL_CABLE1TH_MASK 0x1FFU
1009 #define VOLT_CTRL_SW_BYPASS 0x10
1010 #define VOLT_CTRL_SWLOWEST 0x8
1012 #define VOLT_CTRL_DACAMP10_SHIFT 0
1014 #define MIIDBG_CABLE1TH_DET 0x3E
1015 #define CABLE1TH_DET_EN 0x8000
1021 #define MIIEXT_CLDCTRL3 0x8003
1022 #define CLDCTRL3_BP_CABLE1TH_DET_GT 0x8000
1023 #define CLDCTRL3_AZ_DISAMP 0x1000
1024 #define L2CB_CLDCTRL3 0x4D19
1025 #define L1D_CLDCTRL3 0xDD19
1027 #define MIIEXT_CLDCTRL6 0x8006
1028 #define CLDCTRL6_CAB_LEN_MASK 0x1FFU
1029 #define CLDCTRL6_CAB_LEN_SHIFT 0
1030 #define CLDCTRL6_CAB_LEN_SHORT 0x50
1035 #define MIIEXT_LOCAL_EEEADV 0x3C
1036 #define LOCAL_EEEADV_1000BT 0x4
1037 #define LOCAL_EEEADV_100BT 0x2
1039 #define MIIEXT_REMOTE_EEEADV 0x3D
1040 #define REMOTE_EEEADV_1000BT 0x4
1041 #define REMOTE_EEEADV_100BT 0x2
1043 #define MIIEXT_EEE_ANEG 0x8000
1044 #define EEE_ANEG_1000M 0x4
1045 #define EEE_ANEG_100M 0x2