Lines Matching +full:0 +full:x1b00
38 #define ALX_DEV_ID_AR8161 0x1091
39 #define ALX_DEV_ID_E2200 0xe091
40 #define ALX_DEV_ID_E2400 0xe0a1
41 #define ALX_DEV_ID_E2500 0xe0b1
42 #define ALX_DEV_ID_AR8162 0x1090
43 #define ALX_DEV_ID_AR8171 0x10A1
44 #define ALX_DEV_ID_AR8172 0x10A0
47 * bit(0): with xD support
52 #define ALX_REV_A0 0
57 #define ALX_DEV_CTRL 0x0060
60 #define ALX_MSIX_MASK 0x0090
62 #define ALX_UE_SVRT 0x010C
67 #define ALX_EFLD 0x0204
71 #define ALX_EFLD_START BIT(0)
74 #define ALX_SLD 0x0218
79 #define ALX_PDLL_TRNS1 0x1104
82 #define ALX_PMCTRL 0x12F8
87 #define ALX_PMCTRL_LCKDET_TIMER_MASK 0xF
89 #define ALX_PMCTRL_LCKDET_TIMER_DEF 0xC
91 #define ALX_PMCTRL_L1REQ_TO_MASK 0xF
93 #define ALX_PMCTRL_L1REG_TO_DEF 0xF
95 #define ALX_PMCTRL_L1_TIMER_MASK 0x7
114 #define ALX_MASTER 0x1400
126 #define ALX_MASTER_DMA_MAC_RST BIT(0)
129 #define ALX_IRQ_MODU_TIMER 0x1408
130 #define ALX_IRQ_MODU_TIMER1_MASK 0xFFFF
131 #define ALX_IRQ_MODU_TIMER1_SHIFT 0
133 #define ALX_PHY_CTRL 0x140C
137 /* bit13: 1:pll always ON, 0:can switch in lpw */
146 #define ALX_PHY_CTRL_DSPRST_OUT BIT(0)
152 #define ALX_MAC_STS 0x1410
156 #define ALX_MAC_STS_RXMAC_BUSY BIT(0)
162 #define ALX_MDIO 0x1414
165 #define ALX_MDIO_CLK_SEL_MASK 0x7
167 #define ALX_MDIO_CLK_SEL_25MD4 0
171 /* bit21: 1:read,0:write */
173 #define ALX_MDIO_REG_MASK 0x1F
175 #define ALX_MDIO_DATA_MASK 0xFFFF
176 #define ALX_MDIO_DATA_SHIFT 0
179 #define ALX_MDIO_EXTN 0x1448
180 #define ALX_MDIO_EXTN_DEVAD_MASK 0x1F
182 #define ALX_MDIO_EXTN_REG_MASK 0xFFFF
183 #define ALX_MDIO_EXTN_REG_SHIFT 0
185 #define ALX_SERDES 0x1424
189 #define ALX_LPI_CTRL 0x1440
190 #define ALX_LPI_CTRL_EN BIT(0)
193 #define ALX_HRTBT_EXT_CTRL 0x1AD0
194 #define L1F_HRTBT_EXT_CTRL_PERIOD_HIGH_MASK 0x3F
208 #define ALX_HRTBT_EXT_CTRL_FRAG_LEN_MASK 0xFF
213 #define ALX_HRTBT_EXT_CTRL_ARP_EN BIT(0)
215 #define ALX_HRTBT_REM_IPV4_ADDR 0x1AD4
216 #define ALX_HRTBT_HOST_IPV4_ADDR 0x1478
217 #define ALX_HRTBT_REM_IPV6_ADDR3 0x1AD8
218 #define ALX_HRTBT_REM_IPV6_ADDR2 0x1ADC
219 #define ALX_HRTBT_REM_IPV6_ADDR1 0x1AE0
220 #define ALX_HRTBT_REM_IPV6_ADDR0 0x1AE4
223 #define ALX_SWOI_ACER_CTRL 0x1B8C
225 #define ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_MASK 0XFF
227 #define ALX_SWOI_ORIG_ACK_ADDR_MASK 0XFFF
228 #define ALX_SWOI_ORIG_ACK_ADDR_SHIFT 0
230 #define ALX_SWOI_IOAC_CTRL_2 0x1B90
231 #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_MASK 0xFF
233 #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_MASK 0xFFF
235 #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_MASK 0xFFF
236 #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_SHIFT 0
238 #define ALX_SWOI_IOAC_CTRL_3 0x1B94
239 #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_MASK 0xFF
241 #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_MASK 0xFFF
243 #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_MASK 0xFFF
244 #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_SHIFT 0
247 #define ALX_IDLE_DECISN_TIMER 0x1474
249 #define ALX_IDLE_DECISN_TIMER_DEF 0x400
251 #define ALX_MAC_CTRL 0x1480
254 /* bit29: 1:legacy(hi5b), 0:marvl(lo5b)*/
258 #define ALX_MAC_CTRL_SPEED_MASK 0x3
264 #define ALX_MAC_CTRL_PRMBLEN_MASK 0xF
272 #define ALX_MAC_CTRL_TX_EN BIT(0)
274 #define ALX_STAD0 0x1488
275 #define ALX_STAD1 0x148C
277 #define ALX_HASH_TBL0 0x1490
278 #define ALX_HASH_TBL1 0x1494
280 #define ALX_MTU 0x149C
284 #define ALX_SRAM5 0x1524
285 #define ALX_SRAM_RXF_LEN_MASK 0xFFF
286 #define ALX_SRAM_RXF_LEN_SHIFT 0
289 #define ALX_SRAM9 0x1534
290 #define ALX_SRAM_LOAD_PTR BIT(0)
292 #define ALX_RX_BASE_ADDR_HI 0x1540
294 #define ALX_TX_BASE_ADDR_HI 0x1544
296 #define ALX_RFD_ADDR_LO 0x1550
297 #define ALX_RFD_RING_SZ 0x1560
298 #define ALX_RFD_BUF_SZ 0x1564
300 #define ALX_RRD_ADDR_LO 0x1568
301 #define ALX_RRD_RING_SZ 0x1578
304 #define ALX_TPD_PRI3_ADDR_LO 0x14E4
305 #define ALX_TPD_PRI2_ADDR_LO 0x14E0
306 #define ALX_TPD_PRI1_ADDR_LO 0x157C
307 #define ALX_TPD_PRI0_ADDR_LO 0x1580
310 #define ALX_TPD_PRI3_PIDX 0x1618
311 #define ALX_TPD_PRI2_PIDX 0x161A
312 #define ALX_TPD_PRI1_PIDX 0x15F0
313 #define ALX_TPD_PRI0_PIDX 0x15F2
316 #define ALX_TPD_PRI3_CIDX 0x161C
317 #define ALX_TPD_PRI2_CIDX 0x161E
318 #define ALX_TPD_PRI1_CIDX 0x15F4
319 #define ALX_TPD_PRI0_CIDX 0x15F6
321 #define ALX_TPD_RING_SZ 0x1584
323 #define ALX_TXQ0 0x1590
324 #define ALX_TXQ0_TXF_BURST_PREF_MASK 0xFFFF
326 #define ALX_TXQ_TXF_BURST_PREF_DEF 0x200
331 #define ALX_TXQ0_TPD_BURSTPREF_MASK 0xF
332 #define ALX_TXQ0_TPD_BURSTPREF_SHIFT 0
335 #define ALX_TXQ1 0x1594
340 #define ALX_RXQ0 0x15A0
343 #define ALX_RXQ0_RSS_MODE_MASK 0x3
345 #define ALX_RXQ0_RSS_MODE_DIS 0
347 #define ALX_RXQ0_NUM_RFD_PREF_MASK 0x3F
350 #define ALX_RXQ0_IDT_TBL_SIZE_MASK 0x1FF
352 #define ALX_RXQ0_IDT_TBL_SIZE_DEF 0x100
355 #define ALX_RXQ0_RSS_HSTYP_MASK 0xF
365 #define ALX_RXQ0_ASPM_THRESH_MASK 0x3
366 #define ALX_RXQ0_ASPM_THRESH_SHIFT 0
369 #define ALX_RXQ2 0x15A8
370 #define ALX_RXQ2_RXF_XOFF_THRESH_MASK 0xFFF
372 #define ALX_RXQ2_RXF_XON_THRESH_MASK 0xFFF
373 #define ALX_RXQ2_RXF_XON_THRESH_SHIFT 0
380 #define ALX_DMA 0x15C0
381 #define ALX_DMA_RCHNL_SEL_MASK 0x3
383 #define ALX_DMA_WDLY_CNT_MASK 0xF
386 #define ALX_DMA_RDLY_CNT_MASK 0x1F
389 /* bit10: 0:tpd with pri, 1: data */
391 #define ALX_DMA_RREQ_BLEN_MASK 0x7
393 #define ALX_DMA_RORDER_MODE_MASK 0x7
394 #define ALX_DMA_RORDER_MODE_SHIFT 0
397 #define ALX_WOL0 0x14A0
403 #define ALX_RFD_PIDX 0x15E0
405 #define ALX_RFD_CIDX 0x15F8
408 #define ALX_MIB_BASE 0x1700
410 #define ALX_MIB_RX_OK (ALX_MIB_BASE + 0)
463 #define ALX_ISR 0x1600
486 #define ALX_ISR_SMB BIT(0)
488 #define ALX_IMR 0x1604
491 #define ALX_INT_RETRIG 0x1608
495 #define ALX_SMB_TIMER 0x15C4
497 #define ALX_TINT_TPD_THRSHLD 0x15C8
499 #define ALX_TINT_TIMER 0x15CC
501 #define ALX_CLK_GATE 0x1814
507 #define ALX_CLK_GATE_DMAW BIT(0)
516 #define ALX_DRV 0x1804
525 #define ALX_DRV_PHY_MASK 0xFF
527 #define ALX_DRV_PHY_UNKNOWN 0
530 #define ALX_PHY_INITED 0x003F
533 #define ALX_WOL_CTRL2 0x1830
537 #define ALX_WOL_CTRL2_PTRN_EN BIT(0)
539 #define ALX_WOL_CTRL3 0x1834
540 #define ALX_WOL_CTRL3_PTRN_ADDR_MASK 0xFFFFF
541 #define ALX_WOL_CTRL3_PTRN_ADDR_SHIFT 0
543 #define ALX_WOL_CTRL4 0x1838
575 #define ALX_WOL_CTRL4_PT0_EN BIT(0)
577 #define ALX_WOL_CTRL5 0x183C
578 #define ALX_WOL_CTRL5_PT3_LEN_MASK 0xFF
580 #define ALX_WOL_CTRL5_PT2_LEN_MASK 0xFF
582 #define ALX_WOL_CTRL5_PT1_LEN_MASK 0xFF
584 #define ALX_WOL_CTRL5_PT0_LEN_MASK 0xFF
585 #define ALX_WOL_CTRL5_PT0_LEN_SHIFT 0
587 #define ALX_WOL_CTRL6 0x1840
588 #define ALX_WOL_CTRL5_PT7_LEN_MASK 0xFF
590 #define ALX_WOL_CTRL5_PT6_LEN_MASK 0xFF
592 #define ALX_WOL_CTRL5_PT5_LEN_MASK 0xFF
594 #define ALX_WOL_CTRL5_PT4_LEN_MASK 0xFF
595 #define ALX_WOL_CTRL5_PT4_LEN_SHIFT 0
597 #define ALX_WOL_CTRL7 0x1844
598 #define ALX_WOL_CTRL5_PT11_LEN_MASK 0xFF
600 #define ALX_WOL_CTRL5_PT10_LEN_MASK 0xFF
602 #define ALX_WOL_CTRL5_PT9_LEN_MASK 0xFF
604 #define ALX_WOL_CTRL5_PT8_LEN_MASK 0xFF
605 #define ALX_WOL_CTRL5_PT8_LEN_SHIFT 0
607 #define ALX_WOL_CTRL8 0x1848
608 #define ALX_WOL_CTRL5_PT15_LEN_MASK 0xFF
610 #define ALX_WOL_CTRL5_PT14_LEN_MASK 0xFF
612 #define ALX_WOL_CTRL5_PT13_LEN_MASK 0xFF
614 #define ALX_WOL_CTRL5_PT12_LEN_MASK 0xFF
615 #define ALX_WOL_CTRL5_PT12_LEN_SHIFT 0
617 #define ALX_ACER_FIXED_PTN0 0x1850
618 #define ALX_ACER_FIXED_PTN0_MASK 0xFFFFFFFF
619 #define ALX_ACER_FIXED_PTN0_SHIFT 0
621 #define ALX_ACER_FIXED_PTN1 0x1854
622 #define ALX_ACER_FIXED_PTN1_MASK 0xFFFF
623 #define ALX_ACER_FIXED_PTN1_SHIFT 0
625 #define ALX_ACER_RANDOM_NUM0 0x1858
626 #define ALX_ACER_RANDOM_NUM0_MASK 0xFFFFFFFF
627 #define ALX_ACER_RANDOM_NUM0_SHIFT 0
629 #define ALX_ACER_RANDOM_NUM1 0x185C
630 #define ALX_ACER_RANDOM_NUM1_MASK 0xFFFFFFFF
631 #define ALX_ACER_RANDOM_NUM1_SHIFT 0
633 #define ALX_ACER_RANDOM_NUM2 0x1860
634 #define ALX_ACER_RANDOM_NUM2_MASK 0xFFFFFFFF
635 #define ALX_ACER_RANDOM_NUM2_SHIFT 0
637 #define ALX_ACER_RANDOM_NUM3 0x1864
638 #define ALX_ACER_RANDOM_NUM3_MASK 0xFFFFFFFF
639 #define ALX_ACER_RANDOM_NUM3_SHIFT 0
641 #define ALX_ACER_MAGIC 0x1868
646 #define ALX_ACER_MAGIC_RAN_LEN_MASK 0x1F
648 #define ALX_ACER_MAGIC_FIX_LEN_MASK 0x1F
649 #define ALX_ACER_MAGIC_FIX_LEN_SHIFT 0
651 #define ALX_ACER_TIMER 0x186C
655 #define ALX_ACER_TIMER_THRES_MASK 0x1FFFF
656 #define ALX_ACER_TIMER_THRES_SHIFT 0
660 #define ALX_RSS_KEY0 0x14B0
661 #define ALX_RSS_KEY1 0x14B4
662 #define ALX_RSS_KEY2 0x14B8
663 #define ALX_RSS_KEY3 0x14BC
664 #define ALX_RSS_KEY4 0x14C0
665 #define ALX_RSS_KEY5 0x14C4
666 #define ALX_RSS_KEY6 0x14C8
667 #define ALX_RSS_KEY7 0x14CC
668 #define ALX_RSS_KEY8 0x14D0
669 #define ALX_RSS_KEY9 0x14D4
671 #define ALX_RSS_IDT_TBL0 0x1B00
673 #define ALX_MSI_MAP_TBL1 0x15D0
679 #define ALX_MSI_MAP_TBL1_RXQ0_SHIFT 0
681 #define ALX_MSI_MAP_TBL2 0x15D8
687 #define ALX_MSI_MAP_TBL2_RXQ4_SHIFT 0
689 #define ALX_MSI_ID_MAP 0x15D4
691 #define ALX_MSI_RETRANS_TIMER 0x1920
692 /* bit16: 1:line,0:standard */
694 #define ALX_MSI_RETRANS_TM_MASK 0xFFFF
695 #define ALX_MSI_RETRANS_TM_SHIFT 0
700 #define ALX_WRR 0x1938
701 #define ALX_WRR_PRI_MASK 0x3
704 #define ALX_WRR_PRI3_MASK 0x1F
706 #define ALX_WRR_PRI2_MASK 0x1F
708 #define ALX_WRR_PRI1_MASK 0x1F
710 #define ALX_WRR_PRI0_MASK 0x1F
711 #define ALX_WRR_PRI0_SHIFT 0
713 #define ALX_HQTPD 0x193C
715 #define ALX_HQTPD_Q3_NUMPREF_MASK 0xF
717 #define ALX_HQTPD_Q2_NUMPREF_MASK 0xF
719 #define ALX_HQTPD_Q1_NUMPREF_MASK 0xF
720 #define ALX_HQTPD_Q1_NUMPREF_SHIFT 0
722 #define ALX_MISC 0x19C0
723 #define ALX_MISC_PSW_OCP_MASK 0x7
725 #define ALX_MISC_PSW_OCP_DEF 0x7
729 #define ALX_MSIC2 0x19C8
730 #define ALX_MSIC2_CALB_START BIT(0)
732 #define ALX_MISC3 0x19CC
736 #define ALX_MISC3_25M_NOTO_INTNL BIT(0)
739 #define ALX_MSIX_ENTRY_BASE 0x2000
744 #define ALX_MII_GIGA_PSSR 0x11
745 #define ALX_GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800
746 #define ALX_GIGA_PSSR_DPLX 0x2000
747 #define ALX_GIGA_PSSR_SPEED 0xC000
748 #define ALX_GIGA_PSSR_10MBS 0x0000
749 #define ALX_GIGA_PSSR_100MBS 0x4000
750 #define ALX_GIGA_PSSR_1000MBS 0x8000
753 #define ALX_MII_IER 0x12
754 #define ALX_IER_LINK_UP 0x0400
755 #define ALX_IER_LINK_DOWN 0x0800
758 #define ALX_MII_ISR 0x13
760 #define ALX_MII_DBG_ADDR 0x1D
761 #define ALX_MII_DBG_DATA 0x1E
765 #define ALX_MIIDBG_ANACTRL 0x00
766 #define ALX_ANACTRL_DEF 0x02EF
768 #define ALX_MIIDBG_SYSMODCTRL 0x04
770 #define ALX_SYSMODCTRL_IECHOADJ_DEF 0xBB8B
772 #define ALX_MIIDBG_SRDSYSMOD 0x05
773 #define ALX_SRDSYSMOD_DEEMP_EN 0x0040
774 #define ALX_SRDSYSMOD_DEF 0x2C46
776 #define ALX_MIIDBG_HIBNEG 0x0B
777 #define ALX_HIBNEG_PSHIB_EN 0x8000
778 #define ALX_HIBNEG_HIB_PSE 0x1000
779 #define ALX_HIBNEG_DEF 0xBC40
783 #define ALX_MIIDBG_TST10BTCFG 0x12
784 #define ALX_TST10BTCFG_DEF 0x4C04
786 #define ALX_MIIDBG_AZ_ANADECT 0x15
787 #define ALX_AZ_ANADECT_DEF 0x3220
788 #define ALX_AZ_ANADECT_LONG 0x3210
790 #define ALX_MIIDBG_MSE16DB 0x18
791 #define ALX_MSE16DB_UP 0x05EA
792 #define ALX_MSE16DB_DOWN 0x02EA
794 #define ALX_MIIDBG_MSE20DB 0x1C
795 #define ALX_MSE20DB_TH_MASK 0x7F
797 #define ALX_MSE20DB_TH_DEF 0x2E
798 #define ALX_MSE20DB_TH_HI 0x54
800 #define ALX_MIIDBG_AGC 0x23
801 #define ALX_AGC_2_VGA_MASK 0x3FU
806 #define ALX_MIIDBG_LEGCYPS 0x29
807 #define ALX_LEGCYPS_EN 0x8000
808 #define ALX_LEGCYPS_DEF 0x129D
810 #define ALX_MIIDBG_TST100BTCFG 0x36
811 #define ALX_TST100BTCFG_DEF 0xE12C
813 #define ALX_MIIDBG_GREENCFG 0x3B
814 #define ALX_GREENCFG_DEF 0x7078
816 #define ALX_MIIDBG_GREENCFG2 0x3D
817 #define ALX_GREENCFG2_BP_GREEN 0x8000
818 #define ALX_GREENCFG2_GATE_DFSE_EN 0x0080
823 #define ALX_MIIEXT_CLDCTRL3 0x8003
824 #define ALX_CLDCTRL3_BP_CABLE1TH_DET_GT 0x8000
826 #define ALX_MIIEXT_CLDCTRL5 0x8005
827 #define ALX_CLDCTRL5_BP_VD_HLFBIAS 0x4000
829 #define ALX_MIIEXT_CLDCTRL6 0x8006
830 #define ALX_CLDCTRL6_CAB_LEN_MASK 0xFF
831 #define ALX_CLDCTRL6_CAB_LEN_SHIFT 0
835 #define ALX_MIIEXT_VDRVBIAS 0x8062
836 #define ALX_VDRVBIAS_DEF 0x3
841 #define ALX_MIIEXT_LOCAL_EEEADV 0x3C
842 #define ALX_LOCAL_EEEADV_1000BT 0x0004
843 #define ALX_LOCAL_EEEADV_100BT 0x0002
845 #define ALX_MIIEXT_AFE 0x801A
846 #define ALX_AFE_10BT_100M_TH 0x0040
848 #define ALX_MIIEXT_S3DIG10 0x8023
849 /* bit0: 1:bypass 10BT rx fifo, 0:original 10BT rx */
850 #define ALX_MIIEXT_S3DIG10_SL 0x0001
851 #define ALX_MIIEXT_S3DIG10_DEF 0
853 #define ALX_MIIEXT_NLP78 0x8027
854 #define ALX_MIIEXT_NLP78_120M_DEF 0x8A05