Lines Matching full:hw
39 #include "hw.h"
46 static int alx_wait_mdio_idle(struct alx_hw *hw) in alx_wait_mdio_idle() argument
52 val = alx_read_mem32(hw, ALX_MDIO); in alx_wait_mdio_idle()
61 static int alx_read_phy_core(struct alx_hw *hw, bool ext, u8 dev, in alx_read_phy_core() argument
70 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_read_phy_core()
77 alx_write_mem32(hw, ALX_MDIO_EXTN, val); in alx_read_phy_core()
88 alx_write_mem32(hw, ALX_MDIO, val); in alx_read_phy_core()
90 err = alx_wait_mdio_idle(hw); in alx_read_phy_core()
93 val = alx_read_mem32(hw, ALX_MDIO); in alx_read_phy_core()
98 static int alx_write_phy_core(struct alx_hw *hw, bool ext, u8 dev, in alx_write_phy_core() argument
104 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_write_phy_core()
111 alx_write_mem32(hw, ALX_MDIO_EXTN, val); in alx_write_phy_core()
124 alx_write_mem32(hw, ALX_MDIO, val); in alx_write_phy_core()
126 return alx_wait_mdio_idle(hw); in alx_write_phy_core()
129 static int __alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data) in __alx_read_phy_reg() argument
131 return alx_read_phy_core(hw, false, 0, reg, phy_data); in __alx_read_phy_reg()
134 static int __alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data) in __alx_write_phy_reg() argument
136 return alx_write_phy_core(hw, false, 0, reg, phy_data); in __alx_write_phy_reg()
139 static int __alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata) in __alx_read_phy_ext() argument
141 return alx_read_phy_core(hw, true, dev, reg, pdata); in __alx_read_phy_ext()
144 static int __alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data) in __alx_write_phy_ext() argument
146 return alx_write_phy_core(hw, true, dev, reg, data); in __alx_write_phy_ext()
149 static int __alx_read_phy_dbg(struct alx_hw *hw, u16 reg, u16 *pdata) in __alx_read_phy_dbg() argument
153 err = __alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, reg); in __alx_read_phy_dbg()
157 return __alx_read_phy_reg(hw, ALX_MII_DBG_DATA, pdata); in __alx_read_phy_dbg()
160 static int __alx_write_phy_dbg(struct alx_hw *hw, u16 reg, u16 data) in __alx_write_phy_dbg() argument
164 err = __alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, reg); in __alx_write_phy_dbg()
168 return __alx_write_phy_reg(hw, ALX_MII_DBG_DATA, data); in __alx_write_phy_dbg()
171 int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data) in alx_read_phy_reg() argument
175 spin_lock(&hw->mdio_lock); in alx_read_phy_reg()
176 err = __alx_read_phy_reg(hw, reg, phy_data); in alx_read_phy_reg()
177 spin_unlock(&hw->mdio_lock); in alx_read_phy_reg()
182 int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data) in alx_write_phy_reg() argument
186 spin_lock(&hw->mdio_lock); in alx_write_phy_reg()
187 err = __alx_write_phy_reg(hw, reg, phy_data); in alx_write_phy_reg()
188 spin_unlock(&hw->mdio_lock); in alx_write_phy_reg()
193 int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata) in alx_read_phy_ext() argument
197 spin_lock(&hw->mdio_lock); in alx_read_phy_ext()
198 err = __alx_read_phy_ext(hw, dev, reg, pdata); in alx_read_phy_ext()
199 spin_unlock(&hw->mdio_lock); in alx_read_phy_ext()
204 int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data) in alx_write_phy_ext() argument
208 spin_lock(&hw->mdio_lock); in alx_write_phy_ext()
209 err = __alx_write_phy_ext(hw, dev, reg, data); in alx_write_phy_ext()
210 spin_unlock(&hw->mdio_lock); in alx_write_phy_ext()
215 static int alx_read_phy_dbg(struct alx_hw *hw, u16 reg, u16 *pdata) in alx_read_phy_dbg() argument
219 spin_lock(&hw->mdio_lock); in alx_read_phy_dbg()
220 err = __alx_read_phy_dbg(hw, reg, pdata); in alx_read_phy_dbg()
221 spin_unlock(&hw->mdio_lock); in alx_read_phy_dbg()
226 static int alx_write_phy_dbg(struct alx_hw *hw, u16 reg, u16 data) in alx_write_phy_dbg() argument
230 spin_lock(&hw->mdio_lock); in alx_write_phy_dbg()
231 err = __alx_write_phy_dbg(hw, reg, data); in alx_write_phy_dbg()
232 spin_unlock(&hw->mdio_lock); in alx_write_phy_dbg()
237 static u16 alx_get_phy_config(struct alx_hw *hw) in alx_get_phy_config() argument
242 val = alx_read_mem32(hw, ALX_PHY_CTRL); in alx_get_phy_config()
247 val = alx_read_mem32(hw, ALX_DRV); in alx_get_phy_config()
252 alx_read_phy_reg(hw, ALX_MII_DBG_ADDR, &phy_val); in alx_get_phy_config()
259 static bool alx_wait_reg(struct alx_hw *hw, u32 reg, u32 wait, u32 *val) in alx_wait_reg() argument
265 read = alx_read_mem32(hw, reg); in alx_wait_reg()
277 static bool alx_read_macaddr(struct alx_hw *hw, u8 *addr) in alx_read_macaddr() argument
281 mac0 = alx_read_mem32(hw, ALX_STAD0); in alx_read_macaddr()
282 mac1 = alx_read_mem32(hw, ALX_STAD1); in alx_read_macaddr()
291 int alx_get_perm_macaddr(struct alx_hw *hw, u8 *addr) in alx_get_perm_macaddr() argument
296 if (alx_read_macaddr(hw, addr)) in alx_get_perm_macaddr()
300 if (!alx_wait_reg(hw, ALX_SLD, ALX_SLD_STAT | ALX_SLD_START, &val)) in alx_get_perm_macaddr()
302 alx_write_mem32(hw, ALX_SLD, val | ALX_SLD_START); in alx_get_perm_macaddr()
303 if (!alx_wait_reg(hw, ALX_SLD, ALX_SLD_START, NULL)) in alx_get_perm_macaddr()
305 if (alx_read_macaddr(hw, addr)) in alx_get_perm_macaddr()
309 val = alx_read_mem32(hw, ALX_EFLD); in alx_get_perm_macaddr()
311 if (!alx_wait_reg(hw, ALX_EFLD, in alx_get_perm_macaddr()
314 alx_write_mem32(hw, ALX_EFLD, val | ALX_EFLD_START); in alx_get_perm_macaddr()
315 if (!alx_wait_reg(hw, ALX_EFLD, ALX_EFLD_START, NULL)) in alx_get_perm_macaddr()
317 if (alx_read_macaddr(hw, addr)) in alx_get_perm_macaddr()
324 void alx_set_macaddr(struct alx_hw *hw, const u8 *addr) in alx_set_macaddr() argument
330 alx_write_mem32(hw, ALX_STAD0, val); in alx_set_macaddr()
332 alx_write_mem32(hw, ALX_STAD1, val); in alx_set_macaddr()
335 static void alx_reset_osc(struct alx_hw *hw, u8 rev) in alx_reset_osc() argument
339 /* clear Internal OSC settings, switching OSC by hw itself */ in alx_reset_osc()
340 val = alx_read_mem32(hw, ALX_MISC3); in alx_reset_osc()
341 alx_write_mem32(hw, ALX_MISC3, in alx_reset_osc()
348 val = alx_read_mem32(hw, ALX_MISC); in alx_reset_osc()
356 alx_write_mem32(hw, ALX_MISC, val); in alx_reset_osc()
357 alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN); in alx_reset_osc()
358 /* hw will automatically dis OSC after cab. */ in alx_reset_osc()
359 val2 = alx_read_mem32(hw, ALX_MSIC2); in alx_reset_osc()
361 alx_write_mem32(hw, ALX_MSIC2, val2); in alx_reset_osc()
362 alx_write_mem32(hw, ALX_MSIC2, val2 | ALX_MSIC2_CALB_START); in alx_reset_osc()
369 alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN); in alx_reset_osc()
370 alx_write_mem32(hw, ALX_MISC, val); in alx_reset_osc()
376 static int alx_stop_mac(struct alx_hw *hw) in alx_stop_mac() argument
381 rxq = alx_read_mem32(hw, ALX_RXQ0); in alx_stop_mac()
382 alx_write_mem32(hw, ALX_RXQ0, rxq & ~ALX_RXQ0_EN); in alx_stop_mac()
383 txq = alx_read_mem32(hw, ALX_TXQ0); in alx_stop_mac()
384 alx_write_mem32(hw, ALX_TXQ0, txq & ~ALX_TXQ0_EN); in alx_stop_mac()
388 hw->rx_ctrl &= ~(ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_TX_EN); in alx_stop_mac()
389 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); in alx_stop_mac()
392 val = alx_read_mem32(hw, ALX_MAC_STS); in alx_stop_mac()
401 int alx_reset_mac(struct alx_hw *hw) in alx_reset_mac() argument
409 rev = alx_hw_revision(hw); in alx_reset_mac()
410 a_cr = alx_is_rev_a(rev) && alx_hw_with_cr(hw); in alx_reset_mac()
413 alx_write_mem32(hw, ALX_MSIX_MASK, 0xFFFFFFFF); in alx_reset_mac()
414 alx_write_mem32(hw, ALX_IMR, 0); in alx_reset_mac()
415 alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS); in alx_reset_mac()
417 ret = alx_stop_mac(hw); in alx_reset_mac()
422 alx_write_mem32(hw, ALX_RFD_PIDX, 1); in alx_reset_mac()
426 pmctrl = alx_read_mem32(hw, ALX_PMCTRL); in alx_reset_mac()
428 alx_write_mem32(hw, ALX_PMCTRL, in alx_reset_mac()
434 val = alx_read_mem32(hw, ALX_MASTER); in alx_reset_mac()
435 alx_write_mem32(hw, ALX_MASTER, in alx_reset_mac()
441 val = alx_read_mem32(hw, ALX_RFD_PIDX); in alx_reset_mac()
447 val = alx_read_mem32(hw, ALX_MASTER); in alx_reset_mac()
457 alx_write_mem32(hw, ALX_MASTER, val | ALX_MASTER_PCLKSEL_SRDS); in alx_reset_mac()
460 alx_write_mem32(hw, ALX_PMCTRL, pmctrl); in alx_reset_mac()
463 alx_reset_osc(hw, rev); in alx_reset_mac()
465 /* clear Internal OSC settings, switching OSC by hw itself, in alx_reset_mac()
468 val = alx_read_mem32(hw, ALX_MISC3); in alx_reset_mac()
469 alx_write_mem32(hw, ALX_MISC3, in alx_reset_mac()
472 val = alx_read_mem32(hw, ALX_MISC); in alx_reset_mac()
476 alx_write_mem32(hw, ALX_MISC, val); in alx_reset_mac()
480 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); in alx_reset_mac()
482 val = alx_read_mem32(hw, ALX_SERDES); in alx_reset_mac()
483 alx_write_mem32(hw, ALX_SERDES, in alx_reset_mac()
490 void alx_reset_phy(struct alx_hw *hw) in alx_reset_phy() argument
497 val = alx_read_mem32(hw, ALX_PHY_CTRL); in alx_reset_phy()
504 alx_write_mem32(hw, ALX_PHY_CTRL, val); in alx_reset_phy()
506 alx_write_mem32(hw, ALX_PHY_CTRL, val | ALX_PHY_CTRL_DSPRST_OUT); in alx_reset_phy()
512 alx_write_phy_dbg(hw, ALX_MIIDBG_LEGCYPS, ALX_LEGCYPS_DEF); in alx_reset_phy()
513 alx_write_phy_dbg(hw, ALX_MIIDBG_SYSMODCTRL, in alx_reset_phy()
515 alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_VDRVBIAS, in alx_reset_phy()
519 val = alx_read_mem32(hw, ALX_LPI_CTRL); in alx_reset_phy()
520 alx_write_mem32(hw, ALX_LPI_CTRL, val & ~ALX_LPI_CTRL_EN); in alx_reset_phy()
521 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_LOCAL_EEEADV, 0); in alx_reset_phy()
524 alx_write_phy_dbg(hw, ALX_MIIDBG_TST10BTCFG, ALX_TST10BTCFG_DEF); in alx_reset_phy()
525 alx_write_phy_dbg(hw, ALX_MIIDBG_SRDSYSMOD, ALX_SRDSYSMOD_DEF); in alx_reset_phy()
526 alx_write_phy_dbg(hw, ALX_MIIDBG_TST100BTCFG, ALX_TST100BTCFG_DEF); in alx_reset_phy()
527 alx_write_phy_dbg(hw, ALX_MIIDBG_ANACTRL, ALX_ANACTRL_DEF); in alx_reset_phy()
528 alx_read_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, &phy_val); in alx_reset_phy()
529 alx_write_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, in alx_reset_phy()
532 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_NLP78, in alx_reset_phy()
534 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_S3DIG10, in alx_reset_phy()
537 if (hw->lnk_patch) { in alx_reset_phy()
539 alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL3, in alx_reset_phy()
541 alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL3, in alx_reset_phy()
544 alx_read_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, &phy_val); in alx_reset_phy()
545 alx_write_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, in alx_reset_phy()
548 alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL5, in alx_reset_phy()
550 alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL5, in alx_reset_phy()
555 alx_write_phy_reg(hw, ALX_MII_IER, ALX_IER_LINK_UP | ALX_IER_LINK_DOWN); in alx_reset_phy()
560 void alx_reset_pcie(struct alx_hw *hw) in alx_reset_pcie() argument
562 u8 rev = alx_hw_revision(hw); in alx_reset_pcie()
567 pci_read_config_word(hw->pdev, PCI_COMMAND, &val16); in alx_reset_pcie()
570 pci_write_config_word(hw->pdev, PCI_COMMAND, val16); in alx_reset_pcie()
574 val = alx_read_mem32(hw, ALX_WOL0); in alx_reset_pcie()
575 alx_write_mem32(hw, ALX_WOL0, 0); in alx_reset_pcie()
577 val = alx_read_mem32(hw, ALX_PDLL_TRNS1); in alx_reset_pcie()
578 alx_write_mem32(hw, ALX_PDLL_TRNS1, val & ~ALX_PDLL_TRNS1_D3PLLOFF_EN); in alx_reset_pcie()
581 val = alx_read_mem32(hw, ALX_UE_SVRT); in alx_reset_pcie()
583 alx_write_mem32(hw, ALX_UE_SVRT, val); in alx_reset_pcie()
586 val = alx_read_mem32(hw, ALX_MASTER); in alx_reset_pcie()
587 if (alx_is_rev_a(rev) && alx_hw_with_cr(hw)) { in alx_reset_pcie()
590 alx_write_mem32(hw, ALX_MASTER, in alx_reset_pcie()
596 alx_write_mem32(hw, ALX_MASTER, in alx_reset_pcie()
602 alx_enable_aspm(hw, true, true); in alx_reset_pcie()
607 void alx_start_mac(struct alx_hw *hw) in alx_start_mac() argument
611 rxq = alx_read_mem32(hw, ALX_RXQ0); in alx_start_mac()
612 alx_write_mem32(hw, ALX_RXQ0, rxq | ALX_RXQ0_EN); in alx_start_mac()
613 txq = alx_read_mem32(hw, ALX_TXQ0); in alx_start_mac()
614 alx_write_mem32(hw, ALX_TXQ0, txq | ALX_TXQ0_EN); in alx_start_mac()
616 mac = hw->rx_ctrl; in alx_start_mac()
617 if (hw->duplex == DUPLEX_FULL) in alx_start_mac()
622 hw->link_speed == SPEED_1000 ? ALX_MAC_CTRL_SPEED_1000 : in alx_start_mac()
625 hw->rx_ctrl = mac; in alx_start_mac()
626 alx_write_mem32(hw, ALX_MAC_CTRL, mac); in alx_start_mac()
629 void alx_cfg_mac_flowcontrol(struct alx_hw *hw, u8 fc) in alx_cfg_mac_flowcontrol() argument
632 hw->rx_ctrl |= ALX_MAC_CTRL_RXFC_EN; in alx_cfg_mac_flowcontrol()
634 hw->rx_ctrl &= ~ALX_MAC_CTRL_RXFC_EN; in alx_cfg_mac_flowcontrol()
637 hw->rx_ctrl |= ALX_MAC_CTRL_TXFC_EN; in alx_cfg_mac_flowcontrol()
639 hw->rx_ctrl &= ~ALX_MAC_CTRL_TXFC_EN; in alx_cfg_mac_flowcontrol()
641 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); in alx_cfg_mac_flowcontrol()
644 void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en) in alx_enable_aspm() argument
647 u8 rev = alx_hw_revision(hw); in alx_enable_aspm()
649 pmctrl = alx_read_mem32(hw, ALX_PMCTRL); in alx_enable_aspm()
668 if (alx_is_rev_a(rev) && alx_hw_with_cr(hw)) in alx_enable_aspm()
676 alx_write_mem32(hw, ALX_PMCTRL, pmctrl); in alx_enable_aspm()
680 static u32 ethadv_to_hw_cfg(struct alx_hw *hw, u32 ethadv_cfg) in ethadv_to_hw_cfg() argument
722 int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl) in alx_setup_speed_duplex() argument
728 alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, 0); in alx_setup_speed_duplex()
729 val = alx_read_mem32(hw, ALX_DRV); in alx_setup_speed_duplex()
746 if (alx_hw_giga(hw)) in alx_setup_speed_duplex()
751 if (alx_write_phy_reg(hw, MII_ADVERTISE, adv) || in alx_setup_speed_duplex()
752 alx_write_phy_reg(hw, MII_CTRL1000, giga) || in alx_setup_speed_duplex()
753 alx_write_phy_reg(hw, MII_BMCR, cr)) in alx_setup_speed_duplex()
764 err = alx_write_phy_reg(hw, MII_BMCR, cr); in alx_setup_speed_duplex()
768 alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, ALX_PHY_INITED); in alx_setup_speed_duplex()
769 val |= ethadv_to_hw_cfg(hw, ethadv); in alx_setup_speed_duplex()
772 alx_write_mem32(hw, ALX_DRV, val); in alx_setup_speed_duplex()
778 void alx_post_phy_link(struct alx_hw *hw) in alx_post_phy_link() argument
781 u8 revid = alx_hw_revision(hw); in alx_post_phy_link()
788 if (hw->link_speed != SPEED_UNKNOWN) { in alx_post_phy_link()
789 alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL6, in alx_post_phy_link()
792 alx_read_phy_dbg(hw, ALX_MIIDBG_AGC, &phy_val); in alx_post_phy_link()
795 if ((hw->link_speed == SPEED_1000 && in alx_post_phy_link()
798 (hw->link_speed == SPEED_100 && in alx_post_phy_link()
801 alx_write_phy_dbg(hw, ALX_MIIDBG_AZ_ANADECT, in alx_post_phy_link()
803 alx_read_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE, in alx_post_phy_link()
805 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE, in alx_post_phy_link()
808 alx_write_phy_dbg(hw, ALX_MIIDBG_AZ_ANADECT, in alx_post_phy_link()
810 alx_read_phy_ext(hw, ALX_MIIEXT_ANEG, in alx_post_phy_link()
812 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE, in alx_post_phy_link()
817 if (adj_th && hw->lnk_patch) { in alx_post_phy_link()
818 if (hw->link_speed == SPEED_100) { in alx_post_phy_link()
819 alx_write_phy_dbg(hw, ALX_MIIDBG_MSE16DB, in alx_post_phy_link()
821 } else if (hw->link_speed == SPEED_1000) { in alx_post_phy_link()
826 alx_read_phy_dbg(hw, ALX_MIIDBG_MSE20DB, in alx_post_phy_link()
830 alx_write_phy_dbg(hw, ALX_MIIDBG_MSE20DB, in alx_post_phy_link()
835 alx_read_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE, in alx_post_phy_link()
837 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE, in alx_post_phy_link()
840 if (adj_th && hw->lnk_patch) { in alx_post_phy_link()
841 alx_write_phy_dbg(hw, ALX_MIIDBG_MSE16DB, in alx_post_phy_link()
843 alx_read_phy_dbg(hw, ALX_MIIDBG_MSE20DB, &phy_val); in alx_post_phy_link()
846 alx_write_phy_dbg(hw, ALX_MIIDBG_MSE20DB, phy_val); in alx_post_phy_link()
851 bool alx_phy_configured(struct alx_hw *hw) in alx_phy_configured() argument
855 cfg = ethadv_to_hw_cfg(hw, hw->adv_cfg); in alx_phy_configured()
857 hw_cfg = alx_get_phy_config(hw); in alx_phy_configured()
865 int alx_read_phy_link(struct alx_hw *hw) in alx_read_phy_link() argument
867 struct pci_dev *pdev = hw->pdev; in alx_read_phy_link()
871 err = alx_read_phy_reg(hw, MII_BMSR, &bmsr); in alx_read_phy_link()
875 err = alx_read_phy_reg(hw, MII_BMSR, &bmsr); in alx_read_phy_link()
880 hw->link_speed = SPEED_UNKNOWN; in alx_read_phy_link()
881 hw->duplex = DUPLEX_UNKNOWN; in alx_read_phy_link()
886 err = alx_read_phy_reg(hw, ALX_MII_GIGA_PSSR, &giga); in alx_read_phy_link()
895 hw->link_speed = SPEED_1000; in alx_read_phy_link()
898 hw->link_speed = SPEED_100; in alx_read_phy_link()
901 hw->link_speed = SPEED_10; in alx_read_phy_link()
907 hw->duplex = (giga & ALX_GIGA_PSSR_DPLX) ? DUPLEX_FULL : DUPLEX_HALF; in alx_read_phy_link()
915 int alx_clear_phy_intr(struct alx_hw *hw) in alx_clear_phy_intr() argument
920 return alx_read_phy_reg(hw, ALX_MII_ISR, &isr); in alx_clear_phy_intr()
923 void alx_disable_rss(struct alx_hw *hw) in alx_disable_rss() argument
925 u32 ctrl = alx_read_mem32(hw, ALX_RXQ0); in alx_disable_rss()
928 alx_write_mem32(hw, ALX_RXQ0, ctrl); in alx_disable_rss()
931 void alx_configure_basic(struct alx_hw *hw) in alx_configure_basic() argument
935 u8 chip_rev = alx_hw_revision(hw); in alx_configure_basic()
937 alx_set_macaddr(hw, hw->mac_addr); in alx_configure_basic()
939 alx_write_mem32(hw, ALX_CLK_GATE, ALX_CLK_GATE_ALL); in alx_configure_basic()
943 alx_write_mem32(hw, ALX_IDLE_DECISN_TIMER, in alx_configure_basic()
946 alx_write_mem32(hw, ALX_SMB_TIMER, hw->smb_timer * 500UL); in alx_configure_basic()
948 val = alx_read_mem32(hw, ALX_MASTER); in alx_configure_basic()
952 alx_write_mem32(hw, ALX_MASTER, val); in alx_configure_basic()
953 alx_write_mem32(hw, ALX_IRQ_MODU_TIMER, in alx_configure_basic()
954 (hw->imt >> 1) << ALX_IRQ_MODU_TIMER1_SHIFT); in alx_configure_basic()
956 alx_write_mem32(hw, ALX_INT_RETRIG, ALX_INT_RETRIG_TO); in alx_configure_basic()
958 alx_write_mem32(hw, ALX_TINT_TPD_THRSHLD, hw->ith_tpd); in alx_configure_basic()
959 alx_write_mem32(hw, ALX_TINT_TIMER, hw->imt); in alx_configure_basic()
961 raw_mtu = ALX_RAW_MTU(hw->mtu); in alx_configure_basic()
962 alx_write_mem32(hw, ALX_MTU, raw_mtu); in alx_configure_basic()
964 hw->rx_ctrl &= ~ALX_MAC_CTRL_FAST_PAUSE; in alx_configure_basic()
970 alx_write_mem32(hw, ALX_TXQ1, val | ALX_TXQ1_ERRLGPKT_DROP_EN); in alx_configure_basic()
972 max_payload = pcie_get_readrq(hw->pdev) >> 8; in alx_configure_basic()
978 pcie_set_readrq(hw->pdev, 128 << ALX_DEV_CTRL_MAXRRS_MIN); in alx_configure_basic()
984 alx_write_mem32(hw, ALX_TXQ0, val); in alx_configure_basic()
989 alx_write_mem32(hw, ALX_HQTPD, val); in alx_configure_basic()
992 val = alx_read_mem32(hw, ALX_SRAM5); in alx_configure_basic()
1001 alx_write_mem32(hw, ALX_RXQ2, in alx_configure_basic()
1010 if (alx_hw_giga(hw)) in alx_configure_basic()
1014 alx_write_mem32(hw, ALX_RXQ0, val); in alx_configure_basic()
1016 val = alx_read_mem32(hw, ALX_DMA); in alx_configure_basic()
1022 (hw->dma_chnl - 1) << ALX_DMA_RCHNL_SEL_SHIFT; in alx_configure_basic()
1023 alx_write_mem32(hw, ALX_DMA, val); in alx_configure_basic()
1031 alx_write_mem32(hw, ALX_WRR, val); in alx_configure_basic()
1034 void alx_mask_msix(struct alx_hw *hw, int index, bool mask) in alx_mask_msix() argument
1043 alx_write_mem32(hw, reg, val); in alx_mask_msix()
1044 alx_post_write(hw); in alx_mask_msix()
1048 bool alx_get_phy_info(struct alx_hw *hw) in alx_get_phy_info() argument
1052 if (alx_read_phy_reg(hw, MII_PHYSID1, &hw->phy_id[0]) || in alx_get_phy_info()
1053 alx_read_phy_reg(hw, MII_PHYSID2, &hw->phy_id[1])) in alx_get_phy_info()
1060 if (alx_read_phy_ext(hw, 3, MDIO_DEVS1, &devs1) || in alx_get_phy_info()
1061 alx_read_phy_ext(hw, 3, MDIO_DEVS2, &devs2)) in alx_get_phy_info()
1063 hw->mdio.mmds = devs1 | devs2 << 16; in alx_get_phy_info()
1068 void alx_update_hw_stats(struct alx_hw *hw) in alx_update_hw_stats() argument
1071 hw->stats.rx_ok += alx_read_mem32(hw, ALX_MIB_RX_OK); in alx_update_hw_stats()
1072 hw->stats.rx_bcast += alx_read_mem32(hw, ALX_MIB_RX_BCAST); in alx_update_hw_stats()
1073 hw->stats.rx_mcast += alx_read_mem32(hw, ALX_MIB_RX_MCAST); in alx_update_hw_stats()
1074 hw->stats.rx_pause += alx_read_mem32(hw, ALX_MIB_RX_PAUSE); in alx_update_hw_stats()
1075 hw->stats.rx_ctrl += alx_read_mem32(hw, ALX_MIB_RX_CTRL); in alx_update_hw_stats()
1076 hw->stats.rx_fcs_err += alx_read_mem32(hw, ALX_MIB_RX_FCS_ERR); in alx_update_hw_stats()
1077 hw->stats.rx_len_err += alx_read_mem32(hw, ALX_MIB_RX_LEN_ERR); in alx_update_hw_stats()
1078 hw->stats.rx_byte_cnt += alx_read_mem32(hw, ALX_MIB_RX_BYTE_CNT); in alx_update_hw_stats()
1079 hw->stats.rx_runt += alx_read_mem32(hw, ALX_MIB_RX_RUNT); in alx_update_hw_stats()
1080 hw->stats.rx_frag += alx_read_mem32(hw, ALX_MIB_RX_FRAG); in alx_update_hw_stats()
1081 hw->stats.rx_sz_64B += alx_read_mem32(hw, ALX_MIB_RX_SZ_64B); in alx_update_hw_stats()
1082 hw->stats.rx_sz_127B += alx_read_mem32(hw, ALX_MIB_RX_SZ_127B); in alx_update_hw_stats()
1083 hw->stats.rx_sz_255B += alx_read_mem32(hw, ALX_MIB_RX_SZ_255B); in alx_update_hw_stats()
1084 hw->stats.rx_sz_511B += alx_read_mem32(hw, ALX_MIB_RX_SZ_511B); in alx_update_hw_stats()
1085 hw->stats.rx_sz_1023B += alx_read_mem32(hw, ALX_MIB_RX_SZ_1023B); in alx_update_hw_stats()
1086 hw->stats.rx_sz_1518B += alx_read_mem32(hw, ALX_MIB_RX_SZ_1518B); in alx_update_hw_stats()
1087 hw->stats.rx_sz_max += alx_read_mem32(hw, ALX_MIB_RX_SZ_MAX); in alx_update_hw_stats()
1088 hw->stats.rx_ov_sz += alx_read_mem32(hw, ALX_MIB_RX_OV_SZ); in alx_update_hw_stats()
1089 hw->stats.rx_ov_rxf += alx_read_mem32(hw, ALX_MIB_RX_OV_RXF); in alx_update_hw_stats()
1090 hw->stats.rx_ov_rrd += alx_read_mem32(hw, ALX_MIB_RX_OV_RRD); in alx_update_hw_stats()
1091 hw->stats.rx_align_err += alx_read_mem32(hw, ALX_MIB_RX_ALIGN_ERR); in alx_update_hw_stats()
1092 hw->stats.rx_bc_byte_cnt += alx_read_mem32(hw, ALX_MIB_RX_BCCNT); in alx_update_hw_stats()
1093 hw->stats.rx_mc_byte_cnt += alx_read_mem32(hw, ALX_MIB_RX_MCCNT); in alx_update_hw_stats()
1094 hw->stats.rx_err_addr += alx_read_mem32(hw, ALX_MIB_RX_ERRADDR); in alx_update_hw_stats()
1097 hw->stats.tx_ok += alx_read_mem32(hw, ALX_MIB_TX_OK); in alx_update_hw_stats()
1098 hw->stats.tx_bcast += alx_read_mem32(hw, ALX_MIB_TX_BCAST); in alx_update_hw_stats()
1099 hw->stats.tx_mcast += alx_read_mem32(hw, ALX_MIB_TX_MCAST); in alx_update_hw_stats()
1100 hw->stats.tx_pause += alx_read_mem32(hw, ALX_MIB_TX_PAUSE); in alx_update_hw_stats()
1101 hw->stats.tx_exc_defer += alx_read_mem32(hw, ALX_MIB_TX_EXC_DEFER); in alx_update_hw_stats()
1102 hw->stats.tx_ctrl += alx_read_mem32(hw, ALX_MIB_TX_CTRL); in alx_update_hw_stats()
1103 hw->stats.tx_defer += alx_read_mem32(hw, ALX_MIB_TX_DEFER); in alx_update_hw_stats()
1104 hw->stats.tx_byte_cnt += alx_read_mem32(hw, ALX_MIB_TX_BYTE_CNT); in alx_update_hw_stats()
1105 hw->stats.tx_sz_64B += alx_read_mem32(hw, ALX_MIB_TX_SZ_64B); in alx_update_hw_stats()
1106 hw->stats.tx_sz_127B += alx_read_mem32(hw, ALX_MIB_TX_SZ_127B); in alx_update_hw_stats()
1107 hw->stats.tx_sz_255B += alx_read_mem32(hw, ALX_MIB_TX_SZ_255B); in alx_update_hw_stats()
1108 hw->stats.tx_sz_511B += alx_read_mem32(hw, ALX_MIB_TX_SZ_511B); in alx_update_hw_stats()
1109 hw->stats.tx_sz_1023B += alx_read_mem32(hw, ALX_MIB_TX_SZ_1023B); in alx_update_hw_stats()
1110 hw->stats.tx_sz_1518B += alx_read_mem32(hw, ALX_MIB_TX_SZ_1518B); in alx_update_hw_stats()
1111 hw->stats.tx_sz_max += alx_read_mem32(hw, ALX_MIB_TX_SZ_MAX); in alx_update_hw_stats()
1112 hw->stats.tx_single_col += alx_read_mem32(hw, ALX_MIB_TX_SINGLE_COL); in alx_update_hw_stats()
1113 hw->stats.tx_multi_col += alx_read_mem32(hw, ALX_MIB_TX_MULTI_COL); in alx_update_hw_stats()
1114 hw->stats.tx_late_col += alx_read_mem32(hw, ALX_MIB_TX_LATE_COL); in alx_update_hw_stats()
1115 hw->stats.tx_abort_col += alx_read_mem32(hw, ALX_MIB_TX_ABORT_COL); in alx_update_hw_stats()
1116 hw->stats.tx_underrun += alx_read_mem32(hw, ALX_MIB_TX_UNDERRUN); in alx_update_hw_stats()
1117 hw->stats.tx_trd_eop += alx_read_mem32(hw, ALX_MIB_TX_TRD_EOP); in alx_update_hw_stats()
1118 hw->stats.tx_len_err += alx_read_mem32(hw, ALX_MIB_TX_LEN_ERR); in alx_update_hw_stats()
1119 hw->stats.tx_trunc += alx_read_mem32(hw, ALX_MIB_TX_TRUNC); in alx_update_hw_stats()
1120 hw->stats.tx_bc_byte_cnt += alx_read_mem32(hw, ALX_MIB_TX_BCCNT); in alx_update_hw_stats()
1121 hw->stats.tx_mc_byte_cnt += alx_read_mem32(hw, ALX_MIB_TX_MCCNT); in alx_update_hw_stats()
1123 hw->stats.update += alx_read_mem32(hw, ALX_MIB_UPDATE); in alx_update_hw_stats()