73  * and another 16 bytes to allow us to align the dma command
74  * buffers on a 16 byte boundary.
305     out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16);  in dbdma_reset()
319     volatile struct mace __iomem *mb = mp->mace;  in mace_reset()  local
325 	out_8(&mb->biucc, SWRST);  in mace_reset()
326 	if (in_8(&mb->biucc) & SWRST) {  in mace_reset()
337     out_8(&mb->imr, 0xff);	/* disable all intrs for now */  in mace_reset()
338     i = in_8(&mb->ir);  in mace_reset()
339     out_8(&mb->maccc, 0);	/* turn off tx, rx */  in mace_reset()
341     out_8(&mb->biucc, XMTSP_64);  in mace_reset()
342     out_8(&mb->utr, RTRD);  in mace_reset()
343     out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);  in mace_reset()
344     out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */  in mace_reset()
345     out_8(&mb->rcvfc, 0);  in mace_reset()
352 	out_8(&mb->iac, LOGADDR);  in mace_reset()
354 	out_8(&mb->iac, ADDRCHG | LOGADDR);  in mace_reset()
355 	while ((in_8(&mb->iac) & ADDRCHG) != 0)  in mace_reset()
359 	out_8(&mb->ladrf, 0);  in mace_reset()
363 	out_8(&mb->iac, 0);  in mace_reset()
366 	out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO);  in mace_reset()
368 	out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO);  in mace_reset()
374     volatile struct mace __iomem *mb = mp->mace;  in __mace_set_address()  local
381 	out_8(&mb->iac, PHYADDR);  in __mace_set_address()
383 	out_8(&mb->iac, ADDRCHG | PHYADDR);  in __mace_set_address()
384 	while ((in_8(&mb->iac) & ADDRCHG) != 0)  in __mace_set_address()
388         out_8(&mb->padr, macaddr[i] = p[i]);  in __mace_set_address()
393         out_8(&mb->iac, 0);  in __mace_set_address()
399     volatile struct mace __iomem *mb = mp->mace;  in mace_set_address()  local
407     out_8(&mb->maccc, mp->maccc);  in mace_set_address()
434     volatile struct mace __iomem *mb = mp->mace;  in mace_open()  local
475     out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */  in mace_open()
477     out_le32(&rd->control, (RUN << 16) | RUN);  in mace_open()
485     out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16);  in mace_open()
494     out_8(&mb->maccc, mp->maccc);  in mace_open()
496     out_8(&mb->imr, RCVINT);  in mace_open()
504     volatile struct mace __iomem *mb = mp->mace;  in mace_close()  local
509     out_8(&mb->maccc, 0);  in mace_close()
510     out_8(&mb->imr, 0xff);		/* disable all intrs */  in mace_close()
513     rd->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */  in mace_close()
514     td->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */  in mace_close()
574 	out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));  in mace_xmit_start()
590     volatile struct mace __iomem *mb = mp->mace;  in mace_set_multicast()  local
623 	    out_8(&mb->iac, LOGADDR);  in mace_set_multicast()
625 	    out_8(&mb->iac, ADDRCHG | LOGADDR);  in mace_set_multicast()
626 	    while ((in_8(&mb->iac) & ADDRCHG) != 0)  in mace_set_multicast()
630 	    out_8(&mb->ladrf, multicast_filter[i]);  in mace_set_multicast()
632 	    out_8(&mb->iac, 0);  in mace_set_multicast()
635     out_8(&mb->maccc, mp->maccc);  in mace_set_multicast()
641     volatile struct mace __iomem *mb = mp->mace;  in mace_handle_misc_intrs()  local
646     dev->stats.rx_missed_errors += in_8(&mb->mpc);   /* reading clears it */  in mace_handle_misc_intrs()
649     dev->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */  in mace_handle_misc_intrs()
664     volatile struct mace __iomem *mb = mp->mace;  in mace_interrupt()  local
673     intr = in_8(&mb->ir);		/* read interrupt register */  in mace_interrupt()
674     in_8(&mb->xmtrc);			/* get retries */  in mace_interrupt()
678     while (in_8(&mb->pr) & XMTSV) {  in mace_interrupt()
686 	intr = in_8(&mb->ir);  in mace_interrupt()
690 	    fs = in_8(&mb->xmtfs);  in mace_interrupt()
692 	    out_8(&mb->xmtfc, AUTO_PAD_XMIT);  in mace_interrupt()
697 	out_le32(&td->control, RUN << 16);  in mace_interrupt()
702 	xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;  in mace_interrupt()
715 	    out_8(&mb->xmtfc, DXMTFCS);  in mace_interrupt()
717 	fs = in_8(&mb->xmtfs);  in mace_interrupt()
735 	    x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;  in mace_interrupt()
747 		out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT);  in mace_interrupt()
748 		out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU);  in mace_interrupt()
750 		out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT);  in mace_interrupt()
751 		out_8(&mb->xmtfc, AUTO_PAD_XMIT);  in mace_interrupt()
799 	out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));  in mace_interrupt()
810     volatile struct mace __iomem *mb = mp->mace;  in mace_tx_timeout()  local
823     mace_handle_misc_intrs(mp, in_8(&mb->ir), dev);  in mace_tx_timeout()
828     out_8(&mb->maccc, 0);  in mace_tx_timeout()
838     out_le32(&rd->control, (RUN << 16) | RUN);  in mace_tx_timeout()
859 	out_le32(&td->control, (RUN << 16) | RUN);  in mace_tx_timeout()
865     out_8(&mb->imr, RCVINT);  in mace_tx_timeout()
866     out_8(&mb->maccc, mp->maccc);  in mace_tx_timeout()
973 	    out_le32(&rd->control, (PAUSE << 16) | PAUSE);  in mace_rxdma_intr()
981 	out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE));  in mace_rxdma_intr()