125 #include "xgbe-common.h"
127 #define XGBE_BLWC_PROPERTY		"amd,serdes-blwc"
128 #define XGBE_CDR_RATE_PROPERTY		"amd,serdes-cdr-rate"
129 #define XGBE_PQ_SKEW_PROPERTY		"amd,serdes-pq-skew"
130 #define XGBE_TX_AMP_PROPERTY		"amd,serdes-tx-amp"
131 #define XGBE_DFE_CFG_PROPERTY		"amd,serdes-dfe-tap-config"
132 #define XGBE_DFE_ENA_PROPERTY		"amd,serdes-dfe-tap-enable"
165 /* Rate-change complete wait/retry count */
234 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;  in xgbe_phy_an_outcome()
235 	struct xgbe_phy_data *phy_data = pdata->phy_data;  in xgbe_phy_an_outcome()
236 	enum xgbe_mode mode;  in xgbe_phy_an_outcome()  local
250 	if (pdata->phy.pause_autoneg) {  in xgbe_phy_an_outcome()
251 		/* Set flow control based on auto-negotiation result */  in xgbe_phy_an_outcome()
252 		pdata->phy.tx_pause = 0;  in xgbe_phy_an_outcome()
253 		pdata->phy.rx_pause = 0;  in xgbe_phy_an_outcome()
256 			pdata->phy.tx_pause = 1;  in xgbe_phy_an_outcome()
257 			pdata->phy.rx_pause = 1;  in xgbe_phy_an_outcome()
260 				pdata->phy.rx_pause = 1;  in xgbe_phy_an_outcome()
262 				pdata->phy.tx_pause = 1;  in xgbe_phy_an_outcome()
272 		if (phy_data->speed_set == XGBE_SPEEDSET_2500_10000)  in xgbe_phy_an_outcome()
280 		mode = XGBE_MODE_KR;  in xgbe_phy_an_outcome()
282 		if (phy_data->speed_set == XGBE_SPEEDSET_2500_10000)  in xgbe_phy_an_outcome()
283 			mode = XGBE_MODE_KX_2500;  in xgbe_phy_an_outcome()
285 			mode = XGBE_MODE_KX_1000;  in xgbe_phy_an_outcome()
287 		mode = XGBE_MODE_UNKNOWN;  in xgbe_phy_an_outcome()
296 	return mode;  in xgbe_phy_an_outcome()
302 	struct ethtool_link_ksettings *slks = &pdata->phy.lks;  in xgbe_phy_an_advertising()
320 	unsigned int reg;  in xgbe_phy_pcs_power_cycle()  local
322 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);  in xgbe_phy_pcs_power_cycle()
324 	reg |= MDIO_CTRL1_LPOWER;  in xgbe_phy_pcs_power_cycle()
325 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);  in xgbe_phy_pcs_power_cycle()
329 	reg &= ~MDIO_CTRL1_LPOWER;  in xgbe_phy_pcs_power_cycle()
330 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);  in xgbe_phy_pcs_power_cycle()
349 	while (wait--) {  in xgbe_phy_complete_ratechange()
358 	netif_dbg(pdata, link, pdata->netdev, "SerDes rx/tx not ready (%#hx)\n",  in xgbe_phy_complete_ratechange()
369 	struct xgbe_phy_data *phy_data = pdata->phy_data;  in xgbe_phy_kr_mode()
370 	unsigned int reg;  in xgbe_phy_kr_mode()  local
373 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);  in xgbe_phy_kr_mode()
374 	reg &= ~MDIO_PCS_CTRL2_TYPE;  in xgbe_phy_kr_mode()
375 	reg |= MDIO_PCS_CTRL2_10GBR;  in xgbe_phy_kr_mode()
376 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);  in xgbe_phy_kr_mode()
378 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);  in xgbe_phy_kr_mode()
379 	reg &= ~MDIO_CTRL1_SPEEDSEL;  in xgbe_phy_kr_mode()
380 	reg |= MDIO_CTRL1_SPEED10G;  in xgbe_phy_kr_mode()
381 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);  in xgbe_phy_kr_mode()
393 			   phy_data->cdr_rate[XGBE_SPEED_10000]);  in xgbe_phy_kr_mode()
395 			   phy_data->tx_amp[XGBE_SPEED_10000]);  in xgbe_phy_kr_mode()
397 			   phy_data->blwc[XGBE_SPEED_10000]);  in xgbe_phy_kr_mode()
399 			   phy_data->pq_skew[XGBE_SPEED_10000]);  in xgbe_phy_kr_mode()
401 			   phy_data->dfe_tap_cfg[XGBE_SPEED_10000]);  in xgbe_phy_kr_mode()
403 		      phy_data->dfe_tap_ena[XGBE_SPEED_10000]);  in xgbe_phy_kr_mode()
407 	netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");  in xgbe_phy_kr_mode()
412 	struct xgbe_phy_data *phy_data = pdata->phy_data;  in xgbe_phy_kx_2500_mode()
413 	unsigned int reg;  in xgbe_phy_kx_2500_mode()  local
416 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);  in xgbe_phy_kx_2500_mode()
417 	reg &= ~MDIO_PCS_CTRL2_TYPE;  in xgbe_phy_kx_2500_mode()
418 	reg |= MDIO_PCS_CTRL2_10GBX;  in xgbe_phy_kx_2500_mode()
419 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);  in xgbe_phy_kx_2500_mode()
421 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);  in xgbe_phy_kx_2500_mode()
422 	reg &= ~MDIO_CTRL1_SPEEDSEL;  in xgbe_phy_kx_2500_mode()
423 	reg |= MDIO_CTRL1_SPEED1G;  in xgbe_phy_kx_2500_mode()
424 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);  in xgbe_phy_kx_2500_mode()
436 			   phy_data->cdr_rate[XGBE_SPEED_2500]);  in xgbe_phy_kx_2500_mode()
438 			   phy_data->tx_amp[XGBE_SPEED_2500]);  in xgbe_phy_kx_2500_mode()
440 			   phy_data->blwc[XGBE_SPEED_2500]);  in xgbe_phy_kx_2500_mode()
442 			   phy_data->pq_skew[XGBE_SPEED_2500]);  in xgbe_phy_kx_2500_mode()
444 			   phy_data->dfe_tap_cfg[XGBE_SPEED_2500]);  in xgbe_phy_kx_2500_mode()
446 		      phy_data->dfe_tap_ena[XGBE_SPEED_2500]);  in xgbe_phy_kx_2500_mode()
450 	netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");  in xgbe_phy_kx_2500_mode()
455 	struct xgbe_phy_data *phy_data = pdata->phy_data;  in xgbe_phy_kx_1000_mode()
456 	unsigned int reg;  in xgbe_phy_kx_1000_mode()  local
459 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);  in xgbe_phy_kx_1000_mode()
460 	reg &= ~MDIO_PCS_CTRL2_TYPE;  in xgbe_phy_kx_1000_mode()
461 	reg |= MDIO_PCS_CTRL2_10GBX;  in xgbe_phy_kx_1000_mode()
462 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);  in xgbe_phy_kx_1000_mode()
464 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);  in xgbe_phy_kx_1000_mode()
465 	reg &= ~MDIO_CTRL1_SPEEDSEL;  in xgbe_phy_kx_1000_mode()
466 	reg |= MDIO_CTRL1_SPEED1G;  in xgbe_phy_kx_1000_mode()
467 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);  in xgbe_phy_kx_1000_mode()
479 			   phy_data->cdr_rate[XGBE_SPEED_1000]);  in xgbe_phy_kx_1000_mode()
481 			   phy_data->tx_amp[XGBE_SPEED_1000]);  in xgbe_phy_kx_1000_mode()
483 			   phy_data->blwc[XGBE_SPEED_1000]);  in xgbe_phy_kx_1000_mode()
485 			   phy_data->pq_skew[XGBE_SPEED_1000]);  in xgbe_phy_kx_1000_mode()
487 			   phy_data->dfe_tap_cfg[XGBE_SPEED_1000]);  in xgbe_phy_kx_1000_mode()
489 		      phy_data->dfe_tap_ena[XGBE_SPEED_1000]);  in xgbe_phy_kx_1000_mode()
493 	netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");  in xgbe_phy_kx_1000_mode()
498 	struct xgbe_phy_data *phy_data = pdata->phy_data;  in xgbe_phy_cur_mode()
499 	enum xgbe_mode mode;  in xgbe_phy_cur_mode()  local
500 	unsigned int reg;  in xgbe_phy_cur_mode()  local
502 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);  in xgbe_phy_cur_mode()
503 	reg &= MDIO_PCS_CTRL2_TYPE;  in xgbe_phy_cur_mode()
505 	if (reg == MDIO_PCS_CTRL2_10GBR) {  in xgbe_phy_cur_mode()
506 		mode = XGBE_MODE_KR;  in xgbe_phy_cur_mode()
508 		if (phy_data->speed_set == XGBE_SPEEDSET_2500_10000)  in xgbe_phy_cur_mode()
509 			mode = XGBE_MODE_KX_2500;  in xgbe_phy_cur_mode()
511 			mode = XGBE_MODE_KX_1000;  in xgbe_phy_cur_mode()
514 	return mode;  in xgbe_phy_cur_mode()
519 	struct xgbe_phy_data *phy_data = pdata->phy_data;  in xgbe_phy_switch_mode()
520 	enum xgbe_mode mode;  in xgbe_phy_switch_mode()  local
522 	/* If we are in KR switch to KX, and vice-versa */  in xgbe_phy_switch_mode()
524 		if (phy_data->speed_set == XGBE_SPEEDSET_2500_10000)  in xgbe_phy_switch_mode()
525 			mode = XGBE_MODE_KX_2500;  in xgbe_phy_switch_mode()
527 			mode = XGBE_MODE_KX_1000;  in xgbe_phy_switch_mode()
529 		mode = XGBE_MODE_KR;  in xgbe_phy_switch_mode()
532 	return mode;  in xgbe_phy_switch_mode()
538 	struct xgbe_phy_data *phy_data = pdata->phy_data;  in xgbe_phy_get_mode()
542 		return (phy_data->speed_set == XGBE_SPEEDSET_1000_10000)  in xgbe_phy_get_mode()
545 		return (phy_data->speed_set == XGBE_SPEEDSET_2500_10000)  in xgbe_phy_get_mode()
554 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)  in xgbe_phy_set_mode()  argument
556 	switch (mode) {  in xgbe_phy_set_mode()
572 				enum xgbe_mode mode, bool advert)  in xgbe_phy_check_mode()  argument
574 	if (pdata->phy.autoneg == AUTONEG_ENABLE) {  in xgbe_phy_check_mode()
579 		cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);  in xgbe_phy_check_mode()
580 		if (cur_mode == mode)  in xgbe_phy_check_mode()
587 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)  in xgbe_phy_use_mode()  argument
589 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;  in xgbe_phy_use_mode()
591 	switch (mode) {  in xgbe_phy_use_mode()
593 		return xgbe_phy_check_mode(pdata, mode,  in xgbe_phy_use_mode()
596 		return xgbe_phy_check_mode(pdata, mode,  in xgbe_phy_use_mode()
599 		return xgbe_phy_check_mode(pdata, mode,  in xgbe_phy_use_mode()
608 	struct xgbe_phy_data *phy_data = pdata->phy_data;  in xgbe_phy_valid_speed()
612 		if (phy_data->speed_set != XGBE_SPEEDSET_1000_10000)  in xgbe_phy_valid_speed()
616 		if (phy_data->speed_set != XGBE_SPEEDSET_2500_10000)  in xgbe_phy_valid_speed()
628 	unsigned int reg;  in xgbe_phy_link_status()  local
635 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);  in xgbe_phy_link_status()
636 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);  in xgbe_phy_link_status()
638 	return (reg & MDIO_STAT1_LSTATUS) ? 1 : 0;  in xgbe_phy_link_status()
654 	unsigned int reg, count;  in xgbe_phy_reset()  local
657 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);  in xgbe_phy_reset()
658 	reg |= MDIO_CTRL1_RESET;  in xgbe_phy_reset()
659 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);  in xgbe_phy_reset()
664 		reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);  in xgbe_phy_reset()
665 	} while ((reg & MDIO_CTRL1_RESET) && --count);  in xgbe_phy_reset()
667 	if (reg & MDIO_CTRL1_RESET)  in xgbe_phy_reset()
668 		return -ETIMEDOUT;  in xgbe_phy_reset()
680 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;  in xgbe_phy_init()
684 	phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);  in xgbe_phy_init()
686 		return -ENOMEM;  in xgbe_phy_init()
689 	ret = device_property_read_u32(pdata->phy_dev, XGBE_SPEEDSET_PROPERTY,  in xgbe_phy_init()
690 				       &phy_data->speed_set);  in xgbe_phy_init()
692 		dev_err(pdata->dev, "invalid %s property\n",  in xgbe_phy_init()
697 	switch (phy_data->speed_set) {  in xgbe_phy_init()
702 		dev_err(pdata->dev, "invalid %s property\n",  in xgbe_phy_init()
704 		return -EINVAL;  in xgbe_phy_init()
708 	if (device_property_present(pdata->phy_dev, XGBE_BLWC_PROPERTY)) {  in xgbe_phy_init()
709 		ret = device_property_read_u32_array(pdata->phy_dev,  in xgbe_phy_init()
711 						     phy_data->blwc,  in xgbe_phy_init()
714 			dev_err(pdata->dev, "invalid %s property\n",  in xgbe_phy_init()
719 		memcpy(phy_data->blwc, xgbe_phy_blwc,  in xgbe_phy_init()
720 		       sizeof(phy_data->blwc));  in xgbe_phy_init()
723 	if (device_property_present(pdata->phy_dev, XGBE_CDR_RATE_PROPERTY)) {  in xgbe_phy_init()
724 		ret = device_property_read_u32_array(pdata->phy_dev,  in xgbe_phy_init()
726 						     phy_data->cdr_rate,  in xgbe_phy_init()
729 			dev_err(pdata->dev, "invalid %s property\n",  in xgbe_phy_init()
734 		memcpy(phy_data->cdr_rate, xgbe_phy_cdr_rate,  in xgbe_phy_init()
735 		       sizeof(phy_data->cdr_rate));  in xgbe_phy_init()
738 	if (device_property_present(pdata->phy_dev, XGBE_PQ_SKEW_PROPERTY)) {  in xgbe_phy_init()
739 		ret = device_property_read_u32_array(pdata->phy_dev,  in xgbe_phy_init()
741 						     phy_data->pq_skew,  in xgbe_phy_init()
744 			dev_err(pdata->dev, "invalid %s property\n",  in xgbe_phy_init()
749 		memcpy(phy_data->pq_skew, xgbe_phy_pq_skew,  in xgbe_phy_init()
750 		       sizeof(phy_data->pq_skew));  in xgbe_phy_init()
753 	if (device_property_present(pdata->phy_dev, XGBE_TX_AMP_PROPERTY)) {  in xgbe_phy_init()
754 		ret = device_property_read_u32_array(pdata->phy_dev,  in xgbe_phy_init()
756 						     phy_data->tx_amp,  in xgbe_phy_init()
759 			dev_err(pdata->dev, "invalid %s property\n",  in xgbe_phy_init()
764 		memcpy(phy_data->tx_amp, xgbe_phy_tx_amp,  in xgbe_phy_init()
765 		       sizeof(phy_data->tx_amp));  in xgbe_phy_init()
768 	if (device_property_present(pdata->phy_dev, XGBE_DFE_CFG_PROPERTY)) {  in xgbe_phy_init()
769 		ret = device_property_read_u32_array(pdata->phy_dev,  in xgbe_phy_init()
771 						     phy_data->dfe_tap_cfg,  in xgbe_phy_init()
774 			dev_err(pdata->dev, "invalid %s property\n",  in xgbe_phy_init()
779 		memcpy(phy_data->dfe_tap_cfg, xgbe_phy_dfe_tap_cfg,  in xgbe_phy_init()
780 		       sizeof(phy_data->dfe_tap_cfg));  in xgbe_phy_init()
783 	if (device_property_present(pdata->phy_dev, XGBE_DFE_ENA_PROPERTY)) {  in xgbe_phy_init()
784 		ret = device_property_read_u32_array(pdata->phy_dev,  in xgbe_phy_init()
786 						     phy_data->dfe_tap_ena,  in xgbe_phy_init()
789 			dev_err(pdata->dev, "invalid %s property\n",  in xgbe_phy_init()
794 		memcpy(phy_data->dfe_tap_ena, xgbe_phy_dfe_tap_ena,  in xgbe_phy_init()
795 		       sizeof(phy_data->dfe_tap_ena));  in xgbe_phy_init()
805 	switch (phy_data->speed_set) {  in xgbe_phy_init()
814 	if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)  in xgbe_phy_init()
817 	pdata->phy_data = phy_data;  in xgbe_phy_init()
824 	struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;  in xgbe_init_function_ptrs_phy_v1()
826 	phy_impl->init			= xgbe_phy_init;  in xgbe_init_function_ptrs_phy_v1()
827 	phy_impl->exit			= xgbe_phy_exit;  in xgbe_init_function_ptrs_phy_v1()
829 	phy_impl->reset			= xgbe_phy_reset;  in xgbe_init_function_ptrs_phy_v1()
830 	phy_impl->start			= xgbe_phy_start;  in xgbe_init_function_ptrs_phy_v1()
831 	phy_impl->stop			= xgbe_phy_stop;  in xgbe_init_function_ptrs_phy_v1()
833 	phy_impl->link_status		= xgbe_phy_link_status;  in xgbe_init_function_ptrs_phy_v1()
835 	phy_impl->valid_speed		= xgbe_phy_valid_speed;  in xgbe_init_function_ptrs_phy_v1()
837 	phy_impl->use_mode		= xgbe_phy_use_mode;  in xgbe_init_function_ptrs_phy_v1()
838 	phy_impl->set_mode		= xgbe_phy_set_mode;  in xgbe_init_function_ptrs_phy_v1()
839 	phy_impl->get_mode		= xgbe_phy_get_mode;  in xgbe_init_function_ptrs_phy_v1()
840 	phy_impl->switch_mode		= xgbe_phy_switch_mode;  in xgbe_init_function_ptrs_phy_v1()
841 	phy_impl->cur_mode		= xgbe_phy_cur_mode;  in xgbe_init_function_ptrs_phy_v1()
843 	phy_impl->an_mode		= xgbe_phy_an_mode;  in xgbe_init_function_ptrs_phy_v1()
845 	phy_impl->an_config		= xgbe_phy_an_config;  in xgbe_init_function_ptrs_phy_v1()
847 	phy_impl->an_advertising	= xgbe_phy_an_advertising;  in xgbe_init_function_ptrs_phy_v1()
849 	phy_impl->an_outcome		= xgbe_phy_an_outcome;  in xgbe_init_function_ptrs_phy_v1()
851 	phy_impl->kr_training_pre	= xgbe_phy_kr_training_pre;  in xgbe_init_function_ptrs_phy_v1()
852 	phy_impl->kr_training_post	= xgbe_phy_kr_training_post;  in xgbe_init_function_ptrs_phy_v1()