Lines Matching refs:AM2150_MACE_BASE
190 #define AM2150_MACE_BASE 0x10 macro
489 data = inb(ioaddr + AM2150_MACE_BASE + reg); in mace_read()
494 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F)); in mace_read()
516 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg); in mace_write()
521 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F)); in mace_write()
807 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR); in mace_close()
868 ioaddr + AM2150_MACE_BASE + MACE_IMR); in mace_start_xmit()
901 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR); in mace_start_xmit()
937 inb(ioaddr + AM2150_MACE_BASE + MACE_IR), in mace_interrupt()
938 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)); in mace_interrupt()
950 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR); in mace_interrupt()
965 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC); in mace_interrupt()
972 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC); in mace_interrupt()
977 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) & in mace_interrupt()