Lines Matching +full:0 +full:xff00
9 ENA_REGS_RESET_NORMAL = 0,
30 /* 0 base */
31 #define ENA_REGS_VERSION_OFF 0x0
32 #define ENA_REGS_CONTROLLER_VERSION_OFF 0x4
33 #define ENA_REGS_CAPS_OFF 0x8
34 #define ENA_REGS_CAPS_EXT_OFF 0xc
35 #define ENA_REGS_AQ_BASE_LO_OFF 0x10
36 #define ENA_REGS_AQ_BASE_HI_OFF 0x14
37 #define ENA_REGS_AQ_CAPS_OFF 0x18
38 #define ENA_REGS_ACQ_BASE_LO_OFF 0x20
39 #define ENA_REGS_ACQ_BASE_HI_OFF 0x24
40 #define ENA_REGS_ACQ_CAPS_OFF 0x28
41 #define ENA_REGS_AQ_DB_OFF 0x2c
42 #define ENA_REGS_ACQ_TAIL_OFF 0x30
43 #define ENA_REGS_AENQ_CAPS_OFF 0x34
44 #define ENA_REGS_AENQ_BASE_LO_OFF 0x38
45 #define ENA_REGS_AENQ_BASE_HI_OFF 0x3c
46 #define ENA_REGS_AENQ_HEAD_DB_OFF 0x40
47 #define ENA_REGS_AENQ_TAIL_OFF 0x44
48 #define ENA_REGS_INTR_MASK_OFF 0x4c
49 #define ENA_REGS_DEV_CTL_OFF 0x54
50 #define ENA_REGS_DEV_STS_OFF 0x58
51 #define ENA_REGS_MMIO_REG_READ_OFF 0x5c
52 #define ENA_REGS_MMIO_RESP_LO_OFF 0x60
53 #define ENA_REGS_MMIO_RESP_HI_OFF 0x64
54 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF 0x68
57 #define ENA_REGS_VERSION_MINOR_VERSION_MASK 0xff
59 #define ENA_REGS_VERSION_MAJOR_VERSION_MASK 0xff00
62 #define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK 0xff
64 #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK 0xff00
66 #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK 0xff0000
68 #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK 0xff000000
71 #define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x1
73 #define ENA_REGS_CAPS_RESET_TIMEOUT_MASK 0x3e
75 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK 0xff00
77 #define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK 0xf0000
80 #define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK 0xffff
82 #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK 0xffff0000
85 #define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK 0xffff
87 #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK 0xffff0000
90 #define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK 0xffff
92 #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK 0xffff0000
95 #define ENA_REGS_DEV_CTL_DEV_RESET_MASK 0x1
97 #define ENA_REGS_DEV_CTL_AQ_RESTART_MASK 0x2
99 #define ENA_REGS_DEV_CTL_QUIESCENT_MASK 0x4
101 #define ENA_REGS_DEV_CTL_IO_RESUME_MASK 0x8
103 #define ENA_REGS_DEV_CTL_RESET_REASON_MASK 0xf0000000
106 #define ENA_REGS_DEV_STS_READY_MASK 0x1
108 #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x2
110 #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK 0x4
112 #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK 0x8
114 #define ENA_REGS_DEV_STS_RESET_FINISHED_MASK 0x10
116 #define ENA_REGS_DEV_STS_FATAL_ERROR_MASK 0x20
118 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK 0x40
120 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK 0x80
123 #define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK 0xffff
125 #define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK 0xffff0000
128 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK 0xffff
130 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK 0xffff0000