Lines Matching +full:0 +full:x650
12 #define USE_TX_COAL_NOW 0
34 u32 HostCtrl; /* 0x40 */
39 u32 MiscCfg; /* 0x50 */
45 u32 pad3[2]; /* 0x60 */
50 u32 pad4[12]; /* 0x70 */
52 u32 DmaWriteState; /* 0xa0 */
54 u32 DmaReadState; /* 0xb0 */
60 u32 pad7[8]; /* 0x120 */
62 u32 CpuCtrl; /* 0x140 */
67 u32 SramAddr; /* 0x154 */
72 u32 MacRxState; /* 0x220 */
76 u32 CpuBCtrl; /* 0x240 */
81 u32 SramBAddr; /* 0x254 */
86 u32 pad13[32]; /* 0x400 */
89 u32 Mb0Hi; /* 0x500 */
124 u32 MacAddrHi; /* 0x600 */
128 u32 MultiCastHi; /* 0x610 */
132 u32 DmaWriteCfg; /* 0x620 */
136 u32 TuneRxCoalTicks;/* 0x630 */
140 u32 TuneMaxRxDesc; /* 0x640 */
144 u32 TracePtr; /* 0x650 */
148 u32 IfMtu; /* 0x660 */
152 u32 pad16[4]; /* 0x670 */
153 u32 RxRetCsm; /* 0x680 */
157 u32 CmdRng[64]; /* 0x700 */
158 u32 Window[0x200];
168 #define ACE_WINDOW_SIZE 0x800
173 #define ACE_TRACE_SIZE 0x8000
179 #define IN_INT 0x01
180 #define CLR_INT 0x02
181 #define HW_RESET 0x08
182 #define BYTE_SWAP 0x10
183 #define WORD_SWAP 0x20
184 #define MASK_INTS 0x40
190 #define EEPROM_DATA_IN 0x800000
191 #define EEPROM_DATA_OUT 0x400000
192 #define EEPROM_WRITE_ENABLE 0x200000
193 #define EEPROM_CLK_OUT 0x100000
195 #define EEPROM_BASE 0xa0000000
197 #define EEPROM_WRITE_SELECT 0xa0
198 #define EEPROM_READ_SELECT 0xa1
200 #define SRAM_BANK_512K 0x200
214 #define SYNC_SRAM_TIMING 0x100000
221 #define CPU_RESET 0x01
222 #define CPU_TRACE 0x02
223 #define CPU_PROM_FAILED 0x10
224 #define CPU_HALT 0x00010000
225 #define CPU_HALTED 0xffff0000
232 #define DMA_READ_MAX_4 0x04
233 #define DMA_READ_MAX_16 0x08
234 #define DMA_READ_MAX_32 0x0c
235 #define DMA_READ_MAX_64 0x10
236 #define DMA_READ_MAX_128 0x14
237 #define DMA_READ_MAX_256 0x18
238 #define DMA_READ_MAX_1K 0x1c
239 #define DMA_WRITE_MAX_4 0x20
240 #define DMA_WRITE_MAX_16 0x40
241 #define DMA_WRITE_MAX_32 0x60
242 #define DMA_WRITE_MAX_64 0x80
243 #define DMA_WRITE_MAX_128 0xa0
244 #define DMA_WRITE_MAX_256 0xc0
245 #define DMA_WRITE_MAX_1K 0xe0
246 #define DMA_READ_WRITE_MASK 0xfc
247 #define MEM_READ_MULTIPLE 0x00020000
248 #define PCI_66MHZ 0x00080000
249 #define PCI_32BIT 0x00100000
250 #define DMA_WRITE_ALL_ALIGN 0x00800000
251 #define READ_CMD_MEM 0x06000000
252 #define WRITE_CMD_MEM 0x70000000
259 #define ACE_BYTE_SWAP_BD 0x02
260 #define ACE_WORD_SWAP_BD 0x04 /* not actually used */
261 #define ACE_WARN 0x08
262 #define ACE_BYTE_SWAP_DMA 0x10
263 #define ACE_NO_JUMBO_FRAG 0x200
264 #define ACE_FATAL 0x40000000
271 #define DMA_THRESH_1W 0x10
272 #define DMA_THRESH_2W 0x20
273 #define DMA_THRESH_4W 0x40
274 #define DMA_THRESH_8W 0x80
275 #define DMA_THRESH_16W 0x100
276 #define DMA_THRESH_32W 0x0 /* not described in doc, but exists. */
290 #define LNK_PREF 0x00008000
291 #define LNK_10MB 0x00010000
292 #define LNK_100MB 0x00020000
293 #define LNK_1000MB 0x00040000
294 #define LNK_FULL_DUPLEX 0x00080000
295 #define LNK_HALF_DUPLEX 0x00100000
296 #define LNK_TX_FLOW_CTL_Y 0x00200000
297 #define LNK_NEG_ADVANCED 0x00400000
298 #define LNK_RX_FLOW_CTL_Y 0x00800000
299 #define LNK_NIC 0x01000000
300 #define LNK_JAM 0x02000000
301 #define LNK_JUMBO 0x04000000
302 #define LNK_ALTEON 0x08000000
303 #define LNK_NEG_FCTL 0x10000000
304 #define LNK_NEGOTIATE 0x20000000
305 #define LNK_ENABLE 0x40000000
306 #define LNK_UP 0x80000000
334 #define E_FW_RUNNING 0x01
335 #define E_STATS_UPDATED 0x04
337 #define E_STATS_UPDATE 0x04
339 #define E_LNK_STATE 0x06
340 #define E_C_LINK_UP 0x01
341 #define E_C_LINK_DOWN 0x02
342 #define E_C_LINK_10_100 0x03
344 #define E_ERROR 0x07
345 #define E_C_ERR_INVAL_CMD 0x01
346 #define E_C_ERR_UNIMP_CMD 0x02
347 #define E_C_ERR_BAD_CFG 0x03
349 #define E_MCAST_LIST 0x08
350 #define E_C_MCAST_ADDR_ADD 0x01
351 #define E_C_MCAST_ADDR_DEL 0x02
353 #define E_RESET_JUMBO_RNG 0x09
375 #define C_HOST_STATE 0x01
376 #define C_C_STACK_UP 0x01
377 #define C_C_STACK_DOWN 0x02
379 #define C_FDR_FILTERING 0x02
380 #define C_C_FDR_FILT_ENABLE 0x01
381 #define C_C_FDR_FILT_DISABLE 0x02
383 #define C_SET_RX_PRD_IDX 0x03
384 #define C_UPDATE_STATS 0x04
385 #define C_RESET_JUMBO_RNG 0x05
386 #define C_ADD_MULTICAST_ADDR 0x08
387 #define C_DEL_MULTICAST_ADDR 0x09
389 #define C_SET_PROMISC_MODE 0x0a
390 #define C_C_PROMISC_ENABLE 0x01
391 #define C_C_PROMISC_DISABLE 0x02
393 #define C_LNK_NEGOTIATION 0x0b
394 #define C_C_NEGOTIATE_BOTH 0x00
395 #define C_C_NEGOTIATE_GIG 0x01
396 #define C_C_NEGOTIATE_10_100 0x02
398 #define C_SET_MAC_ADDR 0x0c
399 #define C_CLEAR_PROFILE 0x0d
401 #define C_SET_MULTICAST_MODE 0x0e
402 #define C_C_MCAST_ENABLE 0x01
403 #define C_C_MCAST_DISABLE 0x02
405 #define C_CLEAR_STATS 0x0f
406 #define C_SET_RX_JUMBO_PRD_IDX 0x10
407 #define C_REFRESH_STATS 0x11
413 #define BD_FLG_TCP_UDP_SUM 0x01
414 #define BD_FLG_IP_SUM 0x02
415 #define BD_FLG_END 0x04
416 #define BD_FLG_MORE 0x08
417 #define BD_FLG_JUMBO 0x10
418 #define BD_FLG_UCAST 0x20
419 #define BD_FLG_MCAST 0x40
420 #define BD_FLG_BCAST 0x60
421 #define BD_FLG_TYP_MASK 0x60
422 #define BD_FLG_IP_FRAG 0x80
423 #define BD_FLG_IP_FRAG_END 0x100
424 #define BD_FLG_VLAN_TAG 0x200
425 #define BD_FLG_FRAME_ERROR 0x400
426 #define BD_FLG_COAL_NOW 0x800
427 #define BD_FLG_MINI 0x1000
433 #define RCB_FLG_TCP_UDP_SUM 0x01
434 #define RCB_FLG_IP_SUM 0x02
435 #define RCB_FLG_NO_PSEUDO_HDR 0x08
436 #define RCB_FLG_VLAN_ASSIST 0x10
437 #define RCB_FLG_COAL_INT_ONLY 0x20
438 #define RCB_FLG_TX_HOST_RING 0x40
439 #define RCB_FLG_IEEE_SNAP_SUM 0x80
440 #define RCB_FLG_EXT_RX_BD 0x100
441 #define RCB_FLG_RNG_DISABLE 0x200
450 #define TX_RING_BASE 0x3800
455 #if 0
715 aa->addrlo = baddr & 0xffffffff; in set_aceaddr()
760 writel(0, ®s->MaskInt); in ace_unmask_irq()