ethernet/agere/et131x.h

52 /* LBCIF Register Groups (addressed via 32-bit offsets) */
56 /* LBCIF Registers (addressed via 8-bit offsets) */
78 /* START OF GLOBAL REGISTER ADDRESS MAP */
81  * Tx queue start address reg in global address map at address 0x0000
82  * tx queue end address reg in global address map at address 0x0004
83  * rx queue start address reg in global address map at address 0x0008
84  * rx queue end address reg in global address map at address 0x000C
87 /* structure for power management control status reg in global address map
88  * located at address 0x0010
103 /* Interrupt status reg at address 0x0018
120 /* Interrupt mask register at address 0x001C
121  * Interrupt alias clear mask reg at address 0x0020
122  * Interrupt status alias reg at address 0x0024
127 /* Software reset reg at address 0x0028
139 /* SLV Timer reg at address 0x002C (low 24 bits)
142 /* MSI Configuration reg at address 0x0030
147 /* Loopback reg located at address 0x0034
152 /* GLOBAL Module of JAGCore Address Mapping
153  * Located at address 0x0000
173 /* START OF TXDMA REGISTER ADDRESS MAP */
174 /* txdma control status reg at address 0x1000
183 /* structure for txdma packet ring base address hi reg in txdma address map
184  * located at address 0x1004
188 /* structure for txdma packet ring base address low reg in txdma address map
189  * located at address 0x1008
193 /* structure for txdma packet ring number of descriptor reg in txdma address
194  * map.  Located at address 0x100C
196  * 31-10: unused
197  * 9-0: pr ndes
211  * txdma tx queue write address reg in txdma address map at 0x1010
212  * txdma tx queue write address external reg in txdma address map at 0x1014
213  * txdma tx queue read address reg in txdma address map at 0x1018
216  * txdma status writeback address hi reg in txdma address map at0x101C
217  * txdma status writeback address lo reg in txdma address map at 0x1020
220  * txdma service request reg in txdma address map at 0x1024
221  * structure for txdma service complete reg in txdma address map at 0x1028
224  * txdma tx descriptor cache read index reg in txdma address map at 0x102C
225  * txdma tx descriptor cache write index reg in txdma address map at 0x1030
227  * txdma error reg in txdma address map at address 0x1034
236 /* Tx DMA Module of JAGCore Address Mapping
237  * Located at address 0x1000
268 /* END OF TXDMA REGISTER ADDRESS MAP */
270 /* START OF RXDMA REGISTER ADDRESS MAP */
271 /* structure for control status reg in rxdma address map
272  * Located at address 0x2000
276  * 1-3: tc
281  * 8-9: fbr0_size
283  * 11-12: fbr1_size
289  * 18-31: unused
300 /* structure for dma writeback lo reg in rxdma address map
301  * located at address 0x2004
305 /* structure for dma writeback hi reg in rxdma address map
306  * located at address 0x2008
310 /* structure for number of packets done reg in rxdma address map
311  * located at address 0x200C
313  * 31-8: unused
314  * 7-0: num done
317 /* structure for max packet time reg in rxdma address map
318  * located at address 0x2010
320  * 31-18: unused
321  * 17-0: time done
324 /* structure for rx queue read address reg in rxdma address map
325  * located at address 0x2014
329 /* structure for rx queue read address external reg in rxdma address map
330  * located at address 0x2018
334 /* structure for rx queue write address reg in rxdma address map
335  * located at address 0x201C
339 /* structure for packet status ring base address lo reg in rxdma address map
340  * located at address 0x2020
344 /* structure for packet status ring base address hi reg in rxdma address map
345  * located at address 0x2024
349 /* structure for packet status ring number of descriptors reg in rxdma address
350  * map.  Located at address 0x2028
352  * 31-12: unused
353  * 11-0: psr ndes
357 /* structure for packet status ring available offset reg in rxdma address map
358  * located at address 0x202C
360  * 31-13: unused
362  * 11-0: psr avail
365 /* structure for packet status ring full offset reg in rxdma address map
366  * located at address 0x2030
368  * 31-13: unused
370  * 11-0: psr full
373 /* structure for packet status ring access index reg in rxdma address map
374  * located at address 0x2034
376  * 31-5: unused
377  * 4-0: psr_ai
380 /* structure for packet status ring minimum descriptors reg in rxdma address
381  * map.  Located at address 0x2038
383  * 31-12: unused
384  * 11-0: psr_min
387 /* structure for free buffer ring base lo address reg in rxdma address map
388  * located at address 0x203C
392 /* structure for free buffer ring base hi address reg in rxdma address map
393  * located at address 0x2040
397 /* structure for free buffer ring number of descriptors reg in rxdma address
398  * map.  Located at address 0x2044
400  * 31-10: unused
401  * 9-0: fbr ndesc
404 /* structure for free buffer ring 0 available offset reg in rxdma address map
405  * located at address 0x2048
409 /* structure for free buffer ring 0 full offset reg in rxdma address map
410  * located at address 0x204C
414 /* structure for free buffer cache 0 full offset reg in rxdma address map
415  * located at address 0x2050
417  * 31-5: unused
418  * 4-0: fbc rdi
421 /* structure for free buffer ring 0 minimum descriptor reg in rxdma address map
422  * located at address 0x2054
424  * 31-10: unused
425  * 9-0: fbr min
428 /* structure for free buffer ring 1 base address lo reg in rxdma address map
429  * located at address 0x2058 - 0x205C
433 /* structure for free buffer ring 1 number of descriptors reg in rxdma address
434  * map.  Located at address 0x2060
438 /* structure for free buffer ring 1 available offset reg in rxdma address map
439  * located at address 0x2064
443 /* structure for free buffer ring 1 full offset reg in rxdma address map
444  * located at address 0x2068
448 /* structure for free buffer cache 1 read index reg in rxdma address map
449  * located at address 0x206C
453 /* structure for free buffer ring 1 minimum descriptor reg in rxdma address map
454  * located at address 0x2070
458 /* Rx DMA Module of JAGCore Address Mapping
459  * Located at address 0x2000
493 /* END OF RXDMA REGISTER ADDRESS MAP */
495 /* START OF TXMAC REGISTER ADDRESS MAP */
496 /* structure for control reg in txmac address map
497  * located at address 0x3000
500  * 31-8: unused
513 /* structure for shadow pointer reg in txmac address map
514  * located at address 0x3004
515  * 31-27: reserved
516  * 26-16: txq rd ptr
517  * 15-11: reserved
518  * 10-0: txq wr ptr
521 /* structure for error count reg in txmac address map
522  * located at address 0x3008
524  * 31-12: unused
525  * 11-8: reserved
526  * 7-4: txq_underrun
527  * 3-0: fifo_underrun
530 /* structure for max fill reg in txmac address map
531  * located at address 0x300C
532  * 31-12: unused
533  * 11-0: max fill
536 /* structure for cf parameter reg in txmac address map
537  * located at address 0x3010
538  * 31-16: cfep
539  * 15-0: cfpt
542 /* structure for tx test reg in txmac address map
543  * located at address 0x3014
544  * 31-17: unused
547  * 14-11: unused
548  * 10-0: txq test pointer
551 /* structure for error reg in txmac address map
552  * located at address 0x3018
554  * 31-9: unused
556  * 7-6: unused
565 /* structure for error interrupt reg in txmac address map
566  * located at address 0x301C
568  * 31-9: unused
570  * 7-6: unused
579 /* structure for error interrupt reg in txmac address map
580  * located at address 0x3020
582  * 31-2: unused
587 /* Tx MAC Module of JAGCore Address Mapping
601 /* END OF TXMAC REGISTER ADDRESS MAP */
603 /* START OF RXMAC REGISTER ADDRESS MAP */
605 /* structure for rxmac control reg in rxmac address map
606  * located at address 0x4000
608  * 31-7: reserved
620 /* structure for Wake On Lan Control and CRC 0 reg in rxmac address map
621  * located at address 0x4004
622  * 31-16: crc
623  * 15-12: reserved
631  * 4-0: valid_crc 4-0
634 /* structure for CRC 1 and CRC 2 reg in rxmac address map
635  * located at address 0x4008
637  * 31-16: crc2
638  * 15-0: crc1
641 /* structure for CRC 3 and CRC 4 reg in rxmac address map
642  * located at address 0x400C
644  * 31-16: crc4
645  * 15-0: crc3
648 /* structure for Wake On Lan Source Address Lo reg in rxmac address map
649  * located at address 0x4010
651  * 31-24: sa3
652  * 23-16: sa4
653  * 15-8: sa5
654  * 7-0: sa6
660 /* structure for Wake On Lan Source Address Hi reg in rxmac address map
661  * located at address 0x4014
663  * 31-16: reserved
664  * 15-8: sa1
665  * 7-0: sa2
669 /* structure for Wake On Lan mask reg in rxmac address map
670  * located at address 0x4018 - 0x4064
674 /* structure for Unicast Packet Filter Address 1 reg in rxmac address map
675  * located at address 0x4068
677  * 31-24: addr1_3
678  * 23-16: addr1_4
679  * 15-8: addr1_5
680  * 7-0: addr1_6
686 /* structure for Unicast Packet Filter Address 2 reg in rxmac address map
687  * located at address 0x406C
689  * 31-24: addr2_3
690  * 23-16: addr2_4
691  * 15-8: addr2_5
692  * 7-0: addr2_6
698 /* structure for Unicast Packet Filter Address 1 & 2 reg in rxmac address map
699  * located at address 0x4070
701  * 31-24: addr2_1
702  * 23-16: addr2_2
703  * 15-8: addr1_1
704  * 7-0: addr1_2
710 /* structure for Multicast Hash reg in rxmac address map
711  * located at address 0x4074 - 0x4080
715 /* structure for Packet Filter Control reg in rxmac address map
716  * located at address 0x4084
718  * 31-23: unused
719  * 22-16: min_pkt_size
720  * 15-4: unused
733  * address map.  Located at address 0x4088
735  * 31-10: reserved
736  * 9-2: max_size
744 /* structure for Memory Controller Interface Water Mark reg in rxmac address
745  * map.  Located at address 0x408C
747  * 31-26: unused
748  * 25-16: mark_hi
749  * 15-10: unused
750  * 9-0: mark_lo
753 /* structure for Rx Queue Dialog reg in rxmac address map.
754  * located at address 0x4090
756  * 31-26: reserved
757  * 25-16: rd_ptr
758  * 15-10: reserved
759  * 9-0: wr_ptr
762 /* structure for space available reg in rxmac address map.
763  * located at address 0x4094
765  * 31-17: reserved
767  * 15-10: reserved
768  * 9-0: space_avail
771 /* structure for management interface reg in rxmac address map.
772  * located at address 0x4098
774  * 31-18: reserved
776  * 16-0: drop_pkt_mask
779 /* structure for Error reg in rxmac address map.
780  * located at address 0x409C
782  * 31-4: unused
789 /* Rx MAC Module of JAGCore Address Mapping
835 /* END OF RXMAC REGISTER ADDRESS MAP */
837 /* START OF MAC REGISTER ADDRESS MAP */
838 /* structure for configuration #1 reg in mac address map.
839  * located at address 0x5000
843  * 29-20: reserved
848  * 15-9: reserved
850  * 7-6: reserved
871 /* structure for configuration #2 reg in mac address map.
872  * located at address 0x5004
873  * 31-16: reserved
874  * 15-12: preamble
875  * 11-10: reserved
876  * 9-8: if mode
877  * 7-6: reserved
895 /* structure for Interpacket gap reg in mac address map.
896  * located at address 0x5008
899  * 30-24: non B2B ipg 1
901  * 22-16: non B2B ipg 2
902  * 15-8: Min ifg enforce
903  * 7-0: B2B ipg
905  * structure for half duplex reg in mac address map.
906  * located at address 0x500C
907  * 31-24: reserved
908  * 23-20: Alt BEB trunc
913  * 15-12: re-xmit max
914  * 11-10: reserved
915  * 9-0: collision window
918 /* structure for Maximum Frame Length reg in mac address map.
919  * located at address 0x5010: bits 0-15 hold the length.
922 /* structure for Reserve 1 reg in mac address map.
923  * located at address 0x5014 - 0x5018
927 /* structure for Test reg in mac address map.
928  * located at address 0x501C
929  * test: bits 0-2, rest unused
932 /* structure for MII Management Configuration reg in mac address map.
933  * located at address 0x5020
936  * 30-6: unused
940  * 2-0: mgmt clock reset
944 /* structure for MII Management Command reg in mac address map.
945  * located at address 0x5024
950 /* structure for MII Management Address reg in mac address map.
951  * located at address 0x5028
952  * 31-13: reserved
953  * 12-8: phy addr
954  * 7-5: reserved
955  * 4-0: register
959 /* structure for MII Management Control reg in mac address map.
960  * located at address 0x502C
961  * 31-16: reserved
962  * 15-0: phy control
965 /* structure for MII Management Status reg in mac address map.
966  * located at address 0x5030
967  * 31-16: reserved
968  * 15-0: phy control
972 /* structure for MII Management Indicators reg in mac address map.
973  * located at address 0x5034
974  * 31-3: reserved
982 /* structure for Interface Control reg in mac address map.
983  * located at address 0x5038
986  * 30-28: reserved
992  * 22-17: reserved
995  * 14-11: reserved
1000  * 6-1: reserved
1006 /* structure for Interface Status reg in mac address map.
1007  * located at address 0x503C
1009  * 31-10: reserved
1022 /* structure for Mac Station Address, Part 1 reg in mac address map.
1023  * located at address 0x5040
1025  * 31-24: Octet6
1026  * 23-16: Octet5
1027  * 15-8: Octet4
1028  * 7-0: Octet3
1034 /* structure for Mac Station Address, Part 2 reg in mac address map.
1035  * located at address 0x5044
1037  * 31-24: Octet2
1038  * 23-16: Octet1
1039  * 15-0: reserved
1044 /* MAC Module of JAGCore Address Mapping
1067 /* END OF MAC REGISTER ADDRESS MAP */
1069 /* START OF MAC STAT REGISTER ADDRESS MAP */
1070 /* structure for Carry Register One and it's Mask Register reg located in mac
1071  * stat address map address 0x6130 and 0x6138.
1080  * 24-17: unused
1100 /* structure for Carry Register Two Mask Register reg in mac stat address map.
1101  * located at address 0x613C
1103  * 31-20: unused
1126 /* MAC STATS Module of JAGCore Address Mapping
1129 	u32 pad[32];			/*  0x6000 - 607C */
1182 /* END OF MAC STAT REGISTER ADDRESS MAP */
1184 /* START OF MMC REGISTER ADDRESS MAP */
1185 /* Main Memory Controller Control reg in mmc address map.
1186  * located at address 0x7000
1196 /* Main Memory Controller Host Memory Access Address reg in mmc
1197  * address map.  Located at address 0x7004. Top 16 bits hold the address bits
1204  * address map.  Located at address 0x7008 - 0x7014
1208 /* Memory Control Module of JAGCore Address Mapping
1219 /* END OF MMC REGISTER ADDRESS MAP */
1221 /* JAGCore Address Mapping
1225 	/* unused section of global address map */
1226 	u8 unused_global[4096 - sizeof(struct global_regs)];
1228 	/* unused section of txdma address map */
1229 	u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
1231 	/* unused section of rxdma address map */
1232 	u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
1234 	/* unused section of txmac address map */
1235 	u8 unused_txmac[4096 - sizeof(struct txmac_regs)];
1237 	/* unused section of rxmac address map */
1238 	u8 unused_rxmac[4096 - sizeof(struct rxmac_regs)];
1239 	struct mac_regs mac;  member
1240 	/* unused section of mac address map */
1241 	u8 unused_mac[4096 - sizeof(struct mac_regs)];
1243 	/* unused section of mac stat address map */
1244 	u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)];
1246 	/* unused section of mmc address map */
1247 	u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
1248 	/* unused section of address map */
1250 	u8 unused_exp_rom[4096];	/* MGS-size TBD */
1251 	u8 unused__[524288];	/* unused section of address map */
1254 /* Defines for generic MII registers 0x00 -> 0x0F can be found in
1279 /* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
1288  *	9-0:	reserved
1294  *	15-11:	reserved
1295  *	10-4:	mi_error_count
1305  *	13-12:	tx_fifo_depth
1306  *	11-10:	speed_downshift
1314  *	2-0:	mac_if_mode
1327  *	12-11:	downshift_attempts
1328  *	10-6:	reserved
1338  *	15-10:	reserved
1352  *	15-10:	reserved
1367  *	14-13:	autoneg_fault
1371  *	9-8:	speed_status
1389  *	15-14:	reserved
1390  *	13-12:	led_dup_indicate
1391  *	11-10:	led_10baseT
1392  *	9-8:	led_collision
1393  *	7-4:	reserved
1394  *	3-2:	pulse_dur
1400  *	15-12:	led_link
1401  *	11-8:	led_tx_rx
1402  *	7-4:	led_100BaseTX
1403  *	3-0:	led_1000BaseT
1432 /* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */