Lines Matching +full:owl +full:- +full:emac
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Actions Semi Owl SoCs Ethernet MAC driver
11 #include <linux/dma-mapping.h>
19 #include "owl-emac.h"
27 return readl(priv->base + reg); in owl_emac_reg_read()
32 writel(data, priv->base + reg); in owl_emac_reg_write()
63 return priv->netdev->dev.parent; in owl_emac_get_dev()
129 return dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); in owl_emac_dma_map_tx()
142 return CIRC_SPACE(ring->head, ring->tail, ring->size); in owl_emac_ring_num_unused()
148 return (cur + 1) & (ring->size - 1); in owl_emac_ring_get_next()
153 ring->head = owl_emac_ring_get_next(ring, ring->head); in owl_emac_ring_push_head()
158 ring->tail = owl_emac_ring_get_next(ring, ring->tail); in owl_emac_ring_pop_tail()
172 offset = ((uintptr_t)skb->data) & (OWL_EMAC_SKB_ALIGN - 1); in owl_emac_alloc_skb()
174 skb_reserve(skb, OWL_EMAC_SKB_ALIGN - offset); in owl_emac_alloc_skb()
181 struct owl_emac_ring *ring = &priv->rx_ring; in owl_emac_ring_prepare_rx()
183 struct net_device *netdev = priv->netdev; in owl_emac_ring_prepare_rx()
189 for (i = 0; i < ring->size; i++) { in owl_emac_ring_prepare_rx()
192 return -ENOMEM; in owl_emac_ring_prepare_rx()
197 return -ENOMEM; in owl_emac_ring_prepare_rx()
200 desc = &ring->descs[i]; in owl_emac_ring_prepare_rx()
201 desc->status = OWL_EMAC_BIT_RDES0_OWN; in owl_emac_ring_prepare_rx()
202 desc->control = skb_tailroom(skb) & OWL_EMAC_MSK_RDES1_RBS1; in owl_emac_ring_prepare_rx()
203 desc->buf_addr = dma_addr; in owl_emac_ring_prepare_rx()
204 desc->reserved = 0; in owl_emac_ring_prepare_rx()
206 ring->skbs[i] = skb; in owl_emac_ring_prepare_rx()
207 ring->skbs_dma[i] = dma_addr; in owl_emac_ring_prepare_rx()
210 desc->control |= OWL_EMAC_BIT_RDES1_RER; in owl_emac_ring_prepare_rx()
212 ring->head = 0; in owl_emac_ring_prepare_rx()
213 ring->tail = 0; in owl_emac_ring_prepare_rx()
220 struct owl_emac_ring *ring = &priv->tx_ring; in owl_emac_ring_prepare_tx()
224 for (i = 0; i < ring->size; i++) { in owl_emac_ring_prepare_tx()
225 desc = &ring->descs[i]; in owl_emac_ring_prepare_tx()
227 desc->status = 0; in owl_emac_ring_prepare_tx()
228 desc->control = OWL_EMAC_BIT_TDES1_IC; in owl_emac_ring_prepare_tx()
229 desc->buf_addr = 0; in owl_emac_ring_prepare_tx()
230 desc->reserved = 0; in owl_emac_ring_prepare_tx()
233 desc->control |= OWL_EMAC_BIT_TDES1_TER; in owl_emac_ring_prepare_tx()
235 memset(ring->skbs_dma, 0, sizeof(dma_addr_t) * ring->size); in owl_emac_ring_prepare_tx()
237 ring->head = 0; in owl_emac_ring_prepare_tx()
238 ring->tail = 0; in owl_emac_ring_prepare_tx()
243 struct owl_emac_ring *ring = &priv->rx_ring; in owl_emac_ring_unprepare_rx()
246 for (i = 0; i < ring->size; i++) { in owl_emac_ring_unprepare_rx()
247 ring->descs[i].status = 0; in owl_emac_ring_unprepare_rx()
249 if (!ring->skbs_dma[i]) in owl_emac_ring_unprepare_rx()
252 owl_emac_dma_unmap_rx(priv, ring->skbs[i], ring->skbs_dma[i]); in owl_emac_ring_unprepare_rx()
253 ring->skbs_dma[i] = 0; in owl_emac_ring_unprepare_rx()
255 dev_kfree_skb(ring->skbs[i]); in owl_emac_ring_unprepare_rx()
256 ring->skbs[i] = NULL; in owl_emac_ring_unprepare_rx()
262 struct owl_emac_ring *ring = &priv->tx_ring; in owl_emac_ring_unprepare_tx()
265 for (i = 0; i < ring->size; i++) { in owl_emac_ring_unprepare_tx()
266 ring->descs[i].status = 0; in owl_emac_ring_unprepare_tx()
268 if (!ring->skbs_dma[i]) in owl_emac_ring_unprepare_tx()
271 owl_emac_dma_unmap_tx(priv, ring->skbs[i], ring->skbs_dma[i]); in owl_emac_ring_unprepare_tx()
272 ring->skbs_dma[i] = 0; in owl_emac_ring_unprepare_tx()
274 dev_kfree_skb(ring->skbs[i]); in owl_emac_ring_unprepare_tx()
275 ring->skbs[i] = NULL; in owl_emac_ring_unprepare_tx()
282 ring->descs = dmam_alloc_coherent(dev, in owl_emac_ring_alloc()
284 &ring->descs_dma, GFP_KERNEL); in owl_emac_ring_alloc()
285 if (!ring->descs) in owl_emac_ring_alloc()
286 return -ENOMEM; in owl_emac_ring_alloc()
288 ring->skbs = devm_kcalloc(dev, size, sizeof(struct sk_buff *), in owl_emac_ring_alloc()
290 if (!ring->skbs) in owl_emac_ring_alloc()
291 return -ENOMEM; in owl_emac_ring_alloc()
293 ring->skbs_dma = devm_kcalloc(dev, size, sizeof(dma_addr_t), in owl_emac_ring_alloc()
295 if (!ring->skbs_dma) in owl_emac_ring_alloc()
296 return -ENOMEM; in owl_emac_ring_alloc()
298 ring->size = size; in owl_emac_ring_alloc()
345 const u8 *mac_addr = netdev->dev_addr; in owl_emac_set_hw_mac_addr()
360 if (priv->pause) { in owl_emac_update_link_state()
371 val = (priv->speed == SPEED_100) ? OWL_EMAC_VAL_MAC_CSR6_SPEED_100M : in owl_emac_update_link_state()
375 if (priv->duplex == DUPLEX_FULL) in owl_emac_update_link_state()
378 spin_lock_bh(&priv->lock); in owl_emac_update_link_state()
391 spin_unlock_bh(&priv->lock); in owl_emac_update_link_state()
397 struct phy_device *phydev = netdev->phydev; in owl_emac_adjust_link()
400 if (phydev->link) { in owl_emac_adjust_link()
401 if (!priv->link) { in owl_emac_adjust_link()
402 priv->link = phydev->link; in owl_emac_adjust_link()
406 if (priv->speed != phydev->speed) { in owl_emac_adjust_link()
407 priv->speed = phydev->speed; in owl_emac_adjust_link()
411 if (priv->duplex != phydev->duplex) { in owl_emac_adjust_link()
412 priv->duplex = phydev->duplex; in owl_emac_adjust_link()
416 if (priv->pause != phydev->pause) { in owl_emac_adjust_link()
417 priv->pause = phydev->pause; in owl_emac_adjust_link()
421 if (priv->link) { in owl_emac_adjust_link()
422 priv->link = phydev->link; in owl_emac_adjust_link()
428 if (phydev->link) in owl_emac_adjust_link()
443 napi_schedule(&priv->napi); in owl_emac_handle_irq()
465 const u8 *mac_addr = priv->netdev->dev_addr; in owl_emac_setup_frame_prepare()
471 frame = skb->data; in owl_emac_setup_frame_prepare()
472 memset(frame, 0, skb->len); in owl_emac_setup_frame_prepare()
478 WARN_ON(priv->mcaddr_list.count >= OWL_EMAC_MAX_MULTICAST_ADDRS); in owl_emac_setup_frame_prepare()
479 for (i = 0; i < priv->mcaddr_list.count; i++) { in owl_emac_setup_frame_prepare()
480 mac_addr = priv->mcaddr_list.addrs[i]; in owl_emac_setup_frame_prepare()
492 struct owl_emac_ring *ring = &priv->tx_ring; in owl_emac_setup_frame_xmit()
493 struct net_device *netdev = priv->netdev; in owl_emac_setup_frame_xmit()
503 return -ENOMEM; in owl_emac_setup_frame_xmit()
509 ret = -ENOMEM; in owl_emac_setup_frame_xmit()
513 spin_lock_bh(&priv->lock); in owl_emac_setup_frame_xmit()
515 tx_head = ring->head; in owl_emac_setup_frame_xmit()
516 desc = &ring->descs[tx_head]; in owl_emac_setup_frame_xmit()
518 status = READ_ONCE(desc->status); in owl_emac_setup_frame_xmit()
519 control = READ_ONCE(desc->control); in owl_emac_setup_frame_xmit()
524 spin_unlock_bh(&priv->lock); in owl_emac_setup_frame_xmit()
526 ret = -EBUSY; in owl_emac_setup_frame_xmit()
530 ring->skbs[tx_head] = skb; in owl_emac_setup_frame_xmit()
531 ring->skbs_dma[tx_head] = dma_addr; in owl_emac_setup_frame_xmit()
535 control |= OWL_EMAC_MSK_TDES1_TBS1 & skb->len; in owl_emac_setup_frame_xmit()
537 WRITE_ONCE(desc->control, control); in owl_emac_setup_frame_xmit()
538 WRITE_ONCE(desc->buf_addr, dma_addr); in owl_emac_setup_frame_xmit()
540 WRITE_ONCE(desc->status, OWL_EMAC_BIT_TDES0_OWN); in owl_emac_setup_frame_xmit()
556 spin_unlock_bh(&priv->lock); in owl_emac_setup_frame_xmit()
570 struct owl_emac_ring *ring = &priv->tx_ring; in owl_emac_ndo_start_xmit()
578 dev_err_ratelimited(&netdev->dev, "TX DMA mapping failed\n"); in owl_emac_ndo_start_xmit()
580 netdev->stats.tx_dropped++; in owl_emac_ndo_start_xmit()
584 spin_lock_bh(&priv->lock); in owl_emac_ndo_start_xmit()
586 tx_head = ring->head; in owl_emac_ndo_start_xmit()
587 desc = &ring->descs[tx_head]; in owl_emac_ndo_start_xmit()
589 status = READ_ONCE(desc->status); in owl_emac_ndo_start_xmit()
590 control = READ_ONCE(desc->control); in owl_emac_ndo_start_xmit()
596 spin_unlock_bh(&priv->lock); in owl_emac_ndo_start_xmit()
598 dev_dbg_ratelimited(&netdev->dev, "TX buffer full, status=0x%08x\n", in owl_emac_ndo_start_xmit()
601 netdev->stats.tx_dropped++; in owl_emac_ndo_start_xmit()
605 ring->skbs[tx_head] = skb; in owl_emac_ndo_start_xmit()
606 ring->skbs_dma[tx_head] = dma_addr; in owl_emac_ndo_start_xmit()
610 control |= OWL_EMAC_MSK_TDES1_TBS1 & skb->len; in owl_emac_ndo_start_xmit()
612 WRITE_ONCE(desc->control, control); in owl_emac_ndo_start_xmit()
613 WRITE_ONCE(desc->buf_addr, dma_addr); in owl_emac_ndo_start_xmit()
615 WRITE_ONCE(desc->status, OWL_EMAC_BIT_TDES0_OWN); in owl_emac_ndo_start_xmit()
626 spin_unlock_bh(&priv->lock); in owl_emac_ndo_start_xmit()
633 struct owl_emac_ring *ring = &priv->tx_ring; in owl_emac_tx_complete_tail()
634 struct net_device *netdev = priv->netdev; in owl_emac_tx_complete_tail()
640 tx_tail = ring->tail; in owl_emac_tx_complete_tail()
641 desc = &ring->descs[tx_tail]; in owl_emac_tx_complete_tail()
643 status = READ_ONCE(desc->status); in owl_emac_tx_complete_tail()
651 dev_dbg_ratelimited(&netdev->dev, in owl_emac_tx_complete_tail()
655 netdev->stats.tx_errors++; in owl_emac_tx_complete_tail()
658 netdev->stats.tx_fifo_errors++; in owl_emac_tx_complete_tail()
661 netdev->stats.tx_aborted_errors++; in owl_emac_tx_complete_tail()
664 netdev->stats.tx_window_errors++; in owl_emac_tx_complete_tail()
667 netdev->stats.tx_heartbeat_errors++; in owl_emac_tx_complete_tail()
670 netdev->stats.tx_carrier_errors++; in owl_emac_tx_complete_tail()
672 netdev->stats.tx_packets++; in owl_emac_tx_complete_tail()
673 netdev->stats.tx_bytes += ring->skbs[tx_tail]->len; in owl_emac_tx_complete_tail()
678 netdev->stats.collisions++; in owl_emac_tx_complete_tail()
680 skb = ring->skbs[tx_tail]; in owl_emac_tx_complete_tail()
681 owl_emac_dma_unmap_tx(priv, skb, ring->skbs_dma[tx_tail]); in owl_emac_tx_complete_tail()
684 ring->skbs[tx_tail] = NULL; in owl_emac_tx_complete_tail()
685 ring->skbs_dma[tx_tail] = 0; in owl_emac_tx_complete_tail()
697 struct owl_emac_ring *ring = &priv->tx_ring; in owl_emac_tx_complete()
698 struct net_device *netdev = priv->netdev; in owl_emac_tx_complete()
702 spin_lock(&priv->lock); in owl_emac_tx_complete()
704 while (ring->tail != ring->head) { in owl_emac_tx_complete()
722 tx_next = ring->tail; in owl_emac_tx_complete()
724 while ((tx_next = owl_emac_ring_get_next(ring, tx_next)) != ring->head) { in owl_emac_tx_complete()
725 status = READ_ONCE(ring->descs[tx_next].status); in owl_emac_tx_complete()
733 status = READ_ONCE(ring->descs[ring->tail].status); in owl_emac_tx_complete()
736 WRITE_ONCE(ring->descs[ring->tail].status, status); in owl_emac_tx_complete()
743 spin_unlock(&priv->lock); in owl_emac_tx_complete()
748 struct owl_emac_ring *ring = &priv->rx_ring; in owl_emac_rx_process()
750 struct net_device *netdev = priv->netdev; in owl_emac_rx_process()
759 spin_lock(&priv->lock); in owl_emac_rx_process()
761 rx_tail = ring->tail; in owl_emac_rx_process()
762 desc = &ring->descs[rx_tail]; in owl_emac_rx_process()
764 status = READ_ONCE(desc->status); in owl_emac_rx_process()
768 spin_unlock(&priv->lock); in owl_emac_rx_process()
772 curr_skb = ring->skbs[rx_tail]; in owl_emac_rx_process()
773 curr_dma = ring->skbs_dma[rx_tail]; in owl_emac_rx_process()
776 spin_unlock(&priv->lock); in owl_emac_rx_process()
782 dev_dbg_ratelimited(&netdev->dev, in owl_emac_rx_process()
787 netdev->stats.rx_over_errors++; in owl_emac_rx_process()
790 netdev->stats.rx_frame_errors++; in owl_emac_rx_process()
793 netdev->stats.rx_length_errors++; in owl_emac_rx_process()
796 netdev->stats.collisions++; in owl_emac_rx_process()
799 netdev->stats.rx_crc_errors++; in owl_emac_rx_process()
802 netdev->stats.rx_fifo_errors++; in owl_emac_rx_process()
809 netdev->stats.rx_length_errors++; in owl_emac_rx_process()
828 skb_put(curr_skb, len - ETH_FCS_LEN); in owl_emac_rx_process()
829 curr_skb->ip_summed = CHECKSUM_NONE; in owl_emac_rx_process()
830 curr_skb->protocol = eth_type_trans(curr_skb, netdev); in owl_emac_rx_process()
831 curr_skb->dev = netdev; in owl_emac_rx_process()
835 netdev->stats.rx_packets++; in owl_emac_rx_process()
836 netdev->stats.rx_bytes += len; in owl_emac_rx_process()
841 netdev->stats.rx_dropped++; in owl_emac_rx_process()
842 netdev->stats.rx_errors++; in owl_emac_rx_process()
848 spin_lock(&priv->lock); in owl_emac_rx_process()
850 ring->skbs[ring->head] = new_skb; in owl_emac_rx_process()
851 ring->skbs_dma[ring->head] = new_dma; in owl_emac_rx_process()
853 WRITE_ONCE(desc->buf_addr, new_dma); in owl_emac_rx_process()
855 WRITE_ONCE(desc->status, OWL_EMAC_BIT_RDES0_OWN); in owl_emac_rx_process()
859 spin_unlock(&priv->lock); in owl_emac_rx_process()
893 recv = owl_emac_rx_process(priv, budget - work_done); in owl_emac_poll()
911 recv = owl_emac_rx_process(priv, budget - work_done); in owl_emac_poll()
930 netdev_dbg(priv->netdev, "%s error status: 0x%08x\n", in owl_emac_poll()
934 schedule_work(&priv->mac_reset_task); in owl_emac_poll()
959 reset_control_assert(priv->reset); in owl_emac_core_hw_reset()
961 reset_control_deassert(priv->reset); in owl_emac_core_hw_reset()
972 ret = readl_poll_timeout(priv->base + OWL_EMAC_REG_MAC_CSR0, in owl_emac_core_sw_reset()
979 if (priv->phy_mode == PHY_INTERFACE_MODE_RMII) { in owl_emac_core_sw_reset()
1010 (u32)(priv->rx_ring.descs_dma)); in owl_emac_core_sw_reset()
1012 (u32)(priv->tx_ring.descs_dma)); in owl_emac_core_sw_reset()
1023 priv->link = 0; in owl_emac_core_sw_reset()
1024 priv->speed = SPEED_UNKNOWN; in owl_emac_core_sw_reset()
1025 priv->duplex = DUPLEX_UNKNOWN; in owl_emac_core_sw_reset()
1026 priv->pause = 0; in owl_emac_core_sw_reset()
1027 priv->mcaddr_list.count = 0; in owl_emac_core_sw_reset()
1056 napi_enable(&priv->napi); in owl_emac_enable()
1062 phy_start(netdev->phydev); in owl_emac_enable()
1083 napi_disable(&priv->napi); in owl_emac_disable()
1086 phy_stop(netdev->phydev); in owl_emac_disable()
1111 priv->mcaddr_list.count = 0; in owl_emac_set_multicast()
1116 if (!is_multicast_ether_addr(ha->addr)) in owl_emac_set_multicast()
1120 ether_addr_copy(priv->mcaddr_list.addrs[index++], ha->addr); in owl_emac_set_multicast()
1123 priv->mcaddr_list.count = index; in owl_emac_set_multicast()
1134 if (netdev->flags & IFF_PROMISC) { in owl_emac_ndo_set_rx_mode()
1136 } else if (netdev->flags & IFF_ALLMULTI) { in owl_emac_ndo_set_rx_mode()
1138 } else if (netdev->flags & IFF_MULTICAST) { in owl_emac_ndo_set_rx_mode()
1147 spin_lock_bh(&priv->lock); in owl_emac_ndo_set_rx_mode()
1160 spin_unlock_bh(&priv->lock); in owl_emac_ndo_set_rx_mode()
1170 if (!is_valid_ether_addr(skaddr->sa_data)) in owl_emac_ndo_set_mac_addr()
1171 return -EADDRNOTAVAIL; in owl_emac_ndo_set_mac_addr()
1174 return -EBUSY; in owl_emac_ndo_set_mac_addr()
1176 eth_hw_addr_set(netdev, skaddr->sa_data); in owl_emac_ndo_set_mac_addr()
1186 return -EINVAL; in owl_emac_ndo_eth_ioctl()
1188 return phy_mii_ioctl(netdev->phydev, req, cmd); in owl_emac_ndo_eth_ioctl()
1196 schedule_work(&priv->mac_reset_task); in owl_emac_ndo_tx_timeout()
1205 netdev_dbg(priv->netdev, "resetting MAC\n"); in owl_emac_reset_task()
1206 owl_emac_disable(priv->netdev, false); in owl_emac_reset_task()
1207 owl_emac_enable(priv->netdev, false); in owl_emac_reset_task()
1217 return &netdev->stats; in owl_emac_ndo_get_stats()
1235 strscpy(info->driver, OWL_EMAC_DRVNAME, sizeof(info->driver)); in owl_emac_ethtool_get_drvinfo()
1242 return priv->msg_enable; in owl_emac_ethtool_get_msglevel()
1249 priv->msg_enable = val; in owl_emac_ethtool_set_msglevel()
1266 return readl_poll_timeout(priv->base + OWL_EMAC_REG_MAC_CSR10, in owl_emac_mdio_wait()
1274 struct owl_emac_priv *priv = bus->priv; in owl_emac_mdio_read()
1302 struct owl_emac_priv *priv = bus->priv; in owl_emac_mdio_write()
1328 mdio_node = of_get_child_by_name(dev->of_node, "mdio"); in owl_emac_mdio_init()
1330 return -ENODEV; in owl_emac_mdio_init()
1333 ret = -ENODEV; in owl_emac_mdio_init()
1337 priv->mii = devm_mdiobus_alloc(dev); in owl_emac_mdio_init()
1338 if (!priv->mii) { in owl_emac_mdio_init()
1339 ret = -ENOMEM; in owl_emac_mdio_init()
1343 snprintf(priv->mii->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); in owl_emac_mdio_init()
1344 priv->mii->name = "owl-emac-mdio"; in owl_emac_mdio_init()
1345 priv->mii->parent = dev; in owl_emac_mdio_init()
1346 priv->mii->read = owl_emac_mdio_read; in owl_emac_mdio_init()
1347 priv->mii->write = owl_emac_mdio_write; in owl_emac_mdio_init()
1348 priv->mii->phy_mask = ~0; /* Mask out all PHYs from auto probing. */ in owl_emac_mdio_init()
1349 priv->mii->priv = priv; in owl_emac_mdio_init()
1351 ret = devm_of_mdiobus_register(dev, priv->mii, mdio_node); in owl_emac_mdio_init()
1364 phy = of_phy_get_and_connect(netdev, dev->of_node, in owl_emac_phy_init()
1367 return -ENODEV; in owl_emac_phy_init()
1379 struct device *dev = netdev->dev.parent; in owl_emac_get_mac_addr()
1383 if (!ret && is_valid_ether_addr(netdev->dev_addr)) in owl_emac_get_mac_addr()
1387 dev_warn(dev, "using random MAC address %pM\n", netdev->dev_addr); in owl_emac_get_mac_addr()
1395 disable_irq(netdev->irq); in owl_emac_suspend()
1402 clk_bulk_disable_unprepare(OWL_EMAC_NCLKS, priv->clks); in owl_emac_suspend()
1413 ret = clk_bulk_prepare_enable(OWL_EMAC_NCLKS, priv->clks); in owl_emac_resume()
1423 clk_bulk_disable_unprepare(OWL_EMAC_NCLKS, priv->clks); in owl_emac_resume()
1430 enable_irq(netdev->irq); in owl_emac_resume()
1439 clk_bulk_disable_unprepare(OWL_EMAC_NCLKS, priv->clks); in owl_emac_clk_disable_unprepare()
1448 switch (priv->phy_mode) { in owl_emac_clk_set_rate()
1459 priv->phy_mode); in owl_emac_clk_set_rate()
1460 return -EOPNOTSUPP; in owl_emac_clk_set_rate()
1463 ret = clk_set_rate(priv->clks[OWL_EMAC_CLK_RMII].clk, rate); in owl_emac_clk_set_rate()
1472 struct device *dev = &pdev->dev; in owl_emac_probe()
1479 return -ENOMEM; in owl_emac_probe()
1485 priv->netdev = netdev; in owl_emac_probe()
1486 priv->msg_enable = netif_msg_init(-1, OWL_EMAC_DEFAULT_MSG_ENABLE); in owl_emac_probe()
1488 ret = of_get_phy_mode(dev->of_node, &priv->phy_mode); in owl_emac_probe()
1494 spin_lock_init(&priv->lock); in owl_emac_probe()
1502 ret = owl_emac_ring_alloc(dev, &priv->rx_ring, OWL_EMAC_RX_RING_SIZE); in owl_emac_probe()
1506 ret = owl_emac_ring_alloc(dev, &priv->tx_ring, OWL_EMAC_TX_RING_SIZE); in owl_emac_probe()
1510 priv->base = devm_platform_ioremap_resource(pdev, 0); in owl_emac_probe()
1511 if (IS_ERR(priv->base)) in owl_emac_probe()
1512 return PTR_ERR(priv->base); in owl_emac_probe()
1514 netdev->irq = platform_get_irq(pdev, 0); in owl_emac_probe()
1515 if (netdev->irq < 0) in owl_emac_probe()
1516 return netdev->irq; in owl_emac_probe()
1518 ret = devm_request_irq(dev, netdev->irq, owl_emac_handle_irq, in owl_emac_probe()
1519 IRQF_SHARED, netdev->name, netdev); in owl_emac_probe()
1521 dev_err(dev, "failed to request irq: %d\n", netdev->irq); in owl_emac_probe()
1526 priv->clks[i].id = owl_emac_clk_names[i]; in owl_emac_probe()
1528 ret = devm_clk_bulk_get(dev, OWL_EMAC_NCLKS, priv->clks); in owl_emac_probe()
1532 ret = clk_bulk_prepare_enable(OWL_EMAC_NCLKS, priv->clks); in owl_emac_probe()
1544 priv->reset = devm_reset_control_get_exclusive(dev, NULL); in owl_emac_probe()
1545 if (IS_ERR(priv->reset)) in owl_emac_probe()
1546 return dev_err_probe(dev, PTR_ERR(priv->reset), in owl_emac_probe()
1566 INIT_WORK(&priv->mac_reset_task, owl_emac_reset_task); in owl_emac_probe()
1568 netdev->min_mtu = OWL_EMAC_MTU_MIN; in owl_emac_probe()
1569 netdev->max_mtu = OWL_EMAC_MTU_MAX; in owl_emac_probe()
1570 netdev->watchdog_timeo = OWL_EMAC_TX_TIMEOUT; in owl_emac_probe()
1571 netdev->netdev_ops = &owl_emac_netdev_ops; in owl_emac_probe()
1572 netdev->ethtool_ops = &owl_emac_ethtool_ops; in owl_emac_probe()
1573 netif_napi_add(netdev, &priv->napi, owl_emac_poll); in owl_emac_probe()
1577 netif_napi_del(&priv->napi); in owl_emac_probe()
1578 phy_disconnect(netdev->phydev); in owl_emac_probe()
1589 netif_napi_del(&priv->napi); in owl_emac_remove()
1590 phy_disconnect(priv->netdev->phydev); in owl_emac_remove()
1591 cancel_work_sync(&priv->mac_reset_task); in owl_emac_remove()
1595 { .compatible = "actions,owl-emac", },
1614 MODULE_DESCRIPTION("Actions Semi Owl SoCs Ethernet MAC Driver");