Lines Matching +full:0 +full:xee000000
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
65 /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
119 #define VORTEX_TOTAL_SIZE 0x20
120 #define BOOMERANG_TOTAL_SIZE 0x40
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
222 CH_3C590 = 0,
379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
426 {0,} /* 0 terminated list. */
438 #define EL3_CMD 0x0e
439 #define EL3_STATUS 0x0e
448 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
467 IntReq = 0x0040, StatsFull = 0x0080,
474 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
476 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
477 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
478 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
481 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
482 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
483 IntrStatus=0x0E, /* Valid in all windows. */
486 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
487 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
488 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
492 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
501 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
511 #define RAM_SIZE(v) BFEXT(v, 0, 3)
523 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
524 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
525 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
526 Media_LnkBeat = 0x0800,
529 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
534 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
535 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
541 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
542 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
544 __le32 next; /* Last entry points to 0. */
551 RxDComplete=0x00008000, RxDError=0x4000,
560 #define DO_ZEROCOPY 0
564 __le32 next; /* Last entry points to 0. */
565 __le32 status; /* bits 0:12 length, others see below. */
579 CRCDisable=0x2000, TxDComplete=0x8000,
580 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
581 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
585 enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
716 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
727 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
728 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
729 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
730 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
731 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
732 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
733 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
734 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
735 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
736 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
737 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
787 static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
788 static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
789 static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
790 static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
791 static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
792 static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
799 static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
804 module_param(debug, int, 0);
805 module_param(global_options, int, 0);
806 module_param_array(options, int, NULL, 0);
807 module_param(global_full_duplex, int, 0);
808 module_param_array(full_duplex, int, NULL, 0);
809 module_param_array(hw_checksums, int, NULL, 0);
810 module_param_array(flow_ctrl, int, NULL, 0);
811 module_param(global_enable_wol, int, 0);
812 module_param_array(enable_wol, int, NULL, 0);
813 module_param(rx_copybreak, int, 0);
814 module_param(max_interrupt_work, int, 0);
815 module_param_hw(compaq_ioaddr, int, ioport, 0);
816 module_param_hw(compaq_irq, int, irq, 0);
817 module_param(compaq_device_id, int, 0);
818 module_param(watchdog, int, 0);
819 module_param(global_use_mmio, int, 0);
820 module_param_array(use_mmio, int, NULL, 0);
821 MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
822 MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
826 MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
827 MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
828 MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
837 MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
853 return 0; in vortex_suspend()
858 return 0; in vortex_suspend()
867 return 0; in vortex_resume()
875 return 0; in vortex_resume()
915 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12, in vortex_eisa_probe()
923 return 0; in vortex_eisa_probe()
945 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD); in vortex_eisa_remove()
949 return 0; in vortex_eisa_remove()
963 /* returns count found (>= 0), or negative on error */
966 int eisa_found = 0; in vortex_eisa_init()
994 /* returns count (>= 0), or negative on error */
1004 if (rc < 0) in vortex_init_one()
1008 if (rc < 0) in vortex_init_one()
1013 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) { in vortex_init_one()
1016 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0; in vortex_init_one()
1017 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0) in vortex_init_one()
1018 pci_bar = use_mmio[unit] ? 1 : 0; in vortex_init_one()
1020 pci_bar = global_use_mmio ? 1 : 0; in vortex_init_one()
1022 ioaddr = pci_iomap(pdev, pci_bar, 0); in vortex_init_one()
1023 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */ in vortex_init_one()
1024 ioaddr = pci_iomap(pdev, 0, 0); in vortex_init_one()
1032 if (rc < 0) in vortex_init_one()
1084 * Return 0 on success.
1093 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */ in vortex_probe1()
1138 if (options[card_idx] >= 0) in vortex_probe1()
1142 if (option > 0) { in vortex_probe1()
1143 if (option & 0x8000) in vortex_probe1()
1145 if (option & 0x4000) in vortex_probe1()
1147 if (option & 0x0400) in vortex_probe1()
1167 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0; in vortex_probe1()
1207 vp->mii.phy_id_mask = 0x1f; in vortex_probe1()
1208 vp->mii.reg_num_mask = 0x1f; in vortex_probe1()
1229 if (option >= 0) { in vortex_probe1()
1230 vp->media_override = ((option & 7) == 2) ? 0 : option & 15; in vortex_probe1()
1233 vp->full_duplex = (option & 0x200) ? 1 : 0; in vortex_probe1()
1234 vp->bus_master = (option & 16) ? 1 : 0; in vortex_probe1()
1237 if (global_full_duplex > 0) in vortex_probe1()
1239 if (global_enable_wol > 0) in vortex_probe1()
1243 if (full_duplex[card_idx] > 0) in vortex_probe1()
1245 if (flow_ctrl[card_idx] > 0) in vortex_probe1()
1247 if (enable_wol[card_idx] > 0) in vortex_probe1()
1258 base = 0x230; in vortex_probe1()
1260 base = EEPROM_Read + 0x30; in vortex_probe1()
1264 for (i = 0; i < 0x40; i++) { in vortex_probe1()
1266 window_write16(vp, base + i, 0, Wn0EepromCmd); in vortex_probe1()
1268 for (timer = 10; timer >= 0; timer--) { in vortex_probe1()
1270 if ((window_read16(vp, 0, Wn0EepromCmd) & in vortex_probe1()
1271 0x8000) == 0) in vortex_probe1()
1274 eeprom[i] = window_read16(vp, 0, Wn0EepromData); in vortex_probe1()
1277 for (i = 0; i < 0x18; i++) in vortex_probe1()
1279 checksum = (checksum ^ (checksum >> 8)) & 0xff; in vortex_probe1()
1280 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */ in vortex_probe1()
1281 while (i < 0x21) in vortex_probe1()
1283 checksum = (checksum ^ (checksum >> 8)) & 0xff; in vortex_probe1()
1285 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO)) in vortex_probe1()
1287 for (i = 0; i < 3; i++) in vortex_probe1()
1299 for (i = 0; i < 6; i++) in vortex_probe1()
1305 if (dev->irq <= 0 || dev->irq >= nr_irqs) in vortex_probe1()
1309 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1; in vortex_probe1()
1312 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14], in vortex_probe1()
1320 vp->cb_fn_base = pci_iomap(pdev, 2, 0); in vortex_probe1()
1333 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010; in vortex_probe1()
1335 n |= 0x10; in vortex_probe1()
1337 n |= 0x4000; in vortex_probe1()
1340 window_write16(vp, 0x0800, 0, 0); in vortex_probe1()
1349 if (vp->info1 & 0x8000) { in vortex_probe1()
1359 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */ in vortex_probe1()
1360 vp->available_media = 0x40; in vortex_probe1()
1387 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) || in vortex_probe1()
1389 int phy, phy_idx = 0; in vortex_probe1()
1395 for (phy = 0; phy < 32 && phy_idx < 1; phy++) { in vortex_probe1()
1402 if (phy == 0) in vortex_probe1()
1409 if (mii_status && mii_status != 0xffff) { in vortex_probe1()
1415 if ((mii_status & 0x0040) == 0) in vortex_probe1()
1420 if (phy_idx == 0) { in vortex_probe1()
1422 vp->phys[0] = 24; in vortex_probe1()
1424 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE); in vortex_probe1()
1427 vp->advertising &= ~0x02A0; in vortex_probe1()
1428 mdio_write(dev, vp->phys[0], 4, vp->advertising); in vortex_probe1()
1431 vp->mii.phy_id = vp->phys[0]; in vortex_probe1()
1441 vp->bus_master = 0; /* AKPM: vortex only */ in vortex_probe1()
1472 if (retval == 0) in vortex_probe1()
1473 return 0; in vortex_probe1()
1495 for (i = 0; i < 2000; i++) { in issue_and_wait()
1501 for (i = 0; i < 100000; i++) { in issue_and_wait()
1504 pr_info("%s: command 0x%04x took %d usecs\n", in issue_and_wait()
1510 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n", in issue_and_wait()
1524 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) | in vortex_set_duplex()
1525 (vp->large_frames ? 0x40 : 0) | in vortex_set_duplex()
1527 0x100 : 0), in vortex_set_duplex()
1534 unsigned int ok_to_print = 0; in vortex_check_media()
1553 int i, mii_reg5, err = 0; in vortex_up()
1596 timer_setup(&vp->timer, vortex_timer, 0); in vortex_up()
1606 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config); in vortex_up()
1610 mdio_read(dev, vp->phys[0], MII_BMSR); in vortex_up()
1611 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA); in vortex_up()
1612 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0); in vortex_up()
1624 issue_and_wait(dev, RxReset|0x04); in vortex_up()
1627 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD); in vortex_up()
1635 for (i = 0; i < 6; i++) in vortex_up()
1638 window_write16(vp, 0, 2, i); in vortex_up()
1641 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010; in vortex_up()
1643 n |= 0x10; in vortex_up()
1645 n |= 0x4000; in vortex_up()
1662 for (i = 0; i < 10; i++) in vortex_up()
1669 window_write16(vp, 0x0040, 4, Wn4_NetDiag); in vortex_up()
1672 vp->cur_rx = 0; in vortex_up()
1675 iowrite32(0x0020, ioaddr + PktStatus); in vortex_up()
1679 vp->cur_tx = vp->dirty_tx = 0; in vortex_up()
1683 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */ in vortex_up()
1684 vp->rx_ring[i].status = 0; in vortex_up()
1685 for (i = 0; i < TX_RING_SIZE; i++) in vortex_up()
1687 iowrite32(0, ioaddr + DownListPtr); in vortex_up()
1701 (vp->bus_master ? DMADone : 0); in vortex_up()
1703 (vp->full_bus_master_rx ? 0 : RxComplete) | in vortex_up()
1705 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete; in vortex_up()
1712 iowrite32(0x8000, vp->cb_fn_base + 4); in vortex_up()
1736 for (i = 0; i < RX_RING_SIZE; i++) { in vortex_open()
1739 vp->rx_ring[i].status = 0; /* Clear complete bit. */ in vortex_open()
1769 for (i = 0; i < RX_RING_SIZE; i++) { in vortex_open()
1790 int ok = 0; in vortex_timer()
1819 vortex_check_media(dev, 0); in vortex_timer()
1866 pr_debug("wrote 0x%08x to Wn3_Config\n", config); in vortex_timer()
1896 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88) in vortex_tx_timeout()
1906 if (vortex_debug > 0) in vortex_tx_timeout()
1914 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0) in vortex_tx_timeout()
1943 int do_tx_reset = 0, reset_mask = 0; in vortex_error()
1944 unsigned char tx_status = 0; in vortex_error()
1947 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status); in vortex_error()
1954 (tx_status != 0x88 && vortex_debug > 0)) { in vortex_error()
1957 if (tx_status == 0x82) { in vortex_error()
1963 if (tx_status & 0x14) dev->stats.tx_fifo_errors++; in vortex_error()
1964 if (tx_status & 0x38) dev->stats.tx_aborted_errors++; in vortex_error()
1965 if (tx_status & 0x08) vp->xstats.tx_max_collisions++; in vortex_error()
1966 iowrite8(0, ioaddr + TxStatus); in vortex_error()
1967 if (tx_status & 0x30) { /* txJabber or txUnderrun */ in vortex_error()
1969 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */ in vortex_error()
1971 reset_mask = 0x0108; /* Reset interface logic, but not download logic */ in vortex_error()
1987 if (DoneDidThat == 0 && in vortex_error()
2010 /* 0x80000000 PCI master abort. */ in vortex_error()
2011 /* 0x40000000 PCI target abort. */ in vortex_error()
2017 vortex_down(dev, 0); in vortex_error()
2018 issue_and_wait(dev, TotalReset | 0xff); in vortex_error()
2020 } else if (fifo_diag & 0x0400) in vortex_error()
2022 if (fifo_diag & 0x3000) { in vortex_error()
2024 issue_and_wait(dev, RxReset|0x07); in vortex_error()
2092 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) { in vortex_start_xmit()
2093 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */ in vortex_start_xmit()
2097 if (tx_status & 0x04) dev->stats.tx_fifo_errors++; in vortex_start_xmit()
2098 if (tx_status & 0x38) dev->stats.tx_aborted_errors++; in vortex_start_xmit()
2099 if (tx_status & 0x30) { in vortex_start_xmit()
2104 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */ in vortex_start_xmit()
2138 if (vortex_debug > 0) in boomerang_start_xmit()
2147 vp->tx_ring[entry].next = 0; in boomerang_start_xmit()
2160 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr); in boomerang_start_xmit()
2161 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG); in boomerang_start_xmit()
2170 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr); in boomerang_start_xmit()
2171 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb)); in boomerang_start_xmit()
2173 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in boomerang_start_xmit()
2177 0, in boomerang_start_xmit()
2181 for(i = i-1; i >= 0; i--) in boomerang_start_xmit()
2188 le32_to_cpu(vp->tx_ring[entry].frag[0].addr), in boomerang_start_xmit()
2189 le32_to_cpu(vp->tx_ring[entry].frag[0].length), in boomerang_start_xmit()
2217 if (ioread32(ioaddr + DownListPtr) == 0) { in boomerang_start_xmit()
2250 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2260 int handled = 0; in _vortex_interrupt()
2261 unsigned int bytes_compl = 0, pkts_compl = 0; in _vortex_interrupt()
2268 pr_debug("vortex_interrupt(). status=0x%4x\n", status); in _vortex_interrupt()
2270 if ((status & IntLatch) == 0) in _vortex_interrupt()
2276 vp->deferred = 0; in _vortex_interrupt()
2279 if (status == 0xffff) /* h/w no longer present (hotplug)? */ in _vortex_interrupt()
2305 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) { in _vortex_interrupt()
2306 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */ in _vortex_interrupt()
2326 if (status == 0xffff) in _vortex_interrupt()
2336 if (--work_done < 0) { in _vortex_interrupt()
2344 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD); in _vortex_interrupt()
2376 int handled = 0; in _boomerang_interrupt()
2377 unsigned int bytes_compl = 0, pkts_compl = 0; in _boomerang_interrupt()
2386 pr_debug("boomerang_interrupt. status=0x%4x\n", status); in _boomerang_interrupt()
2388 if ((status & IntLatch) == 0) in _boomerang_interrupt()
2392 if (status == 0xffff) { /* h/w no longer present (hotplug)? */ in _boomerang_interrupt()
2394 pr_debug("boomerang_interrupt(1): status = 0xffff\n"); in _boomerang_interrupt()
2400 vp->deferred = 0; in _boomerang_interrupt()
2421 while (vp->cur_tx - dirty_tx > 0) { in _boomerang_interrupt()
2428 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0) in _boomerang_interrupt()
2437 le32_to_cpu(vp->tx_ring[entry].frag[0].addr), in _boomerang_interrupt()
2438 le32_to_cpu(vp->tx_ring[entry].frag[0].length)&0xFFF, in _boomerang_interrupt()
2444 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF, in _boomerang_interrupt()
2472 if (--work_done < 0) { in _boomerang_interrupt()
2480 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD); in _boomerang_interrupt()
2489 iowrite32(0x8000, vp->cb_fn_base + 4); in _boomerang_interrupt()
2498 vp->handling_irq = 0; in _boomerang_interrupt()
2532 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) { in vortex_rx()
2533 if (rx_status & 0x4000) { /* Error, update stats. */ in vortex_rx()
2538 if (rx_error & 0x01) dev->stats.rx_over_errors++; in vortex_rx()
2539 if (rx_error & 0x02) dev->stats.rx_length_errors++; in vortex_rx()
2540 if (rx_error & 0x04) dev->stats.rx_frame_errors++; in vortex_rx()
2541 if (rx_error & 0x08) dev->stats.rx_crc_errors++; in vortex_rx()
2542 if (rx_error & 0x10) dev->stats.rx_length_errors++; in vortex_rx()
2545 int pkt_len = rx_status & 0x1fff; in vortex_rx()
2556 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) { in vortex_rx()
2562 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000) in vortex_rx()
2575 for (i = 200; i >= 0; i--) in vortex_rx()
2579 } else if (vortex_debug > 0) in vortex_rx()
2587 return 0; in vortex_rx()
2603 if (--rx_work_limit < 0) in boomerang_rx()
2610 if (rx_error & 0x01) dev->stats.rx_over_errors++; in boomerang_rx()
2611 if (rx_error & 0x02) dev->stats.rx_length_errors++; in boomerang_rx()
2612 if (rx_error & 0x04) dev->stats.rx_frame_errors++; in boomerang_rx()
2613 if (rx_error & 0x08) dev->stats.rx_crc_errors++; in boomerang_rx()
2614 if (rx_error & 0x10) dev->stats.rx_length_errors++; in boomerang_rx()
2617 int pkt_len = rx_status & 0x1fff; in boomerang_rx()
2665 int csum_bits = rx_status & 0xee000000; in boomerang_rx()
2678 vp->rx_ring[entry].status = 0; /* Clear complete bit. */ in boomerang_rx()
2682 return 0; in boomerang_rx()
2704 set_8021q_mode(dev, 0); in vortex_down()
2710 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD); in vortex_down()
2714 iowrite32(0, ioaddr + UpListPtr); in vortex_down()
2716 iowrite32(0, ioaddr + DownListPtr); in vortex_down()
2745 (vp->drv_flags & HAS_HWCKSM) == 0 && in vortex_close()
2755 for (i = 0; i < RX_RING_SIZE; i++) in vortex_close()
2764 for (i = 0; i < TX_RING_SIZE; i++) { in vortex_close()
2770 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++) in vortex_close()
2773 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF, in vortex_close()
2784 return 0; in vortex_close()
2790 if (vortex_debug > 0) { in dump_tx_ring()
2796 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */ in dump_tx_ring()
2806 for (i = 0; i < TX_RING_SIZE; i++) { in dump_tx_ring()
2810 length = le32_to_cpu(vp->tx_ring[i].frag[0].length); in dump_tx_ring()
2851 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0); in update_stats()
2857 0x30) << 4; in update_stats()
2876 dev->stats.rx_bytes += (up & 0x0f) << 16; in update_stats()
2877 dev->stats.tx_bytes += (up & 0xf0) << 12; in update_stats()
2895 return 0; in vortex_get_link_ksettings()
2937 data[0] = vp->xstats.tx_deferred; in vortex_get_ethtool_stats()
2972 "EISA 0x%lx %d", dev->base_addr, dev->irq); in vortex_get_drvinfo()
2985 wol->wolopts = 0; in vortex_get_wol()
3003 vp->enable_wol = 0; in vortex_set_wol()
3006 return 0; in vortex_set_wol()
3033 pci_power_t state = 0; in vortex_ioctl()
3040 if(state != 0) in vortex_ioctl()
3043 if(state != 0) in vortex_ioctl()
3078 #define VLAN_ETHER_TYPE 0x8100
3105 mac_ctrl |= 0x40; in set_8021q_mode()
3107 mac_ctrl &= ~0x40; in set_8021q_mode()
3133 #define MDIO_SHIFT_CLK 0x01
3134 #define MDIO_DIR_WRITE 0x04
3135 #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3136 #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3137 #define MDIO_DATA_READ 0x02
3138 #define MDIO_ENB_IN 0x00
3145 while (-- bits >= 0) { in mdio_sync()
3158 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location; in mdio_read()
3159 unsigned int retval = 0; in mdio_read()
3167 for (i = 14; i >= 0; i--) { in mdio_read()
3176 for (i = 19; i > 0; i--) { in mdio_read()
3181 MDIO_DATA_READ) ? 1 : 0); in mdio_read()
3189 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff; in mdio_read()
3195 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value; in mdio_write()
3204 for (i = 31; i >= 0; i--) { in mdio_write()
3213 for (i = 1; i >= 0; i--) { in mdio_write()
3235 window_write16(vp, 2, 7, 0x0c); in acpi_set_WOL()
3243 vp->enable_wol = 0; in acpi_set_WOL()
3279 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14), in vortex_remove_one()
3315 if (pci_rc == 0) in vortex_init()
3317 if (eisa_rc > 0) in vortex_init()
3320 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV; in vortex_init()