Lines Matching +full:power +full:- +full:role
1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2016-2018 NXP
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
107 sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op); in sja1105_cgu_idiv_packing()
108 sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op); in sja1105_cgu_idiv_packing()
109 sja1105_packing(buf, &idiv->idiv, 5, 2, size, op); in sja1105_cgu_idiv_packing()
110 sja1105_packing(buf, &idiv->pd, 0, 0, size, op); in sja1105_cgu_idiv_packing()
116 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_idiv_config()
117 struct device *dev = priv->ds->dev; in sja1105_cgu_idiv_config()
121 if (regs->cgu_idiv[port] == SJA1105_RSV_ADDR) in sja1105_cgu_idiv_config()
126 return -ERANGE; in sja1105_cgu_idiv_config()
132 idiv.idiv = factor - 1; /* Divide by 1 or 10 */ in sja1105_cgu_idiv_config()
133 idiv.pd = enabled ? 0 : 1; /* Power down? */ in sja1105_cgu_idiv_config()
136 return sja1105_xfer_buf(priv, SPI_WRITE, regs->cgu_idiv[port], in sja1105_cgu_idiv_config()
146 sja1105_packing(buf, &cmd->clksrc, 28, 24, size, op); in sja1105_cgu_mii_control_packing()
147 sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op); in sja1105_cgu_mii_control_packing()
148 sja1105_packing(buf, &cmd->pd, 0, 0, size, op); in sja1105_cgu_mii_control_packing()
152 int port, sja1105_mii_role_t role) in sja1105_cgu_mii_tx_clk_config() argument
154 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_mii_tx_clk_config()
173 if (regs->mii_tx_clk[port] == SJA1105_RSV_ADDR) in sja1105_cgu_mii_tx_clk_config()
176 if (role == XMII_MAC) in sja1105_cgu_mii_tx_clk_config()
184 mii_tx_clk.pd = 0; /* Power Down off => enabled */ in sja1105_cgu_mii_tx_clk_config()
187 return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_tx_clk[port], in sja1105_cgu_mii_tx_clk_config()
194 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_mii_rx_clk_config()
205 if (regs->mii_rx_clk[port] == SJA1105_RSV_ADDR) in sja1105_cgu_mii_rx_clk_config()
211 mii_rx_clk.pd = 0; /* Power Down off => enabled */ in sja1105_cgu_mii_rx_clk_config()
214 return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_rx_clk[port], in sja1105_cgu_mii_rx_clk_config()
221 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_mii_ext_tx_clk_config()
232 if (regs->mii_ext_tx_clk[port] == SJA1105_RSV_ADDR) in sja1105_cgu_mii_ext_tx_clk_config()
238 mii_ext_tx_clk.pd = 0; /* Power Down off => enabled */ in sja1105_cgu_mii_ext_tx_clk_config()
241 return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_tx_clk[port], in sja1105_cgu_mii_ext_tx_clk_config()
248 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_mii_ext_rx_clk_config()
259 if (regs->mii_ext_rx_clk[port] == SJA1105_RSV_ADDR) in sja1105_cgu_mii_ext_rx_clk_config()
265 mii_ext_rx_clk.pd = 0; /* Power Down off => enabled */ in sja1105_cgu_mii_ext_rx_clk_config()
268 return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_rx_clk[port], in sja1105_cgu_mii_ext_rx_clk_config()
273 sja1105_mii_role_t role) in sja1105_mii_clocking_setup() argument
275 struct device *dev = priv->ds->dev; in sja1105_mii_clocking_setup()
278 dev_dbg(dev, "Configuring MII-%s clocking\n", in sja1105_mii_clocking_setup()
279 (role == XMII_MAC) ? "MAC" : "PHY"); in sja1105_mii_clocking_setup()
280 /* If role is MAC, disable IDIV in sja1105_mii_clocking_setup()
281 * If role is PHY, enable IDIV and configure for 1/1 divider in sja1105_mii_clocking_setup()
283 rc = sja1105_cgu_idiv_config(priv, port, (role == XMII_PHY), 1); in sja1105_mii_clocking_setup()
288 * * If role is MAC, select TX_CLK_n in sja1105_mii_clocking_setup()
289 * * If role is PHY, select IDIV_n in sja1105_mii_clocking_setup()
291 rc = sja1105_cgu_mii_tx_clk_config(priv, port, role); in sja1105_mii_clocking_setup()
302 if (role == XMII_PHY) { in sja1105_mii_clocking_setup()
328 sja1105_packing(buf, &cmd->pllclksrc, 28, 24, size, op); in sja1105_cgu_pll_control_packing()
329 sja1105_packing(buf, &cmd->msel, 23, 16, size, op); in sja1105_cgu_pll_control_packing()
330 sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op); in sja1105_cgu_pll_control_packing()
331 sja1105_packing(buf, &cmd->psel, 9, 8, size, op); in sja1105_cgu_pll_control_packing()
332 sja1105_packing(buf, &cmd->direct, 7, 7, size, op); in sja1105_cgu_pll_control_packing()
333 sja1105_packing(buf, &cmd->fbsel, 6, 6, size, op); in sja1105_cgu_pll_control_packing()
334 sja1105_packing(buf, &cmd->bypass, 1, 1, size, op); in sja1105_cgu_pll_control_packing()
335 sja1105_packing(buf, &cmd->pd, 0, 0, size, op); in sja1105_cgu_pll_control_packing()
341 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_rgmii_tx_clk_config()
346 if (regs->rgmii_tx_clk[port] == SJA1105_RSV_ADDR) in sja1105_cgu_rgmii_tx_clk_config()
349 if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS]) { in sja1105_cgu_rgmii_tx_clk_config()
366 /* Power Down off => enabled */ in sja1105_cgu_rgmii_tx_clk_config()
370 return sja1105_xfer_buf(priv, SPI_WRITE, regs->rgmii_tx_clk[port], in sja1105_cgu_rgmii_tx_clk_config()
381 sja1105_packing(buf, &cmd->d32_os, 28, 27, size, op); in sja1105_cfg_pad_mii_packing()
382 sja1105_packing(buf, &cmd->d32_ih, 26, 26, size, op); in sja1105_cfg_pad_mii_packing()
383 sja1105_packing(buf, &cmd->d32_ipud, 25, 24, size, op); in sja1105_cfg_pad_mii_packing()
384 sja1105_packing(buf, &cmd->d10_os, 20, 19, size, op); in sja1105_cfg_pad_mii_packing()
385 sja1105_packing(buf, &cmd->d10_ih, 18, 18, size, op); in sja1105_cfg_pad_mii_packing()
386 sja1105_packing(buf, &cmd->d10_ipud, 17, 16, size, op); in sja1105_cfg_pad_mii_packing()
387 sja1105_packing(buf, &cmd->ctrl_os, 12, 11, size, op); in sja1105_cfg_pad_mii_packing()
388 sja1105_packing(buf, &cmd->ctrl_ih, 10, 10, size, op); in sja1105_cfg_pad_mii_packing()
389 sja1105_packing(buf, &cmd->ctrl_ipud, 9, 8, size, op); in sja1105_cfg_pad_mii_packing()
390 sja1105_packing(buf, &cmd->clk_os, 4, 3, size, op); in sja1105_cfg_pad_mii_packing()
391 sja1105_packing(buf, &cmd->clk_ih, 2, 2, size, op); in sja1105_cfg_pad_mii_packing()
392 sja1105_packing(buf, &cmd->clk_ipud, 1, 0, size, op); in sja1105_cfg_pad_mii_packing()
398 const struct sja1105_regs *regs = priv->info->regs; in sja1105_rgmii_cfg_pad_tx_config()
402 if (regs->pad_mii_tx[port] == SJA1105_RSV_ADDR) in sja1105_rgmii_cfg_pad_tx_config()
421 return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_tx[port], in sja1105_rgmii_cfg_pad_tx_config()
427 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cfg_pad_rx_config()
431 if (regs->pad_mii_rx[port] == SJA1105_RSV_ADDR) in sja1105_cfg_pad_rx_config()
436 /* non-Schmitt (default) */ in sja1105_cfg_pad_rx_config()
437 pad_mii_rx.d32_ipud = 2; /* RXD[3:2] input weak pull-up/down */ in sja1105_cfg_pad_rx_config()
440 /* non-Schmitt (default) */ in sja1105_cfg_pad_rx_config()
441 pad_mii_rx.d10_ipud = 2; /* RXD[1:0] input weak pull-up/down */ in sja1105_cfg_pad_rx_config()
445 /* non-Schmitt (default) */ in sja1105_cfg_pad_rx_config()
447 /* input stage weak pull-up/down: */ in sja1105_cfg_pad_rx_config()
448 /* pull-down */ in sja1105_cfg_pad_rx_config()
452 /* non-Schmitt (default) */ in sja1105_cfg_pad_rx_config()
453 pad_mii_rx.clk_ipud = 2; /* RX_CLK/RXC input pull-up/down: */ in sja1105_cfg_pad_rx_config()
457 return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_rx[port], in sja1105_cfg_pad_rx_config()
467 sja1105_packing(buf, &cmd->rxc_stable_ovr, 15, 15, size, op); in sja1105_cfg_pad_mii_id_packing()
468 sja1105_packing(buf, &cmd->rxc_delay, 14, 10, size, op); in sja1105_cfg_pad_mii_id_packing()
469 sja1105_packing(buf, &cmd->rxc_bypass, 9, 9, size, op); in sja1105_cfg_pad_mii_id_packing()
470 sja1105_packing(buf, &cmd->rxc_pd, 8, 8, size, op); in sja1105_cfg_pad_mii_id_packing()
471 sja1105_packing(buf, &cmd->txc_stable_ovr, 7, 7, size, op); in sja1105_cfg_pad_mii_id_packing()
472 sja1105_packing(buf, &cmd->txc_delay, 6, 2, size, op); in sja1105_cfg_pad_mii_id_packing()
473 sja1105_packing(buf, &cmd->txc_bypass, 1, 1, size, op); in sja1105_cfg_pad_mii_id_packing()
474 sja1105_packing(buf, &cmd->txc_pd, 0, 0, size, op); in sja1105_cfg_pad_mii_id_packing()
494 sja1105_packing(buf, &cmd->rxc_stable_ovr, 26, 26, size, op); in sja1110_cfg_pad_mii_id_packing()
495 sja1105_packing(buf, &cmd->rxc_delay, 25, 21, size, op); in sja1110_cfg_pad_mii_id_packing()
497 sja1105_packing(buf, &cmd->rxc_bypass, 17, 17, size, op); in sja1110_cfg_pad_mii_id_packing()
498 sja1105_packing(buf, &cmd->rxc_pd, 16, 16, size, op); in sja1110_cfg_pad_mii_id_packing()
499 sja1105_packing(buf, &cmd->txc_stable_ovr, 10, 10, size, op); in sja1110_cfg_pad_mii_id_packing()
500 sja1105_packing(buf, &cmd->txc_delay, 9, 5, size, op); in sja1110_cfg_pad_mii_id_packing()
502 sja1105_packing(buf, &cmd->txc_bypass, 1, 1, size, op); in sja1110_cfg_pad_mii_id_packing()
503 sja1105_packing(buf, &cmd->txc_pd, 0, 0, size, op); in sja1110_cfg_pad_mii_id_packing()
506 /* The RGMII delay setup procedure is 2-step and gets called upon each
510 * The easiest way to recover from this is to temporarily power down the TDL,
511 * as it will re-lock at the new frequency afterwards.
516 const struct sja1105_regs *regs = priv->info->regs; in sja1105pqrs_setup_rgmii_delay()
518 int rx_delay = priv->rgmii_rx_delay_ps[port]; in sja1105pqrs_setup_rgmii_delay()
519 int tx_delay = priv->rgmii_tx_delay_ps[port]; in sja1105pqrs_setup_rgmii_delay()
535 rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port], in sja1105pqrs_setup_rgmii_delay()
551 return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port], in sja1105pqrs_setup_rgmii_delay()
558 const struct sja1105_regs *regs = priv->info->regs; in sja1110_setup_rgmii_delay()
560 int rx_delay = priv->rgmii_rx_delay_ps[port]; in sja1110_setup_rgmii_delay()
561 int tx_delay = priv->rgmii_tx_delay_ps[port]; in sja1110_setup_rgmii_delay()
582 return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port], in sja1110_setup_rgmii_delay()
587 sja1105_mii_role_t role) in sja1105_rgmii_clocking_setup() argument
589 struct device *dev = priv->ds->dev; in sja1105_rgmii_clocking_setup()
594 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; in sja1105_rgmii_clocking_setup()
600 if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS]) { in sja1105_rgmii_clocking_setup()
603 } else if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS]) { in sja1105_rgmii_clocking_setup()
606 } else if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS]) { in sja1105_rgmii_clocking_setup()
609 } else if (speed == priv->info->port_speed[SJA1105_SPEED_AUTO]) { in sja1105_rgmii_clocking_setup()
616 rc = -EINVAL; in sja1105_rgmii_clocking_setup()
634 if (!priv->info->setup_rgmii_delay) in sja1105_rgmii_clocking_setup()
637 return priv->info->setup_rgmii_delay(priv, port); in sja1105_rgmii_clocking_setup()
643 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_rmii_ref_clk_config()
654 if (regs->rmii_ref_clk[port] == SJA1105_RSV_ADDR) in sja1105_cgu_rmii_ref_clk_config()
660 ref_clk.pd = 0; /* Power Down off => enabled */ in sja1105_cgu_rmii_ref_clk_config()
663 return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ref_clk[port], in sja1105_cgu_rmii_ref_clk_config()
670 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_rmii_ext_tx_clk_config()
674 if (regs->rmii_ext_tx_clk[port] == SJA1105_RSV_ADDR) in sja1105_cgu_rmii_ext_tx_clk_config()
680 ext_tx_clk.pd = 0; /* Power Down off => enabled */ in sja1105_cgu_rmii_ext_tx_clk_config()
683 return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ext_tx_clk[port], in sja1105_cgu_rmii_ext_tx_clk_config()
689 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_rmii_pll_config()
692 struct device *dev = priv->ds->dev; in sja1105_cgu_rmii_pll_config()
695 if (regs->rmii_pll1 == SJA1105_RSV_ADDR) in sja1105_cgu_rmii_pll_config()
701 * power down (PD) 0x0A010940. in sja1105_cgu_rmii_pll_config()
715 rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf, in sja1105_cgu_rmii_pll_config()
726 rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf, in sja1105_cgu_rmii_pll_config()
736 sja1105_mii_role_t role) in sja1105_rmii_clocking_setup() argument
738 struct device *dev = priv->ds->dev; in sja1105_rmii_clocking_setup()
741 dev_dbg(dev, "Configuring RMII-%s clocking\n", in sja1105_rmii_clocking_setup()
742 (role == XMII_MAC) ? "MAC" : "PHY"); in sja1105_rmii_clocking_setup()
744 if (role == XMII_MAC) { in sja1105_rmii_clocking_setup()
758 if (role == XMII_MAC) { in sja1105_rmii_clocking_setup()
769 struct device *dev = priv->ds->dev; in sja1105_clocking_setup_port()
771 sja1105_mii_role_t role; in sja1105_clocking_setup_port() local
774 mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries; in sja1105_clocking_setup_port()
777 phy_mode = mii->xmii_mode[port]; in sja1105_clocking_setup_port()
779 role = mii->phy_mac[port]; in sja1105_clocking_setup_port()
783 rc = sja1105_mii_clocking_setup(priv, port, role); in sja1105_clocking_setup_port()
786 rc = sja1105_rmii_clocking_setup(priv, port, role); in sja1105_clocking_setup_port()
789 rc = sja1105_rgmii_clocking_setup(priv, port, role); in sja1105_clocking_setup_port()
798 return -EINVAL; in sja1105_clocking_setup_port()
812 struct dsa_switch *ds = priv->ds; in sja1105_clocking_setup()
815 for (port = 0; port < ds->num_ports; port++) { in sja1105_clocking_setup()
829 sja1105_packing(buf, &outclk->clksrc, 27, 24, size, op); in sja1110_cgu_outclk_packing()
830 sja1105_packing(buf, &outclk->autoblock, 11, 11, size, op); in sja1110_cgu_outclk_packing()
831 sja1105_packing(buf, &outclk->pd, 0, 0, size, op); in sja1110_cgu_outclk_packing()
847 /* Power down the BASE_TIMER_CLK to disable the watchdog timer */ in sja1110_disable_microcontroller()
855 /* Power down the BASE_MCSS_CLOCK to gate the microcontroller off */ in sja1110_disable_microcontroller()