Lines Matching +full:25 +full:mhz

130 	idiv.clksrc    = 0x0A;            /* 25MHz */  in sja1105_cgu_idiv_config()
362 	/* RGMII: 125MHz for 1000, 25MHz for 100, 2.5MHz for 10 */  in sja1105_cgu_rgmii_tx_clk_config()
383 	sja1105_packing(buf, &cmd->d32_ipud, 25, 24, size, op);  in sja1105_cfg_pad_mii_packing()
485 	 * 0 = 2.5MHz  in sja1110_cfg_pad_mii_id_packing()
486 	 * 1 = 25MHz  in sja1110_cfg_pad_mii_id_packing()
487 	 * 2 = 50MHz  in sja1110_cfg_pad_mii_id_packing()
488 	 * 3 = 125MHz  in sja1110_cfg_pad_mii_id_packing()
495 	sja1105_packing(buf, &cmd->rxc_delay,      25, 21, size, op);  in sja1110_cfg_pad_mii_id_packing()
601 		/* 1000Mbps, IDIV disabled (125 MHz) */  in sja1105_rgmii_clocking_setup()
604 		/* 100Mbps, IDIV enabled, divide by 1 (25 MHz) */  in sja1105_rgmii_clocking_setup()
607 		/* 10Mbps, IDIV enabled, divide by 10 (2.5 MHz) */  in sja1105_rgmii_clocking_setup()
698 	/* PLL1 must be enabled and output 50 Mhz.  in sja1105_cgu_rmii_pll_config()
704 	/* Step 1: PLL1 setup for 50Mhz */  in sja1105_cgu_rmii_pll_config()
718 		dev_err(dev, "failed to configure PLL1 for 50MHz\n");  in sja1105_cgu_rmii_pll_config()
745 		/* Configure and enable PLL1 for 50Mhz output */  in sja1105_rmii_clocking_setup()