Lines Matching +full:ar9331 +full:- +full:switch
1 // SPDX-License-Identifier: GPL-2.0-only
4 * +----------------------+
5 * GMAC1----RGMII----|--MAC0 |
6 * \---MDIO1----|--REGs |----MDIO3----\
7 * | | | +------+
8 * | | +--| |
9 * | MAC1-|----RMII--M-----| PHY0 |-o P0
10 * | | | | +------+
11 * | | | +--| |
12 * | MAC2-|----RMII--------| PHY1 |-o P1
13 * | | | | +------+
14 * | | | +--| |
15 * | MAC3-|----RMII--------| PHY2 |-o P2
16 * | | | | +------+
17 * | | | +--| |
18 * | MAC4-|----RMII--------| PHY3 |-o P3
19 * | | | | +------+
20 * | | | +--| |
21 * | MAC5-|--+-RMII--M-----|-PHY4-|-o P4
22 * | | | | +------+
23 * +----------------------+ | \--CFG_SW_PHY_SWAP
24 * GMAC0---------------RMII--------------------/ \-CFG_SW_PHY_ADDR_SWAP
25 * \---MDIO0--NC
31 * CFG_SW_PHY_SWAP - swap connections of PHY0 and PHY4. If this bit is not set
36 * CFG_SW_PHY_ADDR_SWAP - swap addresses of PHY0 and PHY4
39 * set and not related to switch internal registers.
77 /* FLOW_LINK_EN - enable mac flow control config auto-neg with phy.
82 /* LINK_EN - If set, MAC is configured from PHY link status.
125 * ------------------------------------------------------------------------
136 * ------------------------------------------------------------------------
138 * ------------------------------------------------------------------------
152 /* ------------------------------------------------------------------------
154 * ------------------------------------------------------------------------
162 * ------------------------------------------------------------------------
254 struct ar9331_sw_port *p = port - port->idx; in ar9331_sw_port_to_priv()
256 return (struct ar9331_sw_priv *)((void *)p - in ar9331_sw_port_to_priv()
260 /* Warning: switch reset will reset last AR9331_SW_MDIO_PHY_MODE_PAGE request
267 ret = reset_control_assert(priv->sw_reset); in ar9331_sw_reset()
271 /* AR9331 doc do not provide any information about proper reset in ar9331_sw_reset()
272 * sequence. The AR8136 (the closes switch to the AR9331) doc says: in ar9331_sw_reset()
277 ret = reset_control_deassert(priv->sw_reset); in ar9331_sw_reset()
282 * status. AR9331 has no EEPROM support. in ar9331_sw_reset()
289 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); in ar9331_sw_reset()
296 struct ar9331_sw_priv *priv = mbus->priv; in ar9331_sw_mbus_write()
297 struct regmap *regmap = priv->regmap; in ar9331_sw_mbus_write()
319 dev_err_ratelimited(priv->dev, "PHY write error: %i\n", ret); in ar9331_sw_mbus_write()
325 struct ar9331_sw_priv *priv = mbus->priv; in ar9331_sw_mbus_read()
326 struct regmap *regmap = priv->regmap; in ar9331_sw_mbus_read()
353 dev_err_ratelimited(priv->dev, "PHY read error: %i\n", ret); in ar9331_sw_mbus_read()
359 struct device *dev = priv->dev; in ar9331_sw_mbus_init()
364 np = dev->of_node; in ar9331_sw_mbus_init()
368 return -ENOMEM; in ar9331_sw_mbus_init()
370 mbus->name = np->full_name; in ar9331_sw_mbus_init()
371 snprintf(mbus->id, MII_BUS_ID_SIZE, "%pOF", np); in ar9331_sw_mbus_init()
373 mbus->read = ar9331_sw_mbus_read; in ar9331_sw_mbus_init()
374 mbus->write = ar9331_sw_mbus_write; in ar9331_sw_mbus_init()
375 mbus->priv = priv; in ar9331_sw_mbus_init()
376 mbus->parent = dev; in ar9331_sw_mbus_init()
380 return -ENODEV; in ar9331_sw_mbus_init()
387 priv->mbus = mbus; in ar9331_sw_mbus_init()
394 struct ar9331_sw_priv *priv = ds->priv; in ar9331_sw_setup_port()
395 struct regmap *regmap = priv->regmap; in ar9331_sw_setup_port()
435 dev_err(priv->dev, "%s: error: %i\n", __func__, ret); in ar9331_sw_setup_port()
442 struct ar9331_sw_priv *priv = ds->priv; in ar9331_sw_setup()
443 struct regmap *regmap = priv->regmap; in ar9331_sw_setup()
450 /* Reset will set proper defaults. CPU - Port0 will be enabled and in ar9331_sw_setup()
451 * configured. All other ports (ports 1 - 5) are disabled in ar9331_sw_setup()
471 for (i = 0; i < ds->num_ports; i++) { in ar9331_sw_setup()
477 ds->configure_vlan_while_not_filtering = false; in ar9331_sw_setup()
481 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); in ar9331_sw_setup()
487 struct ar9331_sw_priv *priv = ds->priv; in ar9331_sw_port_disable()
488 struct regmap *regmap = priv->regmap; in ar9331_sw_port_disable()
493 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); in ar9331_sw_port_disable()
506 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | in ar9331_sw_phylink_get_caps()
509 switch (port) { in ar9331_sw_phylink_get_caps()
512 config->supported_interfaces); in ar9331_sw_phylink_get_caps()
513 config->mac_capabilities |= MAC_1000; in ar9331_sw_phylink_get_caps()
521 config->supported_interfaces); in ar9331_sw_phylink_get_caps()
531 struct ar9331_sw_priv *priv = dp->ds->priv; in ar9331_sw_phylink_mac_config()
532 struct regmap *regmap = priv->regmap; in ar9331_sw_phylink_mac_config()
535 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(dp->index), in ar9331_sw_phylink_mac_config()
539 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); in ar9331_sw_phylink_mac_config()
547 struct ar9331_sw_priv *priv = dp->ds->priv; in ar9331_sw_phylink_mac_link_down()
548 struct regmap *regmap = priv->regmap; in ar9331_sw_phylink_mac_link_down()
549 int port = dp->index; in ar9331_sw_phylink_mac_link_down()
555 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); in ar9331_sw_phylink_mac_link_down()
557 cancel_delayed_work_sync(&priv->port[port].mib_read); in ar9331_sw_phylink_mac_link_down()
568 struct ar9331_sw_priv *priv = dp->ds->priv; in ar9331_sw_phylink_mac_link_up()
569 struct regmap *regmap = priv->regmap; in ar9331_sw_phylink_mac_link_up()
570 int port = dp->index; in ar9331_sw_phylink_mac_link_up()
574 schedule_delayed_work(&priv->port[port].mib_read, 0); in ar9331_sw_phylink_mac_link_up()
577 switch (speed) { in ar9331_sw_phylink_mac_link_up()
605 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); in ar9331_sw_phylink_mac_link_up()
611 struct ethtool_pause_stats *pstats = &port->pause_stats; in ar9331_read_stats()
612 struct rtnl_link_stats64 *stats = &port->stats; in ar9331_read_stats()
617 ret = regmap_bulk_read(priv->regmap, AR9331_MIB_COUNTER(port->idx), in ar9331_read_stats()
620 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); in ar9331_read_stats()
625 spin_lock(&port->stats_lock); in ar9331_read_stats()
627 stats->rx_bytes += raw.rxgoodbyte; in ar9331_read_stats()
628 stats->tx_bytes += raw.txbyte; in ar9331_read_stats()
630 stats->rx_packets += raw.rx64byte + raw.rx128byte + raw.rx256byte + in ar9331_read_stats()
632 stats->tx_packets += raw.tx64byte + raw.tx128byte + raw.tx256byte + in ar9331_read_stats()
635 stats->rx_length_errors += raw.rxrunt + raw.rxfragment + raw.rxtoolong; in ar9331_read_stats()
636 stats->rx_crc_errors += raw.rxfcserr; in ar9331_read_stats()
637 stats->rx_frame_errors += raw.rxalignerr; in ar9331_read_stats()
638 stats->rx_missed_errors += raw.rxoverflow; in ar9331_read_stats()
639 stats->rx_dropped += raw.filtered; in ar9331_read_stats()
640 stats->rx_errors += raw.rxfcserr + raw.rxalignerr + raw.rxrunt + in ar9331_read_stats()
643 stats->tx_window_errors += raw.txlatecol; in ar9331_read_stats()
644 stats->tx_fifo_errors += raw.txunderrun; in ar9331_read_stats()
645 stats->tx_aborted_errors += raw.txabortcol; in ar9331_read_stats()
646 stats->tx_errors += raw.txoversize + raw.txabortcol + raw.txunderrun + in ar9331_read_stats()
649 stats->multicast += raw.rxmulti; in ar9331_read_stats()
650 stats->collisions += raw.txcollision; in ar9331_read_stats()
652 pstats->tx_pause_frames += raw.txpause; in ar9331_read_stats()
653 pstats->rx_pause_frames += raw.rxpause; in ar9331_read_stats()
655 spin_unlock(&port->stats_lock); in ar9331_read_stats()
665 schedule_delayed_work(&port->mib_read, STATS_INTERVAL_JIFFIES); in ar9331_do_stats_poll()
671 struct ar9331_sw_priv *priv = ds->priv; in ar9331_get_stats64()
672 struct ar9331_sw_port *p = &priv->port[port]; in ar9331_get_stats64()
674 spin_lock(&p->stats_lock); in ar9331_get_stats64()
675 memcpy(s, &p->stats, sizeof(*s)); in ar9331_get_stats64()
676 spin_unlock(&p->stats_lock); in ar9331_get_stats64()
682 struct ar9331_sw_priv *priv = ds->priv; in ar9331_get_pause_stats()
683 struct ar9331_sw_port *p = &priv->port[port]; in ar9331_get_pause_stats()
685 spin_lock(&p->stats_lock); in ar9331_get_pause_stats()
686 memcpy(pause_stats, &p->pause_stats, sizeof(*pause_stats)); in ar9331_get_pause_stats()
687 spin_unlock(&p->stats_lock); in ar9331_get_pause_stats()
708 struct regmap *regmap = priv->regmap; in ar9331_sw_irq()
714 dev_err(priv->dev, "can't read interrupt status\n"); in ar9331_sw_irq()
724 child_irq = irq_find_mapping(priv->irqdomain, 0); in ar9331_sw_irq()
730 dev_err(priv->dev, "can't write interrupt status\n"); in ar9331_sw_irq()
741 priv->irq_mask = 0; in ar9331_sw_mask_irq()
748 priv->irq_mask = AR9331_SW_GINT_PHY_INT; in ar9331_sw_unmask_irq()
755 mutex_lock(&priv->lock_irq); in ar9331_sw_irq_bus_lock()
761 struct regmap *regmap = priv->regmap; in ar9331_sw_irq_bus_sync_unlock()
765 AR9331_SW_GINT_PHY_INT, priv->irq_mask); in ar9331_sw_irq_bus_sync_unlock()
767 dev_err(priv->dev, "failed to change IRQ mask\n"); in ar9331_sw_irq_bus_sync_unlock()
769 mutex_unlock(&priv->lock_irq); in ar9331_sw_irq_bus_sync_unlock()
783 irq_set_chip_data(irq, domain->host_data); in ar9331_sw_irq_map()
806 struct device_node *np = priv->dev->of_node; in ar9331_sw_irq_init()
807 struct device *dev = priv->dev; in ar9331_sw_irq_init()
813 return irq ? irq : -EINVAL; in ar9331_sw_irq_init()
816 mutex_init(&priv->lock_irq); in ar9331_sw_irq_init()
824 priv->irqdomain = irq_domain_add_linear(np, 1, &ar9331_sw_irqdomain_ops, in ar9331_sw_irq_init()
826 if (!priv->irqdomain) { in ar9331_sw_irq_init()
828 return -EINVAL; in ar9331_sw_irq_init()
831 irq_set_parent(irq_create_mapping(priv->irqdomain, 0), irq); in ar9331_sw_irq_init()
862 struct mii_bus *sbus = priv->sbus; in ar9331_mdio_read()
875 mutex_lock_nested(&sbus->mdio_lock, MDIO_MUTEX_NESTED); in ar9331_mdio_read()
888 mutex_unlock(&sbus->mdio_lock); in ar9331_mdio_read()
892 mutex_unlock(&sbus->mdio_lock); in ar9331_mdio_read()
893 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to read register.\n"); in ar9331_mdio_read()
901 struct mii_bus *sbus = priv->sbus; in ar9331_mdio_write()
904 mutex_lock_nested(&sbus->mdio_lock, MDIO_MUTEX_NESTED); in ar9331_mdio_write()
911 mutex_unlock(&sbus->mdio_lock); in ar9331_mdio_write()
916 /* In case of this switch we work with 32bit registers on top of 16bit in ar9331_mdio_write()
932 mutex_unlock(&sbus->mdio_lock); in ar9331_mdio_write()
937 mutex_unlock(&sbus->mdio_lock); in ar9331_mdio_write()
938 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to write register.\n"); in ar9331_mdio_write()
992 .range_max = AR9331_SW_REG_PAGE - 4,
1037 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); in ar9331_sw_probe()
1039 return -ENOMEM; in ar9331_sw_probe()
1041 priv->regmap = devm_regmap_init(&mdiodev->dev, &ar9331_sw_bus, priv, in ar9331_sw_probe()
1043 if (IS_ERR(priv->regmap)) { in ar9331_sw_probe()
1044 ret = PTR_ERR(priv->regmap); in ar9331_sw_probe()
1045 dev_err(&mdiodev->dev, "regmap init failed: %d\n", ret); in ar9331_sw_probe()
1049 priv->sw_reset = devm_reset_control_get(&mdiodev->dev, "switch"); in ar9331_sw_probe()
1050 if (IS_ERR(priv->sw_reset)) { in ar9331_sw_probe()
1051 dev_err(&mdiodev->dev, "missing switch reset\n"); in ar9331_sw_probe()
1052 return PTR_ERR(priv->sw_reset); in ar9331_sw_probe()
1055 priv->sbus = mdiodev->bus; in ar9331_sw_probe()
1056 priv->dev = &mdiodev->dev; in ar9331_sw_probe()
1062 ds = &priv->ds; in ar9331_sw_probe()
1063 ds->dev = &mdiodev->dev; in ar9331_sw_probe()
1064 ds->num_ports = AR9331_SW_PORTS; in ar9331_sw_probe()
1065 ds->priv = priv; in ar9331_sw_probe()
1066 priv->ops = ar9331_sw_ops; in ar9331_sw_probe()
1067 ds->ops = &priv->ops; in ar9331_sw_probe()
1068 ds->phylink_mac_ops = &ar9331_phylink_mac_ops; in ar9331_sw_probe()
1069 dev_set_drvdata(&mdiodev->dev, priv); in ar9331_sw_probe()
1071 for (i = 0; i < ARRAY_SIZE(priv->port); i++) { in ar9331_sw_probe()
1072 struct ar9331_sw_port *port = &priv->port[i]; in ar9331_sw_probe()
1074 port->idx = i; in ar9331_sw_probe()
1075 spin_lock_init(&port->stats_lock); in ar9331_sw_probe()
1076 INIT_DELAYED_WORK(&port->mib_read, ar9331_do_stats_poll); in ar9331_sw_probe()
1086 irq_domain_remove(priv->irqdomain); in ar9331_sw_probe()
1093 struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev); in ar9331_sw_remove()
1099 for (i = 0; i < ARRAY_SIZE(priv->port); i++) { in ar9331_sw_remove()
1100 struct ar9331_sw_port *port = &priv->port[i]; in ar9331_sw_remove()
1102 cancel_delayed_work_sync(&port->mib_read); in ar9331_sw_remove()
1105 irq_domain_remove(priv->irqdomain); in ar9331_sw_remove()
1106 dsa_unregister_switch(&priv->ds); in ar9331_sw_remove()
1108 reset_control_assert(priv->sw_reset); in ar9331_sw_remove()
1113 struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev); in ar9331_sw_shutdown()
1118 dsa_switch_shutdown(&priv->ds); in ar9331_sw_shutdown()
1120 dev_set_drvdata(&mdiodev->dev, NULL); in ar9331_sw_shutdown()
1124 { .compatible = "qca,ar9331-switch" },
1141 MODULE_DESCRIPTION("Driver for Atheros AR9331 switch");