dsa/mv88e6xxx/port.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * Marvell 88E6xxx Switch Port Registers support
7  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
16 /* Offset 0x00: Port Status Register */
28 /* - Modes with PHY suffix use output instead of input clock
29  * - Modes without RMII or RGMII use MII
30  * - Modes without speed do not have a fixed speed specified in the manual
31  *   ("DC to x MHz" - variable clock support?)
165 /* Offset 0x04: Port Control Register */
200 /* Offset 0x05: Port Control 1 */
208 /* Offset 0x06: Port Based VLAN Map */
212 /* Offset 0x07: Default Port VLAN ID & Priority */
216 /* Offset 0x08: Port Control 2 Register */
245 /* Offset 0x0B: Port Association Vector */
253 /* Offset 0x0C: Port ATU Control */
287 /* Offset 0x0F: Port Special Ether Type */
294 /* Offset 0x10: Extended Port Control Command */
300 /* Offset 0x11: Extended Port Control Data */
312 /* Offset 0x18: IEEE Priority Mapping Table */
326 /* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */
329 /* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */
344 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
346 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
348 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg,
351 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
353 int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
354 				   phy_interface_t mode);
355 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
356 				   phy_interface_t mode);
357 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
358 				   phy_interface_t mode);
360 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link);
362 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
363 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
365 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
367 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
369 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
371 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
373 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
375 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
377 int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
381 					      int port);
383 					      int port);
385 					       int port);
387 					       int port);
389 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);
391 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map);
393 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid);
394 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid);
396 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid);
397 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid);
399 int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port,
402 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
403 				  u16 mode);
404 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
405 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
406 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
407 				   enum mv88e6xxx_egress_mode mode);
408 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
409 				  enum mv88e6xxx_frame_mode mode);
410 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
411 				  enum mv88e6xxx_frame_mode mode);
413 				       int port, bool unicast);
415 				       int port, bool multicast);
416 int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port,
418 int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port,
420 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
421 			      enum mv88e6xxx_policy_mapping mapping,
423 int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port,
424 			       enum mv88e6xxx_policy_mapping mapping,
426 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
430 			       int port);
431 int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
434 int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
436 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
438 int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port,
440 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
442 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
443 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
444 int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port,
446 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
448 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
450 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
451 			     phy_interface_t mode);
452 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
453 			     phy_interface_t mode);
454 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
455 			      phy_interface_t mode);
456 int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
457 			      phy_interface_t mode);
458 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
459 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
460 int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port,
462 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map);
463 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
465 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port,
469 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port);
470 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port);
473 				int port, int reg, u16 val);
475 int mv88e6xxx_port_hidden_read(struct mv88e6xxx_chip *chip, int block, int port,