Lines Matching +full:port +full:- +full:mapping +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88E6xxx Switch Port Registers support
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
18 #include "port.h"
21 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_read() argument
24 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_read()
29 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_wait_bit() argument
32 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_wait_bit()
37 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_write() argument
40 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_write()
50 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, in mv88e6185_port_set_pause() argument
56 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6185_port_set_pause()
65 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); in mv88e6185_port_set_pause()
72 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
77 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_rgmii_delay() argument
78 phy_interface_t mode) in mv88e6xxx_port_set_rgmii_delay() argument
83 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6xxx_port_set_rgmii_delay()
90 switch (mode) { in mv88e6xxx_port_set_rgmii_delay()
107 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6xxx_port_set_rgmii_delay()
111 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port, in mv88e6xxx_port_set_rgmii_delay()
118 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, in mv88e6352_port_set_rgmii_delay() argument
119 phy_interface_t mode) in mv88e6352_port_set_rgmii_delay() argument
121 if (port < 5) in mv88e6352_port_set_rgmii_delay()
122 return -EOPNOTSUPP; in mv88e6352_port_set_rgmii_delay()
124 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); in mv88e6352_port_set_rgmii_delay()
127 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, in mv88e6390_port_set_rgmii_delay() argument
128 phy_interface_t mode) in mv88e6390_port_set_rgmii_delay() argument
130 if (port != 0) in mv88e6390_port_set_rgmii_delay()
131 return -EOPNOTSUPP; in mv88e6390_port_set_rgmii_delay()
133 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); in mv88e6390_port_set_rgmii_delay()
136 int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, in mv88e6320_port_set_rgmii_delay() argument
137 phy_interface_t mode) in mv88e6320_port_set_rgmii_delay() argument
139 if (port != 2 && port != 5 && port != 6) in mv88e6320_port_set_rgmii_delay()
140 return -EOPNOTSUPP; in mv88e6320_port_set_rgmii_delay()
142 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); in mv88e6320_port_set_rgmii_delay()
145 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link) in mv88e6xxx_port_set_link() argument
150 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6xxx_port_set_link()
169 return -EINVAL; in mv88e6xxx_port_set_link()
172 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6xxx_port_set_link()
176 dev_dbg(chip->dev, "p%d: %s link %s\n", port, in mv88e6xxx_port_set_link()
183 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) in mv88e6xxx_port_sync_link() argument
185 const struct mv88e6xxx_ops *ops = chip->info->ops; in mv88e6xxx_port_sync_link()
194 if (ops->port_set_link) in mv88e6xxx_port_sync_link()
195 err = ops->port_set_link(chip, port, link); in mv88e6xxx_port_sync_link()
200 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) in mv88e6185_port_sync_link() argument
202 const struct mv88e6xxx_ops *ops = chip->info->ops; in mv88e6185_port_sync_link()
206 if (mode == MLO_AN_INBAND) in mv88e6185_port_sync_link()
213 if (ops->port_set_link) in mv88e6185_port_sync_link()
214 err = ops->port_set_link(chip, port, link); in mv88e6185_port_sync_link()
220 int port, int speed, bool alt_bit, in mv88e6xxx_port_set_speed_duplex() argument
256 return -EOPNOTSUPP; in mv88e6xxx_port_set_speed_duplex()
271 return -EOPNOTSUPP; in mv88e6xxx_port_set_speed_duplex()
274 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6xxx_port_set_speed_duplex()
291 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6xxx_port_set_speed_duplex()
296 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); in mv88e6xxx_port_set_speed_duplex()
298 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); in mv88e6xxx_port_set_speed_duplex()
299 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, in mv88e6xxx_port_set_speed_duplex()
307 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, in mv88e6185_port_set_speed_duplex() argument
311 return -EOPNOTSUPP; in mv88e6185_port_set_speed_duplex()
313 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, in mv88e6185_port_set_speed_duplex()
318 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, in mv88e6250_port_set_speed_duplex() argument
322 return -EOPNOTSUPP; in mv88e6250_port_set_speed_duplex()
324 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, in mv88e6250_port_set_speed_duplex()
329 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, in mv88e6341_port_set_speed_duplex() argument
333 return -EOPNOTSUPP; in mv88e6341_port_set_speed_duplex()
335 if (speed == 200 && port != 0) in mv88e6341_port_set_speed_duplex()
336 return -EOPNOTSUPP; in mv88e6341_port_set_speed_duplex()
338 if (speed == 2500 && port < 5) in mv88e6341_port_set_speed_duplex()
339 return -EOPNOTSUPP; in mv88e6341_port_set_speed_duplex()
341 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true, in mv88e6341_port_set_speed_duplex()
346 int port) in mv88e6341_port_max_speed_mode() argument
348 if (port == 5) in mv88e6341_port_max_speed_mode()
355 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, in mv88e6352_port_set_speed_duplex() argument
359 return -EOPNOTSUPP; in mv88e6352_port_set_speed_duplex()
361 if (speed == 200 && port < 5) in mv88e6352_port_set_speed_duplex()
362 return -EOPNOTSUPP; in mv88e6352_port_set_speed_duplex()
364 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false, in mv88e6352_port_set_speed_duplex()
369 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, in mv88e6390_port_set_speed_duplex() argument
373 return -EOPNOTSUPP; in mv88e6390_port_set_speed_duplex()
375 if (speed == 200 && port != 0) in mv88e6390_port_set_speed_duplex()
376 return -EOPNOTSUPP; in mv88e6390_port_set_speed_duplex()
378 if (speed == 2500 && port < 9) in mv88e6390_port_set_speed_duplex()
379 return -EOPNOTSUPP; in mv88e6390_port_set_speed_duplex()
381 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, in mv88e6390_port_set_speed_duplex()
386 int port) in mv88e6390_port_max_speed_mode() argument
388 if (port == 9 || port == 10) in mv88e6390_port_max_speed_mode()
395 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, in mv88e6390x_port_set_speed_duplex() argument
398 if (speed == 200 && port != 0) in mv88e6390x_port_set_speed_duplex()
399 return -EOPNOTSUPP; in mv88e6390x_port_set_speed_duplex()
401 if (speed >= 2500 && port < 9) in mv88e6390x_port_set_speed_duplex()
402 return -EOPNOTSUPP; in mv88e6390x_port_set_speed_duplex()
404 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, in mv88e6390x_port_set_speed_duplex()
409 int port) in mv88e6390x_port_max_speed_mode() argument
411 if (port == 9 || port == 10) in mv88e6390x_port_max_speed_mode()
421 int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, in mv88e6393x_port_set_speed_duplex() argument
427 if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361 && in mv88e6393x_port_set_speed_duplex()
429 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
431 if (speed == 200 && port != 0) in mv88e6393x_port_set_speed_duplex()
432 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
434 if (speed >= 2500 && port > 0 && port < 9) in mv88e6393x_port_set_speed_duplex()
435 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
464 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
479 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
482 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6393x_port_set_speed_duplex()
495 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6393x_port_set_speed_duplex()
500 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); in mv88e6393x_port_set_speed_duplex()
502 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); in mv88e6393x_port_set_speed_duplex()
503 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, in mv88e6393x_port_set_speed_duplex()
511 int port) in mv88e6393x_port_max_speed_mode() argument
514 if (port != 0 && port != 9 && port != 10) in mv88e6393x_port_max_speed_mode()
517 if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361) in mv88e6393x_port_max_speed_mode()
523 static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_cmode() argument
524 phy_interface_t mode, bool force) in mv88e6xxx_port_set_cmode() argument
530 /* Default to a slow mode, so freeing up SERDES interfaces for in mv88e6xxx_port_set_cmode()
533 if (mode == PHY_INTERFACE_MODE_NA) in mv88e6xxx_port_set_cmode()
534 mode = PHY_INTERFACE_MODE_1000BASEX; in mv88e6xxx_port_set_cmode()
536 switch (mode) { in mv88e6xxx_port_set_cmode()
576 if (cmode == chip->ports[port].cmode && !force) in mv88e6xxx_port_set_cmode()
579 chip->ports[port].cmode = 0; in mv88e6xxx_port_set_cmode()
582 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6xxx_port_set_cmode()
589 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); in mv88e6xxx_port_set_cmode()
593 chip->ports[port].cmode = cmode; in mv88e6xxx_port_set_cmode()
599 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, in mv88e6390x_port_set_cmode() argument
600 phy_interface_t mode) in mv88e6390x_port_set_cmode() argument
602 if (port != 9 && port != 10) in mv88e6390x_port_set_cmode()
603 return -EOPNOTSUPP; in mv88e6390x_port_set_cmode()
605 return mv88e6xxx_port_set_cmode(chip, port, mode, false); in mv88e6390x_port_set_cmode()
608 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, in mv88e6390_port_set_cmode() argument
609 phy_interface_t mode) in mv88e6390_port_set_cmode() argument
611 if (port != 9 && port != 10) in mv88e6390_port_set_cmode()
612 return -EOPNOTSUPP; in mv88e6390_port_set_cmode()
614 switch (mode) { in mv88e6390_port_set_cmode()
620 return -EINVAL; in mv88e6390_port_set_cmode()
625 return mv88e6xxx_port_set_cmode(chip, port, mode, false); in mv88e6390_port_set_cmode()
628 int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, in mv88e6393x_port_set_cmode() argument
629 phy_interface_t mode) in mv88e6393x_port_set_cmode() argument
634 if (port != 0 && port != 9 && port != 10) in mv88e6393x_port_set_cmode()
635 return -EOPNOTSUPP; in mv88e6393x_port_set_cmode()
637 if (port == 9 || port == 10) { in mv88e6393x_port_set_cmode()
638 switch (mode) { in mv88e6393x_port_set_cmode()
644 return -EINVAL; in mv88e6393x_port_set_cmode()
651 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6393x_port_set_cmode()
657 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6393x_port_set_cmode()
661 return mv88e6xxx_port_set_cmode(chip, port, mode, false); in mv88e6393x_port_set_cmode()
665 int port) in mv88e6341_port_set_cmode_writable() argument
670 if (port != 5) in mv88e6341_port_set_cmode_writable()
671 return -EOPNOTSUPP; in mv88e6341_port_set_cmode_writable()
673 addr = chip->info->port_base_addr + port; in mv88e6341_port_set_cmode_writable()
689 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port, in mv88e6341_port_set_cmode() argument
690 phy_interface_t mode) in mv88e6341_port_set_cmode() argument
694 if (port != 5) in mv88e6341_port_set_cmode()
695 return -EOPNOTSUPP; in mv88e6341_port_set_cmode()
697 switch (mode) { in mv88e6341_port_set_cmode()
703 return -EINVAL; in mv88e6341_port_set_cmode()
708 err = mv88e6341_port_set_cmode_writable(chip, port); in mv88e6341_port_set_cmode()
712 return mv88e6xxx_port_set_cmode(chip, port, mode, true); in mv88e6341_port_set_cmode()
715 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) in mv88e6185_port_get_cmode() argument
720 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6185_port_get_cmode()
729 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) in mv88e6352_port_get_cmode() argument
734 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6352_port_get_cmode()
745 * Do not limit the period of time that this port can be paused for by
746 * the remote end or the period of time that this port can pause the
749 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, in mv88e6097_port_pause_limit() argument
752 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL, in mv88e6097_port_pause_limit()
756 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, in mv88e6390_port_pause_limit() argument
761 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, in mv88e6390_port_pause_limit()
767 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, in mv88e6390_port_pause_limit()
772 /* Offset 0x04: Port Control Register */
781 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state) in mv88e6xxx_port_set_state() argument
786 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6xxx_port_set_state()
807 return -EINVAL; in mv88e6xxx_port_set_state()
812 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6xxx_port_set_state()
816 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port, in mv88e6xxx_port_set_state()
822 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_egress_mode() argument
823 enum mv88e6xxx_egress_mode mode) in mv88e6xxx_port_set_egress_mode() argument
828 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6xxx_port_set_egress_mode()
834 switch (mode) { in mv88e6xxx_port_set_egress_mode()
848 return -EINVAL; in mv88e6xxx_port_set_egress_mode()
851 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6xxx_port_set_egress_mode()
854 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, in mv88e6085_port_set_frame_mode() argument
855 enum mv88e6xxx_frame_mode mode) in mv88e6085_port_set_frame_mode() argument
860 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6085_port_set_frame_mode()
866 switch (mode) { in mv88e6085_port_set_frame_mode()
874 return -EINVAL; in mv88e6085_port_set_frame_mode()
877 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6085_port_set_frame_mode()
880 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, in mv88e6351_port_set_frame_mode() argument
881 enum mv88e6xxx_frame_mode mode) in mv88e6351_port_set_frame_mode() argument
886 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6351_port_set_frame_mode()
892 switch (mode) { in mv88e6351_port_set_frame_mode()
906 return -EINVAL; in mv88e6351_port_set_frame_mode()
909 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6351_port_set_frame_mode()
913 int port, bool unicast) in mv88e6185_port_set_forward_unknown() argument
918 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6185_port_set_forward_unknown()
927 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6185_port_set_forward_unknown()
930 int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port, in mv88e6352_port_set_ucast_flood() argument
936 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6352_port_set_ucast_flood()
945 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6352_port_set_ucast_flood()
948 int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port, in mv88e6352_port_set_mcast_flood() argument
954 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6352_port_set_mcast_flood()
963 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6352_port_set_mcast_flood()
966 /* Offset 0x05: Port Control 1 */
968 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_message_port() argument
974 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); in mv88e6xxx_port_set_message_port()
983 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); in mv88e6xxx_port_set_message_port()
986 int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_trunk() argument
992 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); in mv88e6xxx_port_set_trunk()
1004 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); in mv88e6xxx_port_set_trunk()
1007 /* Offset 0x06: Port Based VLAN Map */
1009 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map) in mv88e6xxx_port_set_vlan_map() argument
1015 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); in mv88e6xxx_port_set_vlan_map()
1022 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); in mv88e6xxx_port_set_vlan_map()
1026 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map); in mv88e6xxx_port_set_vlan_map()
1031 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid) in mv88e6xxx_port_get_fid() argument
1033 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; in mv88e6xxx_port_get_fid()
1037 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ in mv88e6xxx_port_get_fid()
1038 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); in mv88e6xxx_port_get_fid()
1044 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ in mv88e6xxx_port_get_fid()
1046 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, in mv88e6xxx_port_get_fid()
1057 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid) in mv88e6xxx_port_set_fid() argument
1059 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; in mv88e6xxx_port_set_fid()
1064 return -EINVAL; in mv88e6xxx_port_set_fid()
1066 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ in mv88e6xxx_port_set_fid()
1067 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); in mv88e6xxx_port_set_fid()
1074 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); in mv88e6xxx_port_set_fid()
1078 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ in mv88e6xxx_port_set_fid()
1080 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, in mv88e6xxx_port_set_fid()
1088 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, in mv88e6xxx_port_set_fid()
1094 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid); in mv88e6xxx_port_set_fid()
1099 /* Offset 0x07: Default Port VLAN ID & Priority */
1101 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid) in mv88e6xxx_port_get_pvid() argument
1106 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, in mv88e6xxx_port_get_pvid()
1116 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid) in mv88e6xxx_port_set_pvid() argument
1121 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, in mv88e6xxx_port_set_pvid()
1129 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, in mv88e6xxx_port_set_pvid()
1134 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid); in mv88e6xxx_port_set_pvid()
1139 /* Offset 0x08: Port Control 2 Register */
1149 int port, bool multicast) in mv88e6185_port_set_default_forward() argument
1154 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6185_port_set_default_forward()
1163 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6185_port_set_default_forward()
1166 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, in mv88e6095_port_set_upstream_port() argument
1172 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6095_port_set_upstream_port()
1179 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6095_port_set_upstream_port()
1182 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_mirror() argument
1191 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6xxx_port_set_mirror()
1198 mirror_port = &chip->ports[port].mirror_ingress; in mv88e6xxx_port_set_mirror()
1202 mirror_port = &chip->ports[port].mirror_egress; in mv88e6xxx_port_set_mirror()
1205 return -EINVAL; in mv88e6xxx_port_set_mirror()
1212 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6xxx_port_set_mirror()
1219 int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_lock() argument
1225 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6xxx_port_set_lock()
1233 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6xxx_port_set_lock()
1237 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, ®); in mv88e6xxx_port_set_lock()
1245 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg); in mv88e6xxx_port_set_lock()
1248 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_8021q_mode() argument
1249 u16 mode) in mv88e6xxx_port_set_8021q_mode() argument
1254 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6xxx_port_set_8021q_mode()
1259 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; in mv88e6xxx_port_set_8021q_mode()
1261 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6xxx_port_set_8021q_mode()
1265 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port, in mv88e6xxx_port_set_8021q_mode()
1266 mv88e6xxx_port_8021q_mode_names[mode]); in mv88e6xxx_port_set_8021q_mode()
1271 int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_drop_untagged() argument
1277 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &old); in mv88e6xxx_port_drop_untagged()
1289 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new); in mv88e6xxx_port_drop_untagged()
1292 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map) in mv88e6xxx_port_set_map_da() argument
1297 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6xxx_port_set_map_da()
1306 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6xxx_port_set_map_da()
1309 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, in mv88e6165_port_set_jumbo_size() argument
1317 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6165_port_set_jumbo_size()
1330 return -ERANGE; in mv88e6165_port_set_jumbo_size()
1332 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6165_port_set_jumbo_size()
1335 /* Offset 0x09: Port Rate Control */
1337 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) in mv88e6095_port_egress_rate_limiting() argument
1339 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, in mv88e6095_port_egress_rate_limiting()
1343 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) in mv88e6097_port_egress_rate_limiting() argument
1345 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, in mv88e6097_port_egress_rate_limiting()
1349 /* Offset 0x0B: Port Association Vector */
1351 int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_assoc_vector() argument
1357 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, in mv88e6xxx_port_set_assoc_vector()
1366 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, in mv88e6xxx_port_set_assoc_vector()
1370 /* Offset 0x0C: Port ATU Control */
1372 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) in mv88e6xxx_port_disable_learn_limit() argument
1374 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0); in mv88e6xxx_port_disable_learn_limit()
1379 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port) in mv88e6xxx_port_disable_pri_override() argument
1381 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0); in mv88e6xxx_port_disable_pri_override()
1386 static int mv88e6393x_port_policy_read(struct mv88e6xxx_chip *chip, int port, in mv88e6393x_port_policy_read() argument
1392 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, in mv88e6393x_port_policy_read()
1397 err = mv88e6xxx_port_read(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, in mv88e6393x_port_policy_read()
1407 static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, int port, in mv88e6393x_port_policy_write() argument
1414 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, in mv88e6393x_port_policy_write()
1421 int err, port; in mv88e6393x_port_policy_write_all() local
1423 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { in mv88e6393x_port_policy_write_all()
1424 if (dsa_is_unused_port(chip->ds, port)) in mv88e6393x_port_policy_write_all()
1427 err = mv88e6393x_port_policy_write(chip, port, pointer, data); in mv88e6393x_port_policy_write_all()
1437 int port) in mv88e6393x_set_egress_port() argument
1445 err = mv88e6393x_port_policy_write_all(chip, ptr, port); in mv88e6393x_set_egress_port()
1451 err = mv88e6xxx_g2_write(chip, ptr, port); in mv88e6393x_set_egress_port()
1460 int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, in mv88e6393x_port_set_upstream_port() argument
1467 return mv88e6393x_port_policy_write(chip, port, ptr, data); in mv88e6393x_port_set_upstream_port()
1504 static int mv88e6393x_port_epc_wait_ready(struct mv88e6xxx_chip *chip, int port) in mv88e6393x_port_epc_wait_ready() argument
1508 return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0); in mv88e6393x_port_epc_wait_ready()
1511 /* Port Ether type for 6393X family */
1513 int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, in mv88e6393x_port_set_ether_type() argument
1519 err = mv88e6393x_port_epc_wait_ready(chip, port); in mv88e6393x_port_set_ether_type()
1523 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_DATA, etype); in mv88e6393x_port_set_ether_type()
1531 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val); in mv88e6393x_port_set_ether_type()
1534 /* Offset 0x0f: Port Ether type */
1536 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, in mv88e6351_port_set_ether_type() argument
1539 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype); in mv88e6351_port_set_ether_type()
1542 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
1543 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
1546 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port) in mv88e6095_port_tag_remap() argument
1550 /* Use a direct priority mapping for all IEEE tagged frames */ in mv88e6095_port_tag_remap()
1551 err = mv88e6xxx_port_write(chip, port, in mv88e6095_port_tag_remap()
1557 return mv88e6xxx_port_write(chip, port, in mv88e6095_port_tag_remap()
1563 int port, u16 table, u8 ptr, u16 data) in mv88e6xxx_port_ieeepmt_write() argument
1571 return mv88e6xxx_port_write(chip, port, in mv88e6xxx_port_ieeepmt_write()
1575 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port) in mv88e6390_port_tag_remap() argument
1582 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, in mv88e6390_port_tag_remap()
1588 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); in mv88e6390_port_tag_remap()
1593 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); in mv88e6390_port_tag_remap()
1598 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); in mv88e6390_port_tag_remap()
1609 mv88e6xxx_port_policy_mapping_get_pos(enum mv88e6xxx_policy_mapping mapping, in mv88e6xxx_port_policy_mapping_get_pos() argument
1613 switch (mapping) { in mv88e6xxx_port_policy_mapping_get_pos()
1647 return -EOPNOTSUPP; in mv88e6xxx_port_policy_mapping_get_pos()
1664 return -EOPNOTSUPP; in mv88e6xxx_port_policy_mapping_get_pos()
1670 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, in mv88e6352_port_set_policy() argument
1671 enum mv88e6xxx_policy_mapping mapping, in mv88e6352_port_set_policy() argument
1678 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, in mv88e6352_port_set_policy()
1683 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®); in mv88e6352_port_set_policy()
1690 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg); in mv88e6352_port_set_policy()
1693 int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port, in mv88e6393x_port_set_policy() argument
1694 enum mv88e6xxx_policy_mapping mapping, in mv88e6393x_port_set_policy() argument
1703 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, in mv88e6393x_port_set_policy()
1708 /* The 16-bit Port Policy CTL register from older chips is on 6393x in mv88e6393x_port_set_policy()
1709 * changed to Port Policy MGMT CTL, which can access more data, but in mv88e6393x_port_set_policy()
1710 * indirectly. The original 16-bit value is divided into two 8-bit in mv88e6393x_port_set_policy()
1718 err = mv88e6393x_port_policy_read(chip, port, ptr, ®); in mv88e6393x_port_set_policy()
1725 return mv88e6393x_port_policy_write(chip, port, ptr, reg); in mv88e6393x_port_set_policy()