Lines Matching +full:mode +full:- +full:reg
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
21 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_read() argument
24 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_read()
26 return mv88e6xxx_read(chip, addr, reg, val); in mv88e6xxx_port_read()
29 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_wait_bit() argument
32 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_wait_bit()
34 return mv88e6xxx_wait_bit(chip, addr, reg, bit, val); in mv88e6xxx_port_wait_bit()
37 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_write() argument
40 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_write()
42 return mv88e6xxx_write(chip, addr, reg, val); in mv88e6xxx_port_write()
53 u16 reg; in mv88e6185_port_set_pause() local
56 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6185_port_set_pause()
61 reg |= MV88E6XXX_PORT_STS_MY_PAUSE; in mv88e6185_port_set_pause()
63 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE; in mv88e6185_port_set_pause()
65 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); in mv88e6185_port_set_pause()
78 phy_interface_t mode) in mv88e6xxx_port_set_rgmii_delay() argument
80 u16 reg; in mv88e6xxx_port_set_rgmii_delay() local
83 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6xxx_port_set_rgmii_delay()
87 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | in mv88e6xxx_port_set_rgmii_delay()
90 switch (mode) { in mv88e6xxx_port_set_rgmii_delay()
92 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK; in mv88e6xxx_port_set_rgmii_delay()
95 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; in mv88e6xxx_port_set_rgmii_delay()
98 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | in mv88e6xxx_port_set_rgmii_delay()
107 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6xxx_port_set_rgmii_delay()
111 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port, in mv88e6xxx_port_set_rgmii_delay()
112 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no", in mv88e6xxx_port_set_rgmii_delay()
113 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no"); in mv88e6xxx_port_set_rgmii_delay()
119 phy_interface_t mode) in mv88e6352_port_set_rgmii_delay() argument
122 return -EOPNOTSUPP; in mv88e6352_port_set_rgmii_delay()
124 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); in mv88e6352_port_set_rgmii_delay()
128 phy_interface_t mode) in mv88e6390_port_set_rgmii_delay() argument
131 return -EOPNOTSUPP; in mv88e6390_port_set_rgmii_delay()
133 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); in mv88e6390_port_set_rgmii_delay()
137 phy_interface_t mode) in mv88e6320_port_set_rgmii_delay() argument
140 return -EOPNOTSUPP; in mv88e6320_port_set_rgmii_delay()
142 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); in mv88e6320_port_set_rgmii_delay()
147 u16 reg; in mv88e6xxx_port_set_link() local
150 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6xxx_port_set_link()
154 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | in mv88e6xxx_port_set_link()
159 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK; in mv88e6xxx_port_set_link()
162 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | in mv88e6xxx_port_set_link()
169 return -EINVAL; in mv88e6xxx_port_set_link()
172 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6xxx_port_set_link()
176 dev_dbg(chip->dev, "p%d: %s link %s\n", port, in mv88e6xxx_port_set_link()
177 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce", in mv88e6xxx_port_set_link()
178 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down"); in mv88e6xxx_port_set_link()
183 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) in mv88e6xxx_port_sync_link() argument
185 const struct mv88e6xxx_ops *ops = chip->info->ops; in mv88e6xxx_port_sync_link()
194 if (ops->port_set_link) in mv88e6xxx_port_sync_link()
195 err = ops->port_set_link(chip, port, link); in mv88e6xxx_port_sync_link()
200 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) in mv88e6185_port_sync_link() argument
202 const struct mv88e6xxx_ops *ops = chip->info->ops; in mv88e6185_port_sync_link()
206 if (mode == MLO_AN_INBAND) in mv88e6185_port_sync_link()
213 if (ops->port_set_link) in mv88e6185_port_sync_link()
214 err = ops->port_set_link(chip, port, link); in mv88e6185_port_sync_link()
223 u16 reg, ctrl; in mv88e6xxx_port_set_speed_duplex() local
256 return -EOPNOTSUPP; in mv88e6xxx_port_set_speed_duplex()
271 return -EOPNOTSUPP; in mv88e6xxx_port_set_speed_duplex()
274 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6xxx_port_set_speed_duplex()
278 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | in mv88e6xxx_port_set_speed_duplex()
283 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED; in mv88e6xxx_port_set_speed_duplex()
285 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED; in mv88e6xxx_port_set_speed_duplex()
289 reg |= ctrl; in mv88e6xxx_port_set_speed_duplex()
291 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6xxx_port_set_speed_duplex()
296 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); in mv88e6xxx_port_set_speed_duplex()
298 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); in mv88e6xxx_port_set_speed_duplex()
299 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, in mv88e6xxx_port_set_speed_duplex()
300 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", in mv88e6xxx_port_set_speed_duplex()
301 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); in mv88e6xxx_port_set_speed_duplex()
311 return -EOPNOTSUPP; in mv88e6185_port_set_speed_duplex()
322 return -EOPNOTSUPP; in mv88e6250_port_set_speed_duplex()
333 return -EOPNOTSUPP; in mv88e6341_port_set_speed_duplex()
336 return -EOPNOTSUPP; in mv88e6341_port_set_speed_duplex()
339 return -EOPNOTSUPP; in mv88e6341_port_set_speed_duplex()
359 return -EOPNOTSUPP; in mv88e6352_port_set_speed_duplex()
362 return -EOPNOTSUPP; in mv88e6352_port_set_speed_duplex()
373 return -EOPNOTSUPP; in mv88e6390_port_set_speed_duplex()
376 return -EOPNOTSUPP; in mv88e6390_port_set_speed_duplex()
379 return -EOPNOTSUPP; in mv88e6390_port_set_speed_duplex()
399 return -EOPNOTSUPP; in mv88e6390x_port_set_speed_duplex()
402 return -EOPNOTSUPP; in mv88e6390x_port_set_speed_duplex()
424 u16 reg, ctrl; in mv88e6393x_port_set_speed_duplex() local
427 if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361 && in mv88e6393x_port_set_speed_duplex()
429 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
432 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
435 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
464 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
479 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
482 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6393x_port_set_speed_duplex()
486 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | in mv88e6393x_port_set_speed_duplex()
491 reg |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; in mv88e6393x_port_set_speed_duplex()
493 reg |= ctrl; in mv88e6393x_port_set_speed_duplex()
495 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6393x_port_set_speed_duplex()
500 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); in mv88e6393x_port_set_speed_duplex()
502 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); in mv88e6393x_port_set_speed_duplex()
503 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, in mv88e6393x_port_set_speed_duplex()
504 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", in mv88e6393x_port_set_speed_duplex()
505 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); in mv88e6393x_port_set_speed_duplex()
517 if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361) in mv88e6393x_port_max_speed_mode()
524 phy_interface_t mode, bool force) in mv88e6xxx_port_set_cmode() argument
527 u16 reg; in mv88e6xxx_port_set_cmode() local
530 /* Default to a slow mode, so freeing up SERDES interfaces for in mv88e6xxx_port_set_cmode()
533 if (mode == PHY_INTERFACE_MODE_NA) in mv88e6xxx_port_set_cmode()
534 mode = PHY_INTERFACE_MODE_1000BASEX; in mv88e6xxx_port_set_cmode()
536 switch (mode) { in mv88e6xxx_port_set_cmode()
576 if (cmode == chip->ports[port].cmode && !force) in mv88e6xxx_port_set_cmode()
579 chip->ports[port].cmode = 0; in mv88e6xxx_port_set_cmode()
582 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6xxx_port_set_cmode()
586 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK; in mv88e6xxx_port_set_cmode()
587 reg |= cmode; in mv88e6xxx_port_set_cmode()
589 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); in mv88e6xxx_port_set_cmode()
593 chip->ports[port].cmode = cmode; in mv88e6xxx_port_set_cmode()
600 phy_interface_t mode) in mv88e6390x_port_set_cmode() argument
603 return -EOPNOTSUPP; in mv88e6390x_port_set_cmode()
605 return mv88e6xxx_port_set_cmode(chip, port, mode, false); in mv88e6390x_port_set_cmode()
609 phy_interface_t mode) in mv88e6390_port_set_cmode() argument
612 return -EOPNOTSUPP; in mv88e6390_port_set_cmode()
614 switch (mode) { in mv88e6390_port_set_cmode()
620 return -EINVAL; in mv88e6390_port_set_cmode()
625 return mv88e6xxx_port_set_cmode(chip, port, mode, false); in mv88e6390_port_set_cmode()
629 phy_interface_t mode) in mv88e6393x_port_set_cmode() argument
632 u16 reg; in mv88e6393x_port_set_cmode() local
635 return -EOPNOTSUPP; in mv88e6393x_port_set_cmode()
638 switch (mode) { in mv88e6393x_port_set_cmode()
644 return -EINVAL; in mv88e6393x_port_set_cmode()
651 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6393x_port_set_cmode()
655 reg &= ~MV88E6XXX_PORT_MAC_CTL_EEE; in mv88e6393x_port_set_cmode()
656 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_EEE; in mv88e6393x_port_set_cmode()
657 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6393x_port_set_cmode()
661 return mv88e6xxx_port_set_cmode(chip, port, mode, false); in mv88e6393x_port_set_cmode()
668 u16 reg, bits; in mv88e6341_port_set_cmode_writable() local
671 return -EOPNOTSUPP; in mv88e6341_port_set_cmode_writable()
673 addr = chip->info->port_base_addr + port; in mv88e6341_port_set_cmode_writable()
675 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®); in mv88e6341_port_set_cmode_writable()
682 if ((reg & bits) == bits) in mv88e6341_port_set_cmode_writable()
685 reg |= bits; in mv88e6341_port_set_cmode_writable()
686 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg); in mv88e6341_port_set_cmode_writable()
690 phy_interface_t mode) in mv88e6341_port_set_cmode() argument
695 return -EOPNOTSUPP; in mv88e6341_port_set_cmode()
697 switch (mode) { in mv88e6341_port_set_cmode()
703 return -EINVAL; in mv88e6341_port_set_cmode()
712 return mv88e6xxx_port_set_cmode(chip, port, mode, true); in mv88e6341_port_set_cmode()
718 u16 reg; in mv88e6185_port_get_cmode() local
720 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6185_port_get_cmode()
724 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK; in mv88e6185_port_get_cmode()
732 u16 reg; in mv88e6352_port_get_cmode() local
734 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6352_port_get_cmode()
738 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK; in mv88e6352_port_get_cmode()
783 u16 reg; in mv88e6xxx_port_set_state() local
786 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6xxx_port_set_state()
790 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK; in mv88e6xxx_port_set_state()
807 return -EINVAL; in mv88e6xxx_port_set_state()
810 reg |= state; in mv88e6xxx_port_set_state()
812 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6xxx_port_set_state()
816 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port, in mv88e6xxx_port_set_state()
823 enum mv88e6xxx_egress_mode mode) in mv88e6xxx_port_set_egress_mode() argument
826 u16 reg; in mv88e6xxx_port_set_egress_mode() local
828 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6xxx_port_set_egress_mode()
832 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK; in mv88e6xxx_port_set_egress_mode()
834 switch (mode) { in mv88e6xxx_port_set_egress_mode()
836 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED; in mv88e6xxx_port_set_egress_mode()
839 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED; in mv88e6xxx_port_set_egress_mode()
842 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED; in mv88e6xxx_port_set_egress_mode()
845 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA; in mv88e6xxx_port_set_egress_mode()
848 return -EINVAL; in mv88e6xxx_port_set_egress_mode()
851 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6xxx_port_set_egress_mode()
855 enum mv88e6xxx_frame_mode mode) in mv88e6085_port_set_frame_mode() argument
858 u16 reg; in mv88e6085_port_set_frame_mode() local
860 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6085_port_set_frame_mode()
864 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; in mv88e6085_port_set_frame_mode()
866 switch (mode) { in mv88e6085_port_set_frame_mode()
868 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; in mv88e6085_port_set_frame_mode()
871 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; in mv88e6085_port_set_frame_mode()
874 return -EINVAL; in mv88e6085_port_set_frame_mode()
877 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6085_port_set_frame_mode()
881 enum mv88e6xxx_frame_mode mode) in mv88e6351_port_set_frame_mode() argument
884 u16 reg; in mv88e6351_port_set_frame_mode() local
886 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6351_port_set_frame_mode()
890 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; in mv88e6351_port_set_frame_mode()
892 switch (mode) { in mv88e6351_port_set_frame_mode()
894 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; in mv88e6351_port_set_frame_mode()
897 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; in mv88e6351_port_set_frame_mode()
900 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER; in mv88e6351_port_set_frame_mode()
903 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA; in mv88e6351_port_set_frame_mode()
906 return -EINVAL; in mv88e6351_port_set_frame_mode()
909 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6351_port_set_frame_mode()
916 u16 reg; in mv88e6185_port_set_forward_unknown() local
918 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6185_port_set_forward_unknown()
923 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; in mv88e6185_port_set_forward_unknown()
925 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; in mv88e6185_port_set_forward_unknown()
927 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6185_port_set_forward_unknown()
934 u16 reg; in mv88e6352_port_set_ucast_flood() local
936 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6352_port_set_ucast_flood()
941 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; in mv88e6352_port_set_ucast_flood()
943 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; in mv88e6352_port_set_ucast_flood()
945 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6352_port_set_ucast_flood()
952 u16 reg; in mv88e6352_port_set_mcast_flood() local
954 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6352_port_set_mcast_flood()
959 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; in mv88e6352_port_set_mcast_flood()
961 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; in mv88e6352_port_set_mcast_flood()
963 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6352_port_set_mcast_flood()
1012 u16 reg; in mv88e6xxx_port_set_vlan_map() local
1015 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); in mv88e6xxx_port_set_vlan_map()
1019 reg &= ~mask; in mv88e6xxx_port_set_vlan_map()
1020 reg |= map & mask; in mv88e6xxx_port_set_vlan_map()
1022 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); in mv88e6xxx_port_set_vlan_map()
1026 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map); in mv88e6xxx_port_set_vlan_map()
1033 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; in mv88e6xxx_port_get_fid()
1034 u16 reg; in mv88e6xxx_port_get_fid() local
1037 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ in mv88e6xxx_port_get_fid()
1038 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); in mv88e6xxx_port_get_fid()
1042 *fid = (reg & 0xf000) >> 12; in mv88e6xxx_port_get_fid()
1044 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ in mv88e6xxx_port_get_fid()
1047 ®); in mv88e6xxx_port_get_fid()
1051 *fid |= (reg & upper_mask) << 4; in mv88e6xxx_port_get_fid()
1059 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; in mv88e6xxx_port_set_fid()
1060 u16 reg; in mv88e6xxx_port_set_fid() local
1064 return -EINVAL; in mv88e6xxx_port_set_fid()
1066 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ in mv88e6xxx_port_set_fid()
1067 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); in mv88e6xxx_port_set_fid()
1071 reg &= 0x0fff; in mv88e6xxx_port_set_fid()
1072 reg |= (fid & 0x000f) << 12; in mv88e6xxx_port_set_fid()
1074 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); in mv88e6xxx_port_set_fid()
1078 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ in mv88e6xxx_port_set_fid()
1081 ®); in mv88e6xxx_port_set_fid()
1085 reg &= ~upper_mask; in mv88e6xxx_port_set_fid()
1086 reg |= (fid >> 4) & upper_mask; in mv88e6xxx_port_set_fid()
1089 reg); in mv88e6xxx_port_set_fid()
1094 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid); in mv88e6xxx_port_set_fid()
1103 u16 reg; in mv88e6xxx_port_get_pvid() local
1107 ®); in mv88e6xxx_port_get_pvid()
1111 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; in mv88e6xxx_port_get_pvid()
1118 u16 reg; in mv88e6xxx_port_set_pvid() local
1122 ®); in mv88e6xxx_port_set_pvid()
1126 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK; in mv88e6xxx_port_set_pvid()
1127 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; in mv88e6xxx_port_set_pvid()
1130 reg); in mv88e6xxx_port_set_pvid()
1134 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid); in mv88e6xxx_port_set_pvid()
1152 u16 reg; in mv88e6185_port_set_default_forward() local
1154 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6185_port_set_default_forward()
1159 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; in mv88e6185_port_set_default_forward()
1161 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; in mv88e6185_port_set_default_forward()
1163 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6185_port_set_default_forward()
1170 u16 reg; in mv88e6095_port_set_upstream_port() local
1172 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6095_port_set_upstream_port()
1176 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK; in mv88e6095_port_set_upstream_port()
1177 reg |= upstream_port; in mv88e6095_port_set_upstream_port()
1179 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6095_port_set_upstream_port()
1187 u16 reg; in mv88e6xxx_port_set_mirror() local
1191 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6xxx_port_set_mirror()
1198 mirror_port = &chip->ports[port].mirror_ingress; in mv88e6xxx_port_set_mirror()
1202 mirror_port = &chip->ports[port].mirror_egress; in mv88e6xxx_port_set_mirror()
1205 return -EINVAL; in mv88e6xxx_port_set_mirror()
1208 reg &= ~bit; in mv88e6xxx_port_set_mirror()
1210 reg |= bit; in mv88e6xxx_port_set_mirror()
1212 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6xxx_port_set_mirror()
1222 u16 reg; in mv88e6xxx_port_set_lock() local
1225 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6xxx_port_set_lock()
1229 reg &= ~MV88E6XXX_PORT_CTL0_SA_FILT_MASK; in mv88e6xxx_port_set_lock()
1231 reg |= MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK; in mv88e6xxx_port_set_lock()
1233 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6xxx_port_set_lock()
1237 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, ®); in mv88e6xxx_port_set_lock()
1241 reg &= ~MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT; in mv88e6xxx_port_set_lock()
1243 reg |= MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT; in mv88e6xxx_port_set_lock()
1245 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg); in mv88e6xxx_port_set_lock()
1249 u16 mode) in mv88e6xxx_port_set_8021q_mode() argument
1251 u16 reg; in mv88e6xxx_port_set_8021q_mode() local
1254 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6xxx_port_set_8021q_mode()
1258 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; in mv88e6xxx_port_set_8021q_mode()
1259 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; in mv88e6xxx_port_set_8021q_mode()
1261 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6xxx_port_set_8021q_mode()
1265 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port, in mv88e6xxx_port_set_8021q_mode()
1266 mv88e6xxx_port_8021q_mode_names[mode]); in mv88e6xxx_port_set_8021q_mode()
1294 u16 reg; in mv88e6xxx_port_set_map_da() local
1297 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6xxx_port_set_map_da()
1302 reg |= MV88E6XXX_PORT_CTL2_MAP_DA; in mv88e6xxx_port_set_map_da()
1304 reg &= ~MV88E6XXX_PORT_CTL2_MAP_DA; in mv88e6xxx_port_set_map_da()
1306 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6xxx_port_set_map_da()
1312 u16 reg; in mv88e6165_port_set_jumbo_size() local
1317 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6165_port_set_jumbo_size()
1321 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK; in mv88e6165_port_set_jumbo_size()
1324 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522; in mv88e6165_port_set_jumbo_size()
1326 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048; in mv88e6165_port_set_jumbo_size()
1328 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240; in mv88e6165_port_set_jumbo_size()
1330 return -ERANGE; in mv88e6165_port_set_jumbo_size()
1332 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6165_port_set_jumbo_size()
1354 u16 reg, mask; in mv88e6xxx_port_set_assoc_vector() local
1358 ®); in mv88e6xxx_port_set_assoc_vector()
1363 reg &= ~mask; in mv88e6xxx_port_set_assoc_vector()
1364 reg |= pav & mask; in mv88e6xxx_port_set_assoc_vector()
1367 reg); in mv88e6xxx_port_set_assoc_vector()
1389 u16 reg; in mv88e6393x_port_policy_read() local
1398 ®); in mv88e6393x_port_policy_read()
1402 *data = reg; in mv88e6393x_port_policy_read()
1410 u16 reg; in mv88e6393x_port_policy_write() local
1412 reg = MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE | pointer | data; in mv88e6393x_port_policy_write()
1415 reg); in mv88e6393x_port_policy_write()
1424 if (dsa_is_unused_port(chip->ds, port)) in mv88e6393x_port_policy_write_all()
1542 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
1543 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
1565 u16 reg; in mv88e6xxx_port_ieeepmt_write() local
1567 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table | in mv88e6xxx_port_ieeepmt_write()
1572 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg); in mv88e6xxx_port_ieeepmt_write()
1647 return -EOPNOTSUPP; in mv88e6xxx_port_policy_mapping_get_pos()
1664 return -EOPNOTSUPP; in mv88e6xxx_port_policy_mapping_get_pos()
1674 u16 reg, mask, val; in mv88e6352_port_set_policy() local
1683 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®); in mv88e6352_port_set_policy()
1687 reg &= ~mask; in mv88e6352_port_set_policy()
1688 reg |= (val << shift) & mask; in mv88e6352_port_set_policy()
1690 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg); in mv88e6352_port_set_policy()
1701 u8 reg; in mv88e6393x_port_set_policy() local
1708 /* The 16-bit Port Policy CTL register from older chips is on 6393x in mv88e6393x_port_set_policy()
1710 * indirectly. The original 16-bit value is divided into two 8-bit in mv88e6393x_port_set_policy()
1718 err = mv88e6393x_port_policy_read(chip, port, ptr, ®); in mv88e6393x_port_set_policy()
1722 reg &= ~mask; in mv88e6393x_port_set_policy()
1723 reg |= (val << shift) & mask; in mv88e6393x_port_set_policy()
1725 return mv88e6393x_port_policy_write(chip, port, ptr, reg); in mv88e6393x_port_set_policy()