1 // SPDX-License-Identifier: GPL-2.0-or-later
35 	err = mdiodev_c45_read(&mpcs->mdio, MDIO_MMD_PHYXS, regnum);  in mv88e639x_read()
46 	return mdiodev_c45_write(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, val);  in mv88e639x_write()
52 	return mdiodev_c45_modify(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, mask,  in mv88e639x_modify()
59 	return mdiodev_c45_modify_changed(&mpcs->mdio, MDIO_MMD_PHYXS, regnum,  in mv88e639x_modify_changed()
73 	mpcs->mdio.dev.parent = dev;  in mv88e639x_pcs_alloc()
74 	mpcs->mdio.bus = bus;  in mv88e639x_pcs_alloc()
75 	mpcs->mdio.addr = addr;  in mv88e639x_pcs_alloc()
77 	snprintf(mpcs->name, sizeof(mpcs->name),  in mv88e639x_pcs_alloc()
78 		 "mv88e6xxx-%s-serdes-%d", dev_name(dev), port);  in mv88e639x_pcs_alloc()
88 	handler = READ_ONCE(mpcs->handle_irq);  in mv88e639x_pcs_handle_irq()
103 		mpcs->sgmii_pcs.poll = true;  in mv88e639x_pcs_setup_irq()
104 		mpcs->xg_pcs.poll = true;  in mv88e639x_pcs_setup_irq()
108 	mpcs->irq = irq;  in mv88e639x_pcs_setup_irq()
111 				    IRQF_ONESHOT, mpcs->name, mpcs);  in mv88e639x_pcs_setup_irq()
116 	struct mv88e639x_pcs *mpcs = chip->ports[port].pcs_private;  in mv88e639x_pcs_teardown()
121 	if (mpcs->irq)  in mv88e639x_pcs_teardown()
122 		free_irq(mpcs->irq, mpcs);  in mv88e639x_pcs_teardown()
126 	chip->ports[port].pcs_private = NULL;  in mv88e639x_pcs_teardown()
145 		phylink_pcs_change(&mpcs->sgmii_pcs,  in mv88e639x_sgmii_handle_irq()
155 					   bool enable)  in mv88e639x_sgmii_pcs_control_irq()  argument
159 	if (enable)  in mv88e639x_sgmii_pcs_control_irq()
169 					   bool enable)  in mv88e639x_sgmii_pcs_control_pwr()  argument
173 	if (enable) {  in mv88e639x_sgmii_pcs_control_pwr()
187 	/* power enable done in post_config */  in mv88e639x_sgmii_pcs_enable()
188 	mpcs->handle_irq = mv88e639x_sgmii_handle_irq;  in mv88e639x_sgmii_pcs_enable()
190 	return mv88e639x_sgmii_pcs_control_irq(mpcs, !!mpcs->irq);  in mv88e639x_sgmii_pcs_enable()
224 		err = mdiobus_c45_write(mpcs->mdio.bus, lanes[i],  in mv88e6390_erratum_3_14()
230 		err = mdiobus_c45_write(mpcs->mdio.bus, lanes[i],  in mv88e6390_erratum_3_14()
248 	if (mpcs->erratum_3_14) {  in mv88e639x_sgmii_pcs_post_config()
251 			dev_err(mpcs->mdio.dev.parent,  in mv88e639x_sgmii_pcs_post_config()
263 	u16 bmsr, lpa, status;  in mv88e639x_sgmii_pcs_get_state()  local
268 		dev_err(mpcs->mdio.dev.parent,  in mv88e639x_sgmii_pcs_get_state()
271 		state->link = false;  in mv88e639x_sgmii_pcs_get_state()
275 	err = mv88e639x_read(mpcs, MV88E6390_SGMII_LPA, &lpa);  in mv88e639x_sgmii_pcs_get_state()
277 		dev_err(mpcs->mdio.dev.parent,  in mv88e639x_sgmii_pcs_get_state()
279 			"LPA", ERR_PTR(err));  in mv88e639x_sgmii_pcs_get_state()
280 		state->link = false;  in mv88e639x_sgmii_pcs_get_state()
286 		dev_err(mpcs->mdio.dev.parent,  in mv88e639x_sgmii_pcs_get_state()
289 		state->link = false;  in mv88e639x_sgmii_pcs_get_state()
293 	mv88e6xxx_pcs_decode_state(mpcs->mdio.dev.parent, bmsr, lpa, status,  in mv88e639x_sgmii_pcs_get_state()
312 	mpcs->interface = interface;  in mv88e639x_sgmii_pcs_config()
363 		dev_err(mpcs->mdio.dev.parent,  in mv88e639x_sgmii_pcs_link_up()
404 	state->link = false;  in mv88e639x_xg_pcs_get_state()
408 		dev_err(mpcs->mdio.dev.parent,  in mv88e639x_xg_pcs_get_state()
414 	state->link = !!(status & MDIO_STAT1_LSTATUS);  in mv88e639x_xg_pcs_get_state()
415 	if (state->link) {  in mv88e639x_xg_pcs_get_state()
416 		switch (state->interface) {  in mv88e639x_xg_pcs_get_state()
418 			state->speed = SPEED_5000;  in mv88e639x_xg_pcs_get_state()
424 			state->speed = SPEED_10000;  in mv88e639x_xg_pcs_get_state()
428 			state->link = false;  in mv88e639x_xg_pcs_get_state()
432 		state->duplex = DUPLEX_FULL;  in mv88e639x_xg_pcs_get_state()
451 	mpcs = chip->ports[port].pcs_private;  in mv88e639x_pcs_select()
459 		return &mpcs->sgmii_pcs;  in mv88e639x_pcs_select()
462 		if (!mpcs->supports_5g)  in mv88e639x_pcs_select()
469 		return &mpcs->xg_pcs;  in mv88e639x_pcs_select()
489 		phylink_pcs_change(&mpcs->xg_pcs,  in mv88e6390_xg_handle_irq()
498 static int mv88e6390_xg_control_irq(struct mv88e639x_pcs *mpcs, bool enable)  in mv88e6390_xg_control_irq()  argument
502 	if (enable)  in mv88e6390_xg_control_irq()
519 	mpcs->handle_irq = mv88e6390_xg_handle_irq;  in mv88e6390_xg_pcs_enable()
521 	return mv88e6390_xg_control_irq(mpcs, !!mpcs->irq);  in mv88e6390_xg_pcs_enable()
558 	dev = chip->dev;  in mv88e6390_pcs_init()
562 		return -ENOMEM;  in mv88e6390_pcs_init()
564 	mpcs->sgmii_pcs.ops = &mv88e639x_sgmii_pcs_ops;  in mv88e6390_pcs_init()
565 	mpcs->sgmii_pcs.neg_mode = true;  in mv88e6390_pcs_init()
566 	mpcs->xg_pcs.ops = &mv88e6390_xg_pcs_ops;  in mv88e6390_pcs_init()
567 	mpcs->xg_pcs.neg_mode = true;  in mv88e6390_pcs_init()
569 	if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6190X ||  in mv88e6390_pcs_init()
570 	    chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6390X)  in mv88e6390_pcs_init()
571 		mpcs->erratum_3_14 = true;  in mv88e6390_pcs_init()
578 	/* This is to enable gathering the statistics. Maybe this  in mv88e6390_pcs_init()
585 	chip->ports[port].pcs_private = mpcs;  in mv88e6390_pcs_init()
602 static int mv88e6393x_power_lane(struct mv88e639x_pcs *mpcs, bool enable)  in mv88e6393x_power_lane()  argument
608 				enable ? 0 : val);  in mv88e6393x_power_lane()
643  * When a SERDES port is operating in 1000BASE-X or SGMII mode link may not
691 		err = mdiodev_c45_modify(&mpcs->mdio, fixes[i].dev,  in mv88e6393x_erratum_5_2()
701 /* Inband AN is broken on Amethyst in 2500base-x mode when set by standard
703  * We can get around this by configuring the PCS mode to 1000base-x and then
707  * It seem that when we do this configuration to 2500base-x mode (by changing
708  * PCS mode to 1000base-x and frequency to 3.125 GHz from 1.25 GHz) and then
709  * configure to sgmii or 1000base-x, the device thinks that it already has
712  * To avoid this, change PCS mode back to 2500base-x when disabling SerDes from
713  * 2500base-x mode.
735 	return mdiodev_c45_write(&mpcs->mdio, MDIO_MMD_VEND1, 0x8000, 0x58);  in mv88e6393x_fix_2500basex_an()
740 					       bool enable)  in mv88e6393x_sgmii_apply_2500basex_an()  argument
747 	err = mv88e6393x_fix_2500basex_an(mpcs, enable);  in mv88e6393x_sgmii_apply_2500basex_an()
749 		dev_err(mpcs->mdio.dev.parent,  in mv88e6393x_sgmii_apply_2500basex_an()
751 			enable ? "enable" : "disable", ERR_PTR(err));  in mv88e6393x_sgmii_apply_2500basex_an()
762 	mv88e6393x_sgmii_apply_2500basex_an(mpcs, mpcs->interface, false);  in mv88e6393x_sgmii_pcs_disable()
772 	mv88e6393x_sgmii_apply_2500basex_an(mpcs, mpcs->interface, false);  in mv88e6393x_sgmii_pcs_pre_config()
824 		phylink_pcs_change(&mpcs->xg_pcs, !link_down);  in mv88e6393x_xg_handle_irq()
832 static int mv88e6393x_xg_control_irq(struct mv88e639x_pcs *mpcs, bool enable)  in mv88e6393x_xg_control_irq()  argument
836 	if (enable)  in mv88e6393x_xg_control_irq()
847 	mpcs->handle_irq = mv88e6393x_xg_handle_irq;  in mv88e6393x_xg_pcs_enable()
849 	return mv88e6393x_xg_control_irq(mpcs, !!mpcs->irq);  in mv88e6393x_xg_pcs_enable()
898 	if (state->interface != PHY_INTERFACE_MODE_USXGMII)  in mv88e6393x_xg_pcs_get_state()
901 	state->link = false;  in mv88e6393x_xg_pcs_get_state()
906 		dev_err(mpcs->mdio.dev.parent,  in mv88e6393x_xg_pcs_get_state()
911 	state->link = !!(status & MDIO_USXGMII_LINK);  in mv88e6393x_xg_pcs_get_state()
912 	state->an_complete = state->link;  in mv88e6393x_xg_pcs_get_state()
937 	dev = chip->dev;  in mv88e6393x_pcs_init()
941 		return -ENOMEM;  in mv88e6393x_pcs_init()
943 	mpcs->sgmii_pcs.ops = &mv88e6393x_sgmii_pcs_ops;  in mv88e6393x_pcs_init()
944 	mpcs->sgmii_pcs.neg_mode = true;  in mv88e6393x_pcs_init()
945 	mpcs->xg_pcs.ops = &mv88e6393x_xg_pcs_ops;  in mv88e6393x_pcs_init()
946 	mpcs->xg_pcs.neg_mode = true;  in mv88e6393x_pcs_init()
947 	mpcs->supports_5g = true;  in mv88e6393x_pcs_init()
957 	chip->ports[port].pcs_private = mpcs;  in mv88e6393x_pcs_init()