1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * Marvell 88E6xxx Ethernet switch single-chip definition
28 /* PVT limits for 4-bit port and 5-bit switch */
110  * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level
115  *                               empirical data shows that this mode
149 	 * ports 2-4 are not routet to pins.
152 	/* Multi-chip Addressing Mode.
154 	 * when it is non-zero, and use indirect access to internal registers.
157 	/* Dual-chip Addressing Mode
175 	 * port 0, 1 means internal PHYs range starts at port 1, etc
225 	/* Port index */
263 	enum mv88e6xxx_policy_mapping mapping;  member
267 	int port;  member
278 	int port;  member
355 	/* Handles automatic disabling and re-enabling of the PHY
426 	/* Per-port timestamping resources. */
429 	/* Array of port structures. */
462 	int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
504 	int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
505 				    phy_interface_t mode);
509 #define LINK_UNFORCED		-2
511 	/* Port's MAC link state
515 	int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
517 	/* Synchronise the port link state with that of the SERDES
519 	int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
525 	int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
528 #define SPEED_UNFORCED		-2
529 #define DUPLEX_UNFORCED		-2
531 	/* Port's MAC speed (in Mbps) and MAC duplex mode
539 	int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
542 	/* What interface mode should be used for maximum speed? */
544 					       int port);
546 	int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
548 	int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
549 			       enum mv88e6xxx_policy_mapping mapping,
552 	int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
553 				   enum mv88e6xxx_frame_mode mode);
554 	int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port,
556 	int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port,
558 	int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
560 	int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
563 	int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
564 	int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
566 	int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
567 	int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
568 	int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
570 	/* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
573 	int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
574 			      phy_interface_t mode);
575 	int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
577 	/* Some devices have a per port register indicating what is
578 	 * the upstream port this port should forward to.
580 	int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
583 	/* Snapshot the statistics for a port. The statistics can then
586 	int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
588 	/* Set the histogram mode for statistics, when the control registers
596 	size_t (*stats_get_stat)(struct mv88e6xxx_chip *chip, int port,
599 	int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
602 			       int port);
607 	int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
613 	/* SERDES lane mapping */
614 	int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
618 					   int port);
621 	int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
622 	int (*serdes_get_strings)(struct mv88e6xxx_chip *chip,  int port,
624 	size_t (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,
628 	int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip,  int port);
629 	void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port,
633 	int (*serdes_set_tx_amplitude)(struct mv88e6xxx_chip *chip, int port,
665 	void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port,
702 	/* Access port-scoped Precision Time Protocol registers */
703 	int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
705 	int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
726 	int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
727 	int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
730 	int (*set_ptp_cpu_port)(struct mv88e6xxx_chip *chip, int port);
739 	int (*pcs_init)(struct mv88e6xxx_chip *chip, int port);
740 	void (*pcs_teardown)(struct mv88e6xxx_chip *chip, int port);
741 	struct phylink_pcs *(*pcs_select)(struct mv88e6xxx_chip *chip, int port,
742 					  phy_interface_t mode);
748 	return chip->info->max_sid > 0 &&  in mv88e6xxx_has_stu()
749 		chip->info->ops->stu_loadpurge &&  in mv88e6xxx_has_stu()
750 		chip->info->ops->stu_getnext;  in mv88e6xxx_has_stu()
755 	return chip->info->pvt;  in mv88e6xxx_has_pvt()
760 	return !!chip->info->global2_addr;  in mv88e6xxx_has_lag()
765 	return chip->info->num_databases;  in mv88e6xxx_num_databases()
770 	return chip->info->num_macs;  in mv88e6xxx_num_macs()
775 	return chip->info->num_ports;  in mv88e6xxx_num_ports()
780 	return chip->info->max_vid;  in mv88e6xxx_max_vid()
785 	return chip->info->max_sid;  in mv88e6xxx_max_sid()
790 	return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);  in mv88e6xxx_port_mask()
795 	return chip->info->num_gpio;  in mv88e6xxx_num_gpio()
798 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)  in mv88e6xxx_is_invalid_port()  argument
800 	return (chip->info->invalid_port_mask & BIT(port)) != 0;  in mv88e6xxx_is_invalid_port()
804 					  int port, bool mab)  in mv88e6xxx_port_set_mab()  argument
806 	chip->ports[port].mab = mab;  in mv88e6xxx_port_set_mab()
819 	mutex_lock(&chip->reg_lock);  in mv88e6xxx_reg_lock()
824 	mutex_unlock(&chip->reg_lock);  in mv88e6xxx_reg_unlock()