Lines Matching +full:1 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019-2021 Microchip Technology Inc.
8 #define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12))
10 /* 0 - Operation */
13 #define SW_PHY_REG_BLOCK BIT(7)
14 #define SW_FAST_MODE BIT(3)
15 #define SW_FAST_MODE_OVERRIDE BIT(2)
20 #define LUE_INT BIT(31)
21 #define TRIG_TS_INT BIT(30)
22 #define APB_TIMEOUT_INT BIT(29)
23 #define OVER_TEMP_INT BIT(28)
24 #define HSR_INT BIT(27)
25 #define PIO_INT BIT(26)
26 #define POR_READY_INT BIT(25)
35 /* 1 - Global */
37 #define SW_CLK125_ENB BIT(1)
38 #define SW_CLK25_ENB BIT(0)
40 /* 2 - PHY Control */
42 #define SW_VPHY_DISABLE BIT(31)
44 /* 3 - Operation Control */
47 #define SW_DOUBLE_TAG BIT(7)
48 #define SW_OVER_TEMP_ENABLE BIT(2)
49 #define SW_RESET BIT(1)
53 #define SW_VLAN_ENABLE BIT(7)
54 #define SW_DROP_INVALID_VID BIT(6)
57 #define SW_RESV_MCAST_ENABLE BIT(2)
61 #define UNICAST_LEARN_DISABLE BIT(7)
62 #define SW_FLUSH_STP_TABLE BIT(5)
63 #define SW_FLUSH_MSTP_TABLE BIT(4)
64 #define SW_SRC_ADDR_FILTER BIT(3)
65 #define SW_AGING_ENABLE BIT(2)
66 #define SW_FAST_AGING BIT(1)
67 #define SW_LINK_AUTO_AGING BIT(0)
76 #define SW_NEW_BACKOFF BIT(7)
77 #define SW_PAUSE_UNH_MODE BIT(1)
78 #define SW_AGGR_BACKOFF BIT(0)
81 #define SW_SHORT_IFG BIT(7)
82 #define MULTICAST_STORM_DISABLE BIT(6)
83 #define SW_BACK_PRESSURE BIT(5)
84 #define FAIR_FLOW_CTRL BIT(4)
85 #define NO_EXC_COLLISION_DROP BIT(3)
86 #define SW_LEGAL_PACKET_DISABLE BIT(1)
87 #define SW_PASS_SHORT_FRAME BIT(0)
90 #define SW_MIB_COUNTER_FLUSH BIT(7)
91 #define SW_MIB_COUNTER_FREEZE BIT(6)
93 /* 4 - LUE */
97 #define ALU_V_OVERRIDE BIT(31)
98 #define ALU_V_USE_FID BIT(30)
101 /* 7 - VPhy */
107 #define VPHY_IND_WRITE BIT(1)
108 #define VPHY_IND_BUSY BIT(0)
111 #define VPHY_SMI_INDIRECT_ENABLE BIT(15)
112 #define VPHY_SW_LOOPBACK BIT(14)
113 #define VPHY_MDIO_INTERNAL_ENABLE BIT(13)
114 #define VPHY_SPI_INDIRECT_ENABLE BIT(12)
118 #define VPHY_MODE_MII_PHY 1
121 #define VPHY_SW_COLLISION_TEST BIT(7)
124 #define VPHY_SPEED_1000 BIT(4)
125 #define VPHY_SPEED_100 BIT(3)
126 #define VPHY_FULL_DUPLEX BIT(2)
130 /* 0 - Operation */
134 #define PORT_TAS_INT BIT(5)
135 #define PORT_QCI_INT BIT(4)
136 #define PORT_SGMII_INT BIT(3)
137 #define PORT_PTP_INT BIT(2)
138 #define PORT_PHY_INT BIT(1)
139 #define PORT_ACL_INT BIT(0)
141 #define PORT_SRC_PHY_INT 1
145 #define PORT_MAC_LOOPBACK BIT(7)
146 #define PORT_MAC_REMOTE_LOOPBACK BIT(6)
147 #define PORT_K2L_INSERT_ENABLE BIT(5)
148 #define PORT_K2L_DEBUG_ENABLE BIT(4)
149 #define PORT_TAIL_TAG_ENABLE BIT(2)
152 /* 1 - Phy */
156 /* 3 - xMII */
157 #define PORT_SGMII_SEL BIT(7)
158 #define PORT_GRXC_ENABLE BIT(0)
160 #define PORT_MII_SEL_EDGE BIT(5)
165 #define PORT_DLL_RESET BIT(15)
168 /* 4 - MAC */
170 #define PORT_CHECK_LENGTH BIT(2)
171 #define PORT_BROADCAST_STORM BIT(1)
172 #define PORT_JUMBO_PACKET BIT(0)
175 #define PORT_BACK_PRESSURE BIT(3)
176 #define PORT_PASS_ALL BIT(0)
181 /* 8 - Classification and Policing */
183 #define PORT_HIGHEST_PRIO BIT(7)
184 #define PORT_OR_PRIO BIT(6)
185 #define PORT_MAC_PRIO_ENABLE BIT(4)
186 #define PORT_VLAN_PRIO_ENABLE BIT(3)
187 #define PORT_802_1P_PRIO_ENABLE BIT(2)
188 #define PORT_DIFFSERV_PRIO_ENABLE BIT(1)
189 #define PORT_ACL_PRIO_ENABLE BIT(0)
193 /* 9 - Shaping */
200 #define LAN937X_RGMII_2_PORT (RGMII_2_PORT_NUM - 1)
201 #define LAN937X_RGMII_1_PORT (RGMII_1_PORT_NUM - 1)