Lines Matching +full:0 +full:x0c10

9 #define REG_SW_GLOBAL_LED_OVR__4	0x0120
11 #define LED_OVR_1			BIT(0)
13 #define REG_SW_GLOBAL_LED_SRC__4	0x0128
18 #define REG_PTP_CLK_CTRL		0x0500
26 #define PTP_CLK_RESET			BIT(0)
28 #define REG_PTP_RTC_SUB_NANOSEC__2	0x0502
30 #define PTP_RTC_SUB_NANOSEC_M		0x0007
31 #define PTP_RTC_0NS			0x00
33 #define REG_PTP_RTC_NANOSEC		0x0504
35 #define REG_PTP_RTC_SEC			0x0508
37 #define REG_PTP_SUBNANOSEC_RATE		0x050C
39 #define PTP_SUBNANOSEC_M		0x3FFFFFFF
43 #define REG_PTP_SUBNANOSEC_RATE_L	0x050E
45 #define REG_PTP_RATE_DURATION		0x0510
46 #define REG_PTP_RATE_DURATION_H		0x0510
47 #define REG_PTP_RATE_DURATION_L		0x0512
49 #define REG_PTP_MSG_CONF1		0x0514
58 #define PTP_1STEP			BIT(0)
60 #define REG_PTP_UNIT_INDEX__4		0x0520
64 #define PTP_TOU_INDEX			GENMASK(1, 0)
66 #define REG_PTP_TRIG_STATUS__4		0x0524
69 #define TRIG_DONE_M			GENMASK(2, 0)
71 #define REG_PTP_INT_STATUS__4		0x0528
74 #define TS_INT_M			GENMASK(1, 0)
76 #define REG_PTP_CTRL_STAT__4		0x052C
85 #define TS_RESET			BIT(0)
87 #define REG_TRIG_TARGET_NANOSEC	0x0530
88 #define REG_TRIG_TARGET_SEC		0x0534
90 #define REG_TRIG_CTRL__4		0x0538
99 #define TRIG_NEG_EDGE			0
107 #define TRIG_CASCADE_ITERATE_CNT_M	GENMASK(15, 0)
109 #define REG_TRIG_CYCLE_WIDTH		0x053C
110 #define TRIG_CYCLE_WIDTH_M		GENMASK(31, 0)
112 #define REG_TRIG_CYCLE_CNT		0x0540
115 #define TRIG_BIT_PATTERN_M		GENMASK(15, 0)
117 #define REG_TRIG_ITERATE_TIME		0x0544
119 #define REG_TRIG_PULSE_WIDTH__4	0x0548
121 #define TRIG_PULSE_WIDTH_M		GENMASK(23, 0)
124 #define REG_PTP_PORT_RX_DELAY__2	0x0C00
125 #define REG_PTP_PORT_TX_DELAY__2	0x0C02
126 #define REG_PTP_PORT_ASYM_DELAY__2	0x0C04
128 #define REG_PTP_PORT_XDELAY_TS		0x0C08
129 #define REG_PTP_PORT_SYNC_TS		0x0C0C
130 #define REG_PTP_PORT_PDRESP_TS		0x0C10
132 #define REG_PTP_PORT_TX_INT_STATUS__2	0x0C14
133 #define REG_PTP_PORT_TX_INT_ENABLE__2	0x0C16
140 #define KSZ_PDRES_MSG			0