Lines Matching +full:1 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 Microchip Technology Inc.
14 /* 0 - Operation */
43 #define SW_GIGABIT_ABLE BIT(6)
44 #define SW_REDUNDANCY_ABLE BIT(5)
45 #define SW_AVB_ABLE BIT(4)
63 #define SW_QW_ABLE BIT(5)
69 #define LUE_INT BIT(31)
70 #define TRIG_TS_INT BIT(30)
71 #define APB_TIMEOUT_INT BIT(29)
80 /* 1 - Global */
82 #define SW_SPARE_REG_2 BIT(7)
83 #define SW_SPARE_REG_1 BIT(6)
84 #define SW_SPARE_REG_0 BIT(5)
85 #define SW_BIG_ENDIAN BIT(4)
86 #define SPI_AUTO_EDGE_DETECTION BIT(1)
87 #define SPI_CLOCK_OUT_RISING_EDGE BIT(0)
90 #define SW_ENABLE_REFCLKO BIT(1)
91 #define SW_REFCLKO_IS_125MHZ BIT(0)
95 #define SW_IBA_ENABLE BIT(31)
96 #define SW_IBA_DA_MATCH BIT(30)
97 #define SW_IBA_INIT BIT(29)
106 #define APB_TIMEOUT_ACKNOWLEDGE BIT(31)
112 #define SW_IBA_REQ BIT(31)
113 #define SW_IBA_RESP BIT(30)
114 #define SW_IBA_DA_MISMATCH BIT(14)
115 #define SW_IBA_FMT_MISMATCH BIT(13)
116 #define SW_IBA_CODE_ERROR BIT(12)
117 #define SW_IBA_CMD_ERROR BIT(11)
118 #define SW_IBA_CMD_LOC_M (BIT(6) - 1)
134 #define SW_IBA_RETRY_CNT_M (BIT(5) - 1)
136 /* 2 - PHY */
139 #define SW_PLL_POWER_DOWN BIT(5)
141 #define SW_ENERGY_DETECTION 1
145 /* 3 - Operation Control */
148 #define SW_DOUBLE_TAG BIT(7)
149 #define SW_RESET BIT(1)
160 #define SW_SHAPING_CREDIT_ACCT BIT(1)
161 #define SW_POLICING_CREDIT_ACCT BIT(0)
165 #define SW_VLAN_ENABLE BIT(7)
166 #define SW_DROP_INVALID_VID BIT(6)
170 #define SW_RESV_MCAST_ENABLE BIT(2)
172 #define SW_HASH_OPTION_CRC 1
178 #define UNICAST_LEARN_DISABLE BIT(7)
179 #define SW_SRC_ADDR_FILTER BIT(6)
180 #define SW_FLUSH_STP_TABLE BIT(5)
181 #define SW_FLUSH_MSTP_TABLE BIT(4)
182 #define SW_FWD_MCAST_SRC_ADDR BIT(3)
183 #define SW_AGING_ENABLE BIT(2)
184 #define SW_FAST_AGING BIT(1)
185 #define SW_LINK_AUTO_AGING BIT(0)
189 #define SW_TRAP_DOUBLE_TAG BIT(6)
190 #define SW_EGRESS_VLAN_FILTER_DYN BIT(5)
191 #define SW_EGRESS_VLAN_FILTER_STA BIT(4)
194 #define SW_FLUSH_OPTION_DYN_MAC 1
199 #define SW_PRIO_SA 1
209 #define LEARN_FAIL_INT BIT(2)
210 #define ALMOST_FULL_INT BIT(1)
211 #define WRITE_FAIL_INT BIT(0)
225 #define SW_UNK_UCAST_ENABLE BIT(31)
229 #define SW_UNK_MCAST_ENABLE BIT(31)
233 #define SW_UNK_VID_ENABLE BIT(31)
237 #define SW_NEW_BACKOFF BIT(7)
238 #define SW_CHECK_LENGTH BIT(3)
239 #define SW_PAUSE_UNH_MODE BIT(1)
240 #define SW_AGGR_BACKOFF BIT(0)
244 #define SW_BACK_PRESSURE BIT(5)
246 #define FAIR_FLOW_CTRL BIT(4)
247 #define NO_EXC_COLLISION_DROP BIT(3)
248 #define SW_JUMBO_PACKET BIT(2)
249 #define SW_LEGAL_PACKET_DISABLE BIT(1)
250 #define SW_PASS_SHORT_FRAME BIT(0)
254 #define SW_REPLACE_VID BIT(3)
260 #define SW_PASS_PAUSE BIT(3)
264 #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3)
268 #define SW_MIB_COUNTER_FLUSH BIT(7)
269 #define SW_MIB_COUNTER_FREEZE BIT(6)
283 #define SW_TOS_DSCP_REMARK BIT(1)
284 #define SW_TOS_DSCP_REMAP BIT(0)
321 #define SW_IGMP_SNOOP BIT(6)
322 #define SW_IPV6_MLD_OPTION BIT(3)
323 #define SW_IPV6_MLD_SNOOP BIT(2)
324 #define SW_MIRROR_RX_TX BIT(0)
328 #define SW_CLASS_D_IP_ENABLE BIT(31)
345 #define UNICAST_VLAN_BOUNDARY BIT(1)
351 /* 4 - */
354 #define VLAN_VALID BIT(31)
355 #define VLAN_FORWARD_OPTION BIT(27)
371 #define VLAN_START BIT(7)
373 #define VLAN_WRITE 1
384 #define ALU_DIRECT_INDEX_M (BIT(12) - 1)
388 #define ALU_VALID_CNT_M (BIT(14) - 1)
390 #define ALU_START BIT(7)
391 #define ALU_VALID BIT(6)
392 #define ALU_DIRECT BIT(2)
394 #define ALU_WRITE 1
400 #define ALU_RESV_MCAST_INDEX_M (BIT(6) - 1)
401 #define ALU_STAT_START BIT(7)
402 #define ALU_RESV_MCAST_ADDR BIT(1)
406 #define ALU_V_STATIC_VALID BIT(31)
407 #define ALU_V_SRC_FILTER BIT(30)
408 #define ALU_V_DST_FILTER BIT(29)
409 #define ALU_V_PRIO_AGE_CNT_M (BIT(3) - 1)
415 #define ALU_V_OVERRIDE BIT(31)
416 #define ALU_V_USE_FID BIT(30)
417 #define ALU_V_PORT_MAP (BIT(24) - 1)
421 #define ALU_V_FID_M (BIT(16) - 1)
436 #define HSR_INDEX_MAX BIT(9)
437 #define HSR_DIRECT_INDEX_M (HSR_INDEX_MAX - 1)
441 #define HSR_PATH_INDEX_M (BIT(4) - 1)
445 #define HSR_VALID_CNT_M (BIT(14) - 1)
447 #define HSR_START BIT(7)
448 #define HSR_VALID BIT(6)
449 #define HSR_SEARCH_END BIT(5)
450 #define HSR_DIRECT BIT(2)
452 #define HSR_WRITE 1
458 #define HSR_V_STATIC_VALID BIT(31)
459 #define HSR_V_AGE_CNT_M (BIT(3) - 1)
461 #define HSR_V_PATH_ID_M (BIT(4) - 1)
487 #define HSR_V_SEQ_M (BIT(16) - 1)
489 /* 5 - PTP Clock */
492 #define PTP_STEP_ADJ BIT(6)
493 #define PTP_STEP_DIR BIT(5)
494 #define PTP_READ_TIME BIT(4)
495 #define PTP_LOAD_TIME BIT(3)
496 #define PTP_CLK_ADJ_ENABLE BIT(2)
497 #define PTP_CLK_ENABLE BIT(1)
498 #define PTP_CLK_RESET BIT(0)
515 #define PTP_RATE_DIR BIT(31)
516 #define PTP_TMP_RATE_ENABLE BIT(30)
526 #define PTP_802_1AS BIT(7)
527 #define PTP_ENABLE BIT(6)
528 #define PTP_ETH_ENABLE BIT(5)
529 #define PTP_IPV4_UDP_ENABLE BIT(4)
530 #define PTP_IPV6_UDP_ENABLE BIT(3)
531 #define PTP_TC_P2P BIT(2)
532 #define PTP_MASTER BIT(1)
533 #define PTP_1STEP BIT(0)
537 #define PTP_UNICAST_ENABLE BIT(12)
538 #define PTP_ALTERNATE_MASTER BIT(11)
539 #define PTP_ALL_HIGH_PRIO BIT(10)
540 #define PTP_SYNC_CHECK BIT(9)
541 #define PTP_DELAY_CHECK BIT(8)
542 #define PTP_PDELAY_CHECK BIT(7)
543 #define PTP_DROP_SYNC_DELAY_REQ BIT(5)
544 #define PTP_DOMAIN_CHECK BIT(4)
545 #define PTP_UDP_CHECKSUM BIT(2)
574 #define GPIO_IN BIT(7)
575 #define GPIO_OUT BIT(6)
576 #define TS_INT_ENABLE BIT(5)
577 #define TRIG_ACTIVE BIT(4)
578 #define TRIG_ENABLE BIT(3)
579 #define TRIG_RESET BIT(2)
580 #define TS_ENABLE BIT(1)
581 #define TS_RESET BIT(0)
596 #define TRIG_CASCADE_ENABLE BIT(31)
597 #define TRIG_CASCADE_TAIL BIT(30)
600 #define TRIG_NOW BIT(25)
601 #define TRIG_NOTIFY BIT(24)
602 #define TRIG_EDGE BIT(23)
606 #define TRIG_POS_EDGE 1
634 #define TS_EVENT_OVERFLOW BIT(16)
637 #define TS_DETECT_RISE BIT(7)
638 #define TS_DETECT_FALL BIT(6)
640 #define TS_CASCADE_TAIL BIT(5)
642 #define TS_CASCADE_UPS_S 1
643 #define TS_CASCADE_ENABLE BIT(0)
682 #define TS_EVENT_NANOSEC_M (BIT(30) - 1)
687 (REG_TS_EVENT_1_NANOSEC - REG_TS_EVENT_0_NANOSEC)
689 #define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12))
696 #define DLR_SRC_PORT_UNICAST BIT(31)
699 #define DLR_SRC_PORT_EACH 1
705 #define DLR_RESET_SEQ_ID BIT(3)
706 #define DLR_BACKUP_AUTO_ON BIT(2)
707 #define DLR_BEACON_TX_ENABLE BIT(1)
708 #define DLR_ASSIST_ENABLE BIT(0)
713 #define DLR_NODE_STATE_S 1
715 #define DLR_NODE_STATE_FAULT 1
718 #define DLR_RING_STATE_NORMAL 1
728 #define DLR_TIMEOUT_WINDOW_M (BIT(22) - 1)
732 #define DLR_VLAN_ID_M (BIT(12) - 1)
752 #define HSR_DUPLICATE_DISCARD BIT(7)
753 #define HSR_NODE_UNICAST BIT(6)
756 #define HSR_LEARN_MCAST_DISABLE BIT(2)
759 #define HSR_HASH_UPPER_BITS 1
765 #define HSR_LEARN_UCAST_DISABLE BIT(7)
766 #define HSR_FLUSH_TABLE BIT(5)
767 #define HSR_PROC_MCAST_SRC BIT(3)
768 #define HSR_AGING_ENABLE BIT(2)
777 #define HSR_WINDOW_OVERFLOW_INT BIT(3)
778 #define HSR_LEARN_FAIL_INT BIT(2)
779 #define HSR_ALMOST_FULL_INT BIT(1)
780 #define HSR_WRITE_FAIL_INT BIT(0)
784 #define HSR_ENTRY_INDEX_M (BIT(10) - 1)
785 #define HSR_FAIL_INDEX_M (BIT(8) - 1)
789 #define HSR_FAIL_LEARN_INDEX_M (BIT(8) - 1)
793 #define HSR_CPU_ACCESS_ENTRY_INDEX_M (BIT(8) - 1)
795 /* 0 - Operation */
808 #define PORT_SGMII_INT BIT(3)
809 #define PORT_PTP_INT BIT(2)
810 #define PORT_PHY_INT BIT(1)
811 #define PORT_ACL_INT BIT(0)
818 #define PORT_MAC_LOOPBACK BIT(7)
819 #define PORT_FORCE_TX_FLOW_CTRL BIT(4)
820 #define PORT_FORCE_RX_FLOW_CTRL BIT(3)
821 #define PORT_TAIL_TAG_ENABLE BIT(2)
822 #define PORT_QUEUE_SPLIT_MASK GENMASK(1, 0)
835 #define PORT_INTF_SPEED_NONE GENMASK(1, 0)
836 #define PORT_INTF_FULL_DUPLEX BIT(2)
837 #define PORT_TX_FLOW_CTRL BIT(1)
838 #define PORT_RX_FLOW_CTRL BIT(0)
842 /* 1 - PHY */
845 #define PORT_PHY_RESET BIT(15)
846 #define PORT_PHY_LOOPBACK BIT(14)
847 #define PORT_SPEED_100MBIT BIT(13)
848 #define PORT_AUTO_NEG_ENABLE BIT(12)
849 #define PORT_POWER_DOWN BIT(11)
850 #define PORT_ISOLATE BIT(10)
851 #define PORT_AUTO_NEG_RESTART BIT(9)
852 #define PORT_FULL_DUPLEX BIT(8)
853 #define PORT_COLLISION_TEST BIT(7)
854 #define PORT_SPEED_1000MBIT BIT(6)
858 #define PORT_100BT4_CAPABLE BIT(15)
859 #define PORT_100BTX_FD_CAPABLE BIT(14)
860 #define PORT_100BTX_CAPABLE BIT(13)
861 #define PORT_10BT_FD_CAPABLE BIT(12)
862 #define PORT_10BT_CAPABLE BIT(11)
863 #define PORT_EXTENDED_STATUS BIT(8)
864 #define PORT_MII_SUPPRESS_CAPABLE BIT(6)
865 #define PORT_AUTO_NEG_ACKNOWLEDGE BIT(5)
866 #define PORT_REMOTE_FAULT BIT(4)
867 #define PORT_AUTO_NEG_CAPABLE BIT(3)
868 #define PORT_LINK_STATUS BIT(2)
869 #define PORT_JABBER_DETECT BIT(1)
870 #define PORT_EXTENDED_CAPABILITY BIT(0)
880 #define PORT_AUTO_NEG_NEXT_PAGE BIT(15)
881 #define PORT_AUTO_NEG_REMOTE_FAULT BIT(13)
882 #define PORT_AUTO_NEG_ASYM_PAUSE BIT(11)
883 #define PORT_AUTO_NEG_SYM_PAUSE BIT(10)
884 #define PORT_AUTO_NEG_100BT4 BIT(9)
885 #define PORT_AUTO_NEG_100BTX_FD BIT(8)
886 #define PORT_AUTO_NEG_100BTX BIT(7)
887 #define PORT_AUTO_NEG_10BT_FD BIT(6)
888 #define PORT_AUTO_NEG_10BT BIT(5)
897 #define PORT_REMOTE_NEXT_PAGE BIT(15)
898 #define PORT_REMOTE_ACKNOWLEDGE BIT(14)
899 #define PORT_REMOTE_REMOTE_FAULT BIT(13)
900 #define PORT_REMOTE_ASYM_PAUSE BIT(11)
901 #define PORT_REMOTE_SYM_PAUSE BIT(10)
902 #define PORT_REMOTE_100BTX_FD BIT(8)
903 #define PORT_REMOTE_100BTX BIT(7)
904 #define PORT_REMOTE_10BT_FD BIT(6)
905 #define PORT_REMOTE_10BT BIT(5)
909 #define PORT_AUTO_NEG_MANUAL BIT(12)
910 #define PORT_AUTO_NEG_MASTER BIT(11)
911 #define PORT_AUTO_NEG_MASTER_PREFERRED BIT(10)
912 #define PORT_AUTO_NEG_1000BT_FD BIT(9)
913 #define PORT_AUTO_NEG_1000BT BIT(8)
917 #define PORT_MASTER_FAULT BIT(15)
918 #define PORT_LOCAL_MASTER BIT(14)
919 #define PORT_LOCAL_RX_OK BIT(13)
920 #define PORT_REMOTE_RX_OK BIT(12)
921 #define PORT_REMOTE_1000BT_FD BIT(11)
922 #define PORT_REMOTE_1000BT BIT(10)
936 #define PORT_MMD_OP_DATA_NO_INCR 1
946 #define MMD_DEVICE_ID_DSP 1
953 #define DSP_SQI_ERR_DETECTED BIT(15)
961 #define EEE_ADV_100MBIT BIT(1)
962 #define EEE_ADV_1GBIT BIT(2)
971 #define PORT_100BTX_FD_ABLE BIT(15)
972 #define PORT_100BTX_ABLE BIT(14)
973 #define PORT_10BT_FD_ABLE BIT(13)
974 #define PORT_10BT_ABLE BIT(12)
977 #define PORT_SGMII_AUTO_INCR BIT(23)
980 #define PORT_SGMII_ADDR_M (BIT(21) - 1)
983 #define PORT_SGMII_DATA_M (BIT(16) - 1)
997 #define SR_MII_RESET BIT(15)
998 #define SR_MII_LOOPBACK BIT(14)
999 #define SR_MII_SPEED_100MBIT BIT(13)
1000 #define SR_MII_AUTO_NEG_ENABLE BIT(12)
1001 #define SR_MII_POWER_DOWN BIT(11)
1002 #define SR_MII_AUTO_NEG_RESTART BIT(9)
1003 #define SR_MII_FULL_DUPLEX BIT(8)
1004 #define SR_MII_SPEED_1000MBIT BIT(6)
1011 #define SR_MII_AUTO_NEG_NEXT_PAGE BIT(15)
1015 #define SR_MII_AUTO_NEG_OFFLINE 1
1021 #define SR_MII_AUTO_NEG_ASYM_PAUSE_TX 1
1024 #define SR_MII_AUTO_NEG_HALF_DUPLEX BIT(6)
1025 #define SR_MII_AUTO_NEG_FULL_DUPLEX BIT(5)
1035 #define SR_MII_8_BIT BIT(8)
1036 #define SR_MII_SGMII_LINK_UP BIT(4)
1037 #define SR_MII_TX_CFG_PHY_MASTER BIT(3)
1039 #define SR_MII_PCS_MODE_S 1
1041 #define SR_MII_AUTO_NEG_COMPLETE_INTR BIT(0)
1045 #define SR_MII_STAT_LINK_UP BIT(4)
1049 #define SR_MII_STAT_100_MBPS 1
1051 #define SR_MII_STAT_FULL_DUPLEX BIT(1)
1057 #define SR_MII_PHY_WRITE BIT(1)
1058 #define SR_MII_PHY_START_BUSY BIT(0)
1062 #define SR_MII_PHY_ADDR_M (BIT(16) - 1)
1066 #define SR_MII_PHY_DATA_M (BIT(16) - 1)
1073 #define PORT_REMOTE_LOOPBACK BIT(8)
1076 #define PORT_LED_CTRL_TEST BIT(3)
1077 #define PORT_10BT_PREAMBLE BIT(2)
1078 #define PORT_LINK_MD_10BT_ENABLE BIT(1)
1079 #define PORT_LINK_MD_PASS BIT(0)
1083 #define PORT_START_CABLE_DIAG BIT(15)
1084 #define PORT_TX_DISABLE BIT(14)
1092 #define PORT_CABLE_STAT_OPEN 1
1099 #define PORT_1000_LINK_GOOD BIT(1)
1100 #define PORT_100_LINK_GOOD BIT(0)
1104 #define PORT_LINK_DETECT BIT(14)
1105 #define PORT_SIGNAL_DETECT BIT(13)
1106 #define PORT_PHY_STAT_MDI BIT(12)
1107 #define PORT_PHY_STAT_MASTER BIT(11)
1114 #define JABBER_INT BIT(7)
1115 #define RX_ERR_INT BIT(6)
1116 #define PAGE_RX_INT BIT(5)
1117 #define PARALLEL_DETECT_FAULT_INT BIT(4)
1118 #define LINK_PARTNER_ACK_INT BIT(3)
1119 #define LINK_DOWN_INT BIT(2)
1120 #define REMOTE_FAULT_INT BIT(1)
1121 #define LINK_UP_INT BIT(0)
1125 #define PORT_REG_CLK_SPEED_25_MHZ BIT(14)
1126 #define PORT_PHY_FORCE_MDI BIT(7)
1127 #define PORT_PHY_AUTO_MDIX_DISABLE BIT(6)
1130 #define PORT_PHY_PCS_LOOPBACK BIT(0)
1136 #define PORT_100BT_FIXED_LATENCY BIT(15)
1140 #define PORT_INT_PIN_HIGH BIT(14)
1141 #define PORT_ENABLE_JABBER BIT(9)
1142 #define PORT_STAT_SPEED_1000MBIT BIT(6)
1143 #define PORT_STAT_SPEED_100MBIT BIT(5)
1144 #define PORT_STAT_SPEED_10MBIT BIT(4)
1145 #define PORT_STAT_FULL_DUPLEX BIT(3)
1148 #define PORT_STAT_MASTER BIT(2)
1149 #define PORT_RESET BIT(1)
1150 #define PORT_LINK_STATUS_FAIL BIT(0)
1152 /* 3 - xMII */
1153 #define PORT_SGMII_SEL BIT(7)
1154 #define PORT_GRXC_ENABLE BIT(0)
1156 #define PORT_RMII_CLK_SEL BIT(7)
1157 #define PORT_MII_SEL_EDGE BIT(5)
1164 /* 4 - MAC */
1167 #define PORT_BROADCAST_STORM BIT(1)
1168 #define PORT_JUMBO_FRAME BIT(0)
1172 #define PORT_BACK_PRESSURE BIT(3)
1173 #define PORT_PASS_ALL BIT(0)
1177 #define PORT_100BT_EEE_DISABLE BIT(7)
1178 #define PORT_1000BT_EEE_DISABLE BIT(6)
1185 #define PORT_COUNT_IFG_S 1
1187 #define PORT_IN_PORT_BASED BIT(6)
1188 #define PORT_IN_PACKET_BASED BIT(5)
1189 #define PORT_IN_FLOW_CTRL BIT(4)
1193 #define PORT_IN_UNICAST 1
1196 #define PORT_COUNT_IFG BIT(1)
1197 #define PORT_COUNT_PREAMBLE BIT(0)
1213 #define PORT_RATE_LIMIT_M (BIT(7) - 1)
1215 /* 5 - MIB Counters */
1218 #define MIB_COUNTER_READ BIT(25)
1219 #define MIB_COUNTER_FLUSH_FREEZE BIT(24)
1220 #define MIB_COUNTER_INDEX_M (BIT(8) - 1)
1226 /* 6 - ACL */
1236 #define ACL_MODE_LAYER_2 1
1242 #define ACL_ENABLE_2_TYPE 1
1245 #define ACL_ENABLE_3_IP 1
1248 #define ACL_ENABLE_4_TCP_PORT_COMP 1
1251 #define ACL_SRC BIT(1)
1252 #define ACL_EQUAL BIT(0)
1270 #define ACL_PORT_MODE_S 1
1272 #define ACL_PORT_MODE_EITHER 1
1278 #define ACL_TCP_FLAG_ENABLE BIT(0)
1295 #define ACL_PRIO_MODE_HIGHER 1
1300 #define ACL_VLAN_PRIO_REPLACE BIT(2)
1311 #define ACL_MAP_MODE_OR 1
1315 #define ACL_CNT_M (BIT(11) - 1)
1321 #define ACL_MSEC_UNIT BIT(6)
1322 #define ACL_INTR_MODE BIT(5)
1345 #define PORT_ACL_WRITE_DONE BIT(6)
1346 #define PORT_ACL_READ_DONE BIT(5)
1347 #define PORT_ACL_WRITE BIT(4)
1352 /* 8 - Classification and Policing */
1355 #define PORT_MIRROR_RX BIT(6)
1356 #define PORT_MIRROR_TX BIT(5)
1357 #define PORT_MIRROR_SNIFFER BIT(1)
1361 #define PORT_HIGHEST_PRIO BIT(7)
1362 #define PORT_OR_PRIO BIT(6)
1363 #define PORT_MAC_PRIO_ENABLE BIT(4)
1364 #define PORT_VLAN_PRIO_ENABLE BIT(3)
1365 #define PORT_802_1P_PRIO_ENABLE BIT(2)
1366 #define PORT_DIFFSERV_PRIO_ENABLE BIT(1)
1367 #define PORT_ACL_PRIO_ENABLE BIT(0)
1371 #define PORT_USER_PRIO_CEILING BIT(7)
1372 #define PORT_DROP_NON_VLAN BIT(4)
1373 #define PORT_DROP_TAG BIT(3)
1379 #define PORT_ACL_ENABLE BIT(2)
1382 #define PORT_AUTHEN_BLOCK 1
1399 #define POLICE_DROP_ALL BIT(10)
1403 #define POLICE_PACKET_GREEN 1
1406 #define PORT_BASED_POLICING BIT(7)
1409 #define COLOR_MARK_ENABLE BIT(4)
1410 #define COLOR_REMAP_ENABLE BIT(3)
1411 #define POLICE_DROP_SRP BIT(2)
1412 #define POLICE_COLOR_NOT_AWARE BIT(1)
1413 #define POLICE_ENABLE BIT(0)
1421 #define POLICE_COLOR_MAP_M (BIT(POLICE_COLOR_MAP_S) - 1)
1436 #define WRED_PM_CTRL_M (BIT(11) - 1)
1451 #define WRED_RANDOM_DROP_ENABLE BIT(31)
1452 #define WRED_PMON_FLUSH BIT(30)
1453 #define WRED_DROP_GYR_DISABLE BIT(29)
1454 #define WRED_DROP_YR_DISABLE BIT(28)
1455 #define WRED_DROP_R_DISABLE BIT(27)
1456 #define WRED_DROP_ALL BIT(26)
1457 #define WRED_PMON_M (BIT(24) - 1)
1459 /* 9 - Shaping */
1463 #define MTI_PVID_REPLACE BIT(0)
1467 /* A - QM */
1479 #define PORT_QM_MIN_RESV_SPACE_M (BIT(11) - 1)
1485 #define PORT_QM_WATER_MARK_M (BIT(11) - 1)
1490 #define PORT_QM_TX_CNT_M (BIT(11) - 1)
1498 /* B - LUE */
1501 #define PORT_VLAN_LOOKUP_VID_0 BIT(7)
1502 #define PORT_INGRESS_FILTER BIT(6)
1503 #define PORT_DISCARD_NON_VID BIT(5)
1504 #define PORT_MAC_BASED_802_1X BIT(4)
1505 #define PORT_SRC_ADDR_FILTER BIT(3)
1511 /* C - PTP */
1532 #define PTP_PORT_SYNC_INT BIT(15)
1533 #define PTP_PORT_XDELAY_REQ_INT BIT(14)
1534 #define PTP_PORT_PDELAY_RESP_INT BIT(13)
1571 #define PTP_TRIG_UNIT_M (BIT(MAX_TRIG_UNIT) - 1)
1572 #define PTP_TS_UNIT_M (BIT(MAX_TIMESTAMP_UNIT) - 1)