Lines Matching +full:1 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
23 #define SW_REVISION_S 1
27 #define KSZ8863_GLOBAL_SOFTWARE_RESET BIT(4)
28 #define KSZ8863_PCS_RESET BIT(0)
31 #define KSZ88X3_PORT3_RMII_CLK_INTERNAL BIT(3)
35 #define SW_NEW_BACKOFF BIT(7)
36 #define SW_GLOBAL_RESET BIT(6)
37 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
38 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
39 #define SW_LINK_AUTO_AGING BIT(0)
43 #define SW_HUGE_PACKET BIT(6)
44 #define SW_TX_FLOW_CTRL_DISABLE BIT(5)
45 #define SW_RX_FLOW_CTRL_DISABLE BIT(4)
46 #define SW_CHECK_LENGTH BIT(3)
47 #define SW_AGING_ENABLE BIT(2)
48 #define SW_FAST_AGING BIT(1)
49 #define SW_AGGR_BACKOFF BIT(0)
53 #define UNICAST_VLAN_BOUNDARY BIT(7)
54 #define SW_BACK_PRESSURE BIT(5)
55 #define FAIR_FLOW_CTRL BIT(4)
56 #define NO_EXC_COLLISION_DROP BIT(3)
57 #define SW_LEGAL_PACKET_DISABLE BIT(1)
59 #define KSZ8863_HUGE_PACKET_ENABLE BIT(2)
60 #define KSZ8863_LEGAL_PACKET_ENABLE BIT(1)
63 #define WEIGHTED_FAIR_QUEUE_ENABLE BIT(3)
65 #define SW_VLAN_ENABLE BIT(7)
66 #define SW_IGMP_SNOOP BIT(6)
67 #define SW_MIRROR_RX_TX BIT(0)
71 #define SW_HALF_DUPLEX_FLOW_CTRL BIT(7)
72 #define SW_HALF_DUPLEX BIT(6)
73 #define SW_FLOW_CTRL BIT(5)
74 #define SW_10_MBIT BIT(4)
75 #define SW_REPLACE_VID BIT(3)
81 #define SW_MIB_COUNTER_FLUSH BIT(7)
82 #define SW_MIB_COUNTER_FREEZE BIT(6)
94 #define SW_LED_LINK_ACT 1
100 #define SW_PASS_PAUSE BIT(0)
106 #define SW_PLL_POWER_DOWN BIT(5)
110 #define SW_ENERGY_DETECTION 1
121 #define PORT_BROADCAST_STORM BIT(7)
122 #define PORT_DIFFSERV_ENABLE BIT(6)
123 #define PORT_802_1P_ENABLE BIT(5)
127 #define PORT_BASED_PRIO_1 1
130 #define PORT_INSERT_TAG BIT(2)
131 #define PORT_REMOVE_TAG BIT(1)
132 #define KSZ8795_PORT_2QUEUE_SPLIT_EN BIT(0)
133 #define KSZ8873_PORT_4QUEUE_SPLIT_EN BIT(0)
141 #define PORT_MIRROR_SNIFFER BIT(7)
142 #define PORT_MIRROR_RX BIT(6)
143 #define PORT_MIRROR_TX BIT(5)
152 #define KSZ8873_PORT_2QUEUE_SPLIT_EN BIT(7)
153 #define PORT_INGRESS_FILTER BIT(6)
154 #define PORT_DISCARD_NON_VID BIT(5)
155 #define PORT_FORCE_FLOW_CTRL BIT(4)
156 #define PORT_BACK_PRESSURE BIT(3)
177 #define PORT_ACL_ENABLE BIT(2)
180 #define PORT_AUTHEN_BLOCK 1
185 #define PORT_MII_INTERNAL_CLOCK BIT(7)
186 #define PORT_GMII_MAC_MODE BIT(2)
193 #define PORT_AUTO_NEG_ASYM_PAUSE BIT(5)
194 #define PORT_AUTO_NEG_SYM_PAUSE BIT(4)
195 #define PORT_AUTO_NEG_100BTX_FD BIT(3)
196 #define PORT_AUTO_NEG_100BTX BIT(2)
197 #define PORT_AUTO_NEG_10BT_FD BIT(1)
198 #define PORT_AUTO_NEG_10BT BIT(0)
206 #define PORT_REMOTE_ASYM_PAUSE BIT(5)
207 #define PORT_REMOTE_SYM_PAUSE BIT(4)
208 #define PORT_REMOTE_100BTX_FD BIT(3)
209 #define PORT_REMOTE_100BTX BIT(2)
210 #define PORT_REMOTE_10BT_FD BIT(1)
211 #define PORT_REMOTE_10BT BIT(0)
218 #define PORT_HP_MDIX BIT(7)
219 #define PORT_REVERSED_POLARITY BIT(5)
220 #define PORT_TX_FLOW_CTRL BIT(4)
221 #define PORT_RX_FLOW_CTRL BIT(3)
222 #define PORT_STAT_SPEED_100MBIT BIT(2)
223 #define PORT_STAT_FULL_DUPLEX BIT(1)
225 #define PORT_REMOTE_FAULT BIT(0)
232 #define PORT_CABLE_10M_SHORT BIT(7)
236 #define PORT_CABLE_STAT_OPEN 1
239 #define PORT_START_CABLE_DIAG BIT(4)
240 #define PORT_FORCE_LINK BIT(3)
241 #define PORT_POWER_SAVING BIT(2)
242 #define PORT_PHY_REMOTE_LOOPBACK BIT(1)
258 #define PORT_AUTO_NEG_ENABLE BIT(7)
259 #define PORT_AUTO_NEG_DISABLE BIT(7)
260 #define PORT_FORCE_100_MBIT BIT(6)
261 #define PORT_FORCE_FULL_DUPLEX BIT(5)
268 #define PORT_LED_OFF BIT(7)
269 #define PORT_TX_DISABLE BIT(6)
270 #define PORT_AUTO_NEG_RESTART BIT(5)
271 #define PORT_POWER_DOWN BIT(3)
272 #define PORT_AUTO_MDIX_DISABLE BIT(2)
273 #define PORT_FORCE_MDIX BIT(1)
274 #define PORT_MAC_LOOPBACK BIT(0)
275 #define KSZ8873_PORT_PHY_LOOPBACK BIT(0)
282 #define PORT_MDIX_STATUS BIT(7)
283 #define PORT_AUTO_NEG_COMPLETE BIT(6)
284 #define PORT_STAT_LINK_GOOD BIT(5)
291 #define PORT_PHY_LOOPBACK BIT(7)
292 #define PORT_PHY_ISOLATE BIT(5)
293 #define PORT_PHY_SOFT_RESET BIT(4)
294 #define PORT_PHY_FORCE_LINK BIT(3)
296 #define PHY_MODE_IN_AUTO_NEG 1
335 (REG_PORT_2_CTRL_0 - REG_PORT_1_CTRL_0))
338 #define TABLE_EEE_V 1
346 #define TABLE_READ BIT(4)
349 #define TABLE_VLAN_V 1
370 #define INT_PME BIT(4)
375 #define INT_PORT_5 BIT(4)
376 #define INT_PORT_4 BIT(3)
377 #define INT_PORT_3 BIT(2)
378 #define INT_PORT_2 BIT(1)
379 #define INT_PORT_1 BIT(0)
407 #define SW_SELF_ADDR_FILTER_ENABLE BIT(6)
414 #define SW_UNK_FWD_ENABLE BIT(5)
422 #define SW_IN_RATE_LIMIT_64_MS 1
424 #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3)
425 #define SW_INS_TAG_ENABLE BIT(2)
449 #define SW_IPV6_MLD_OPTION BIT(3)
450 #define SW_IPV6_MLD_SNOOP BIT(2)
458 #define PORT_PASS_ALL BIT(6)
460 #define PORT_INS_TAG_FOR_PORT_5 BIT(3)
461 #define PORT_INS_TAG_FOR_PORT_4 BIT(2)
462 #define PORT_INS_TAG_FOR_PORT_3 BIT(1)
463 #define PORT_INS_TAG_FOR_PORT_2 BIT(0)
471 #define KSZ8795_PORT_4QUEUE_SPLIT_EN BIT(1)
472 #define PORT_DROP_TAG BIT(0)
516 #define RATE_CTRL_ENABLE BIT(7)
517 #define RATE_RATIO_M (BIT(7) - 1)
519 #define PORT_OUT_RATE_ENABLE BIT(7)
532 #define PORT_COUNT_IFG_S 1
534 #define PORT_IN_PORT_BASED BIT(PORT_IN_PORT_BASED_S)
535 #define PORT_RATE_PACKET_BASED BIT(PORT_RATE_PACKET_BASED_S)
536 #define PORT_IN_FLOW_CTRL BIT(PORT_IN_FLOW_CTRL_S)
538 #define PORT_IN_UNICAST 1
541 #define PORT_COUNT_IFG BIT(PORT_COUNT_IFG_S)
542 #define PORT_COUNT_PREAMBLE BIT(PORT_COUNT_PREAMBLE_S)
565 #define PORT_IN_RATE_ENABLE BIT(7)
566 #define PORT_RATE_LIMIT_M (BIT(7) - 1)
595 #define SW_PME_OUTPUT_ENABLE BIT(1)
596 #define SW_PME_ACTIVE_HIGH BIT(0)
598 #define PORT_MAGIC_PACKET_DETECT BIT(2)
599 #define PORT_LINK_UP_DETECT BIT(1)
600 #define PORT_ENERGY_DETECT BIT(0)
609 #define ACL_MODE_LAYER_2 1
615 #define ACL_ENABLE_2_TYPE 1
618 #define ACL_ENABLE_3_IP 1
621 #define ACL_ENABLE_4_TCP_PORT_COMP 1
624 #define ACL_SRC BIT(1)
625 #define ACL_EQUAL BIT(0)
635 #define ACL_PORT_MODE_S 1
637 #define ACL_PORT_MODE_EITHER 1
641 #define ACL_TCP_FLAG_ENABLE BIT(0)
652 #define ACL_PRIO_MODE_HIGHER 1
657 #define ACL_VLAN_PRIO_REPLACE BIT(2)
666 #define ACL_MAP_MODE_OR 1
671 #define ACL_CNT_M (BIT(11) - 1)
673 #define ACL_MSEC_UNIT BIT(4)
674 #define ACL_INTR_MODE BIT(3)
697 #define PORT_ACL_WRITE_DONE BIT(6)
698 #define PORT_ACL_READ_DONE BIT(5)
699 #define PORT_ACL_WRITE BIT(4)
704 #define PORT_ACL_FORCE_DLR_MISS BIT(0)
712 #define PHY_START_CABLE_DIAG BIT(15)
719 #define PHY_CABLE_10M_SHORT BIT(12)
726 #define PHY_STAT_REVERSED_POLARITY BIT(5)
727 #define PHY_STAT_MDIX BIT(4)
728 #define PHY_FORCE_LINK BIT(3)
729 #define PHY_POWER_SAVING_ENABLE BIT(2)
730 #define PHY_REMOTE_LOOPBACK BIT(1)
772 * MIB_COUNTER_VALUE 00-00000000-3FFFFFFF
773 * MIB_TOTAL_BYTES 00-0000000F-FFFFFFFF
774 * MIB_PACKET_DROPPED 00-00000000-0000FFFF
775 * MIB_COUNTER_VALID 00-00000020-00000000
776 * MIB_COUNTER_OVERFLOW 00-00000040-00000000
793 #define TAIL_TAG_OVERRIDE BIT(6)
794 #define TAIL_TAG_LOOKUP BIT(7)