Lines Matching +full:port +full:- +full:mapping +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
16 * The hardware does not support VLAN filter on the port, but on the
20 * rule and the CPU port is also added to all bridges. This makes it possible
23 * each switch port which is used when the port is used without an
46 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p))
135 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x))
143 /* buffer management Port Configuration Register */
147 /* buffer management Port Control Register */
153 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x))
155 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x))
169 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */
170 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */
171 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */
178 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */
180 #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */
181 #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */
219 /* Ethernet Switch Fetch DMA Port Control Register */
221 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */
230 /* Ethernet Switch Store DMA Port Control Register */
232 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */
240 #define GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT GENMASK(7, 4) /* Port on learned entries */
241 #define GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC BIT(0) /* Static, non-aging entry */
246 * but long packets currently cause lock-ups with an MTU of over 2526. Medium
247 * packets are sometimes dropped (e.g. TCP over 2477, UDP over 2516-2519, ICMP
295 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index
296 u16 table; // PCE_TBL_CTRL.ADDR = pData->table
331 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */
346 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */
359 return __raw_readl(priv->gswip + (offset * 4)); in gswip_switch_r()
364 __raw_writel(val, priv->gswip + (offset * 4)); in gswip_switch_w()
382 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, in gswip_switch_r_timeout()
388 return __raw_readl(priv->mdio + (offset * 4)); in gswip_mdio_r()
393 __raw_writel(val, priv->mdio + (offset * 4)); in gswip_mdio_w()
408 return __raw_readl(priv->mii + (offset * 4)); in gswip_mii_r()
413 __raw_writel(val, priv->mii + (offset * 4)); in gswip_mii_w()
427 int port) in gswip_mii_mask_cfg() argument
429 /* There's no MII_CFG register for the CPU port */ in gswip_mii_mask_cfg()
430 if (!dsa_is_cpu_port(priv->ds, port)) in gswip_mii_mask_cfg()
431 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port)); in gswip_mii_mask_cfg()
435 int port) in gswip_mii_mask_pcdu() argument
437 switch (port) { in gswip_mii_mask_pcdu()
454 while (likely(cnt--)) { in gswip_mdio_poll()
462 return -ETIMEDOUT; in gswip_mdio_poll()
467 struct gswip_priv *priv = bus->priv; in gswip_mdio_wr()
472 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); in gswip_mdio_wr()
487 struct gswip_priv *priv = bus->priv; in gswip_mdio_rd()
492 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); in gswip_mdio_rd()
503 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); in gswip_mdio_rd()
512 struct device_node *mdio_np, *switch_np = priv->dev->of_node; in gswip_mdio()
513 struct device *dev = priv->dev; in gswip_mdio()
517 mdio_np = of_get_compatible_child(switch_np, "lantiq,xrx200-mdio"); in gswip_mdio()
523 err = -ENOMEM; in gswip_mdio()
527 bus->priv = priv; in gswip_mdio()
528 bus->read = gswip_mdio_rd; in gswip_mdio()
529 bus->write = gswip_mdio_wr; in gswip_mdio()
530 bus->name = "lantiq,xrx200-mdio"; in gswip_mdio()
531 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv->dev)); in gswip_mdio()
532 bus->parent = priv->dev; in gswip_mdio()
548 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD : in gswip_pce_table_entry_read()
551 mutex_lock(&priv->pce_table_lock); in gswip_pce_table_entry_read()
556 mutex_unlock(&priv->pce_table_lock); in gswip_pce_table_entry_read()
560 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); in gswip_pce_table_entry_read()
563 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, in gswip_pce_table_entry_read()
569 mutex_unlock(&priv->pce_table_lock); in gswip_pce_table_entry_read()
573 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) in gswip_pce_table_entry_read()
574 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i)); in gswip_pce_table_entry_read()
576 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) in gswip_pce_table_entry_read()
577 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i)); in gswip_pce_table_entry_read()
579 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK); in gswip_pce_table_entry_read()
583 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE); in gswip_pce_table_entry_read()
584 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD); in gswip_pce_table_entry_read()
585 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7; in gswip_pce_table_entry_read()
587 mutex_unlock(&priv->pce_table_lock); in gswip_pce_table_entry_read()
598 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR : in gswip_pce_table_entry_write()
601 mutex_lock(&priv->pce_table_lock); in gswip_pce_table_entry_write()
606 mutex_unlock(&priv->pce_table_lock); in gswip_pce_table_entry_write()
610 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); in gswip_pce_table_entry_write()
613 tbl->table | addr_mode, in gswip_pce_table_entry_write()
616 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) in gswip_pce_table_entry_write()
617 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i)); in gswip_pce_table_entry_write()
619 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) in gswip_pce_table_entry_write()
620 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i)); in gswip_pce_table_entry_write()
624 tbl->table | addr_mode, in gswip_pce_table_entry_write()
627 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK); in gswip_pce_table_entry_write()
632 if (tbl->type) in gswip_pce_table_entry_write()
634 if (tbl->valid) in gswip_pce_table_entry_write()
636 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK; in gswip_pce_table_entry_write()
643 mutex_unlock(&priv->pce_table_lock); in gswip_pce_table_entry_write()
648 /* Add the LAN port into a bridge with the CPU port by
653 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add) in gswip_add_single_port_br() argument
657 unsigned int cpu_port = priv->hw_info->cpu_port; in gswip_add_single_port_br()
660 vlan_active.index = port + 1; in gswip_add_single_port_br()
663 vlan_active.val[0] = port + 1 /* fid */; in gswip_add_single_port_br()
667 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); in gswip_add_single_port_br()
674 vlan_mapping.index = port + 1; in gswip_add_single_port_br()
677 vlan_mapping.val[1] = BIT(port) | BIT(cpu_port); in gswip_add_single_port_br()
681 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); in gswip_add_single_port_br()
688 static int gswip_port_enable(struct dsa_switch *ds, int port, in gswip_port_enable() argument
691 struct gswip_priv *priv = ds->priv; in gswip_port_enable()
694 if (!dsa_is_cpu_port(ds, port)) { in gswip_port_enable()
697 err = gswip_add_single_port_br(priv, port, true); in gswip_port_enable()
702 mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK; in gswip_port_enable()
705 GSWIP_MDIO_PHYp(port)); in gswip_port_enable()
708 /* RMON Counter Enable for port */ in gswip_port_enable()
709 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port)); in gswip_port_enable()
711 /* enable port fetch/store dma & VLAN Modification */ in gswip_port_enable()
714 GSWIP_FDMA_PCTRLp(port)); in gswip_port_enable()
716 GSWIP_SDMA_PCTRLp(port)); in gswip_port_enable()
721 static void gswip_port_disable(struct dsa_switch *ds, int port) in gswip_port_disable() argument
723 struct gswip_priv *priv = ds->priv; in gswip_port_disable()
726 GSWIP_FDMA_PCTRLp(port)); in gswip_port_disable()
728 GSWIP_SDMA_PCTRLp(port)); in gswip_port_disable()
768 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port, in gswip_port_vlan_filtering() argument
772 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); in gswip_port_vlan_filtering()
773 struct gswip_priv *priv = ds->priv; in gswip_port_vlan_filtering()
776 if (bridge && !!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) { in gswip_port_vlan_filtering()
779 return -EIO; in gswip_port_vlan_filtering()
788 GSWIP_PCE_VCTRL(port)); in gswip_port_vlan_filtering()
790 GSWIP_PCE_PCTRL_0p(port)); in gswip_port_vlan_filtering()
792 /* Use port based VLAN */ in gswip_port_vlan_filtering()
797 GSWIP_PCE_VCTRL(port)); in gswip_port_vlan_filtering()
799 GSWIP_PCE_PCTRL_0p(port)); in gswip_port_vlan_filtering()
807 struct gswip_priv *priv = ds->priv; in gswip_setup()
808 unsigned int cpu_port = priv->hw_info->cpu_port; in gswip_setup()
816 /* disable port fetch/store dma on all ports */ in gswip_setup()
817 for (i = 0; i < priv->hw_info->max_ports; i++) { in gswip_setup()
827 dev_err(priv->dev, "writing PCE microcode failed, %i\n", err); in gswip_setup()
831 /* Default unknown Broadcast/Multicast/Unicast port maps */ in gswip_setup()
843 * to the switch port being completely dead (RX and TX are both not in gswip_setup()
845 * Also with various other PHY / port combinations (PHY11G GPHY, PHY22F in gswip_setup()
858 for (i = 0; i < priv->hw_info->max_ports; i++) in gswip_setup()
863 /* enable special tag insertion on cpu port */ in gswip_setup()
883 dev_err(priv->dev, "MAC flushing didn't finish\n"); in gswip_setup()
887 ds->mtu_enforcement_ingress = true; in gswip_setup()
889 ds->configure_vlan_while_not_filtering = false; in gswip_setup()
895 int port, in gswip_get_tag_protocol() argument
906 unsigned int max_ports = priv->hw_info->max_ports; in gswip_vlan_active_create()
907 int idx = -1; in gswip_vlan_active_create()
912 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_vlan_active_create()
913 if (!priv->vlans[i].bridge) { in gswip_vlan_active_create()
919 if (idx == -1) in gswip_vlan_active_create()
920 return -ENOSPC; in gswip_vlan_active_create()
922 if (fid == -1) in gswip_vlan_active_create()
933 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); in gswip_vlan_active_create()
937 priv->vlans[idx].bridge = bridge; in gswip_vlan_active_create()
938 priv->vlans[idx].vid = vid; in gswip_vlan_active_create()
939 priv->vlans[idx].fid = fid; in gswip_vlan_active_create()
954 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err); in gswip_vlan_active_remove()
955 priv->vlans[idx].bridge = NULL; in gswip_vlan_active_remove()
961 struct net_device *bridge, int port) in gswip_vlan_add_unaware() argument
964 unsigned int max_ports = priv->hw_info->max_ports; in gswip_vlan_add_unaware()
965 unsigned int cpu_port = priv->hw_info->cpu_port; in gswip_vlan_add_unaware()
967 int idx = -1; in gswip_vlan_add_unaware()
972 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_vlan_add_unaware()
973 if (priv->vlans[i].bridge == bridge) { in gswip_vlan_add_unaware()
980 * entry in a free slot and prepare the VLAN mapping table entry. in gswip_vlan_add_unaware()
982 if (idx == -1) { in gswip_vlan_add_unaware()
983 idx = gswip_vlan_active_create(priv, bridge, -1, 0); in gswip_vlan_add_unaware()
993 /* Read the existing VLAN mapping entry from the switch */ in gswip_vlan_add_unaware()
998 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", in gswip_vlan_add_unaware()
1004 /* Update the VLAN mapping entry and write it to the switch */ in gswip_vlan_add_unaware()
1006 vlan_mapping.val[1] |= BIT(port); in gswip_vlan_add_unaware()
1009 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); in gswip_vlan_add_unaware()
1016 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); in gswip_vlan_add_unaware()
1021 struct net_device *bridge, int port, in gswip_vlan_add_aware() argument
1026 unsigned int max_ports = priv->hw_info->max_ports; in gswip_vlan_add_aware()
1027 unsigned int cpu_port = priv->hw_info->cpu_port; in gswip_vlan_add_aware()
1029 int idx = -1; in gswip_vlan_add_aware()
1030 int fid = -1; in gswip_vlan_add_aware()
1035 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_vlan_add_aware()
1036 if (priv->vlans[i].bridge == bridge) { in gswip_vlan_add_aware()
1037 if (fid != -1 && fid != priv->vlans[i].fid) in gswip_vlan_add_aware()
1038 dev_err(priv->dev, "one bridge with multiple flow ids\n"); in gswip_vlan_add_aware()
1039 fid = priv->vlans[i].fid; in gswip_vlan_add_aware()
1040 if (priv->vlans[i].vid == vid) { in gswip_vlan_add_aware()
1048 * entry in a free slot and prepare the VLAN mapping table entry. in gswip_vlan_add_aware()
1050 if (idx == -1) { in gswip_vlan_add_aware()
1061 /* Read the existing VLAN mapping entry from the switch */ in gswip_vlan_add_aware()
1066 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", in gswip_vlan_add_aware()
1073 /* Update the VLAN mapping entry and write it to the switch */ in gswip_vlan_add_aware()
1076 vlan_mapping.val[1] |= BIT(port); in gswip_vlan_add_aware()
1078 vlan_mapping.val[2] &= ~BIT(port); in gswip_vlan_add_aware()
1080 vlan_mapping.val[2] |= BIT(port); in gswip_vlan_add_aware()
1083 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); in gswip_vlan_add_aware()
1091 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port)); in gswip_vlan_add_aware()
1097 struct net_device *bridge, int port, in gswip_vlan_remove() argument
1101 unsigned int max_ports = priv->hw_info->max_ports; in gswip_vlan_remove()
1102 unsigned int cpu_port = priv->hw_info->cpu_port; in gswip_vlan_remove()
1103 int idx = -1; in gswip_vlan_remove()
1108 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_vlan_remove()
1109 if (priv->vlans[i].bridge == bridge && in gswip_vlan_remove()
1110 (!vlan_aware || priv->vlans[i].vid == vid)) { in gswip_vlan_remove()
1116 if (idx == -1) { in gswip_vlan_remove()
1117 dev_err(priv->dev, "bridge to leave does not exists\n"); in gswip_vlan_remove()
1118 return -ENOENT; in gswip_vlan_remove()
1125 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err); in gswip_vlan_remove()
1129 vlan_mapping.val[1] &= ~BIT(port); in gswip_vlan_remove()
1130 vlan_mapping.val[2] &= ~BIT(port); in gswip_vlan_remove()
1133 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); in gswip_vlan_remove()
1141 dev_err(priv->dev, "failed to write active VLAN: %d\n", in gswip_vlan_remove()
1149 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); in gswip_vlan_remove()
1154 static int gswip_port_bridge_join(struct dsa_switch *ds, int port, in gswip_port_bridge_join() argument
1160 struct gswip_priv *priv = ds->priv; in gswip_port_bridge_join()
1167 err = gswip_vlan_add_unaware(priv, br, port); in gswip_port_bridge_join()
1170 priv->port_vlan_filter &= ~BIT(port); in gswip_port_bridge_join()
1172 priv->port_vlan_filter |= BIT(port); in gswip_port_bridge_join()
1174 return gswip_add_single_port_br(priv, port, false); in gswip_port_bridge_join()
1177 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port, in gswip_port_bridge_leave() argument
1181 struct gswip_priv *priv = ds->priv; in gswip_port_bridge_leave()
1183 gswip_add_single_port_br(priv, port, true); in gswip_port_bridge_leave()
1189 gswip_vlan_remove(priv, br, port, 0, true, false); in gswip_port_bridge_leave()
1192 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port, in gswip_port_vlan_prepare() argument
1196 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); in gswip_port_vlan_prepare()
1197 struct gswip_priv *priv = ds->priv; in gswip_port_vlan_prepare()
1198 unsigned int max_ports = priv->hw_info->max_ports; in gswip_port_vlan_prepare()
1200 int i, idx = -1; in gswip_port_vlan_prepare()
1203 if (!dsa_is_cpu_port(ds, port) && !bridge) in gswip_port_vlan_prepare()
1204 return -EOPNOTSUPP; in gswip_port_vlan_prepare()
1207 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_port_vlan_prepare()
1208 if (priv->vlans[i].bridge == bridge && in gswip_port_vlan_prepare()
1209 priv->vlans[i].vid == vlan->vid) { in gswip_port_vlan_prepare()
1219 if (idx == -1) { in gswip_port_vlan_prepare()
1221 for (; pos < ARRAY_SIZE(priv->vlans); pos++) { in gswip_port_vlan_prepare()
1222 if (!priv->vlans[pos].bridge) { in gswip_port_vlan_prepare()
1229 if (idx == -1) { in gswip_port_vlan_prepare()
1231 return -ENOSPC; in gswip_port_vlan_prepare()
1238 static int gswip_port_vlan_add(struct dsa_switch *ds, int port, in gswip_port_vlan_add() argument
1242 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); in gswip_port_vlan_add()
1243 struct gswip_priv *priv = ds->priv; in gswip_port_vlan_add()
1244 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; in gswip_port_vlan_add()
1245 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in gswip_port_vlan_add()
1248 err = gswip_port_vlan_prepare(ds, port, vlan, extack); in gswip_port_vlan_add()
1252 /* We have to receive all packets on the CPU port and should not in gswip_port_vlan_add()
1257 if (dsa_is_cpu_port(ds, port)) in gswip_port_vlan_add()
1260 return gswip_vlan_add_aware(priv, bridge, port, vlan->vid, in gswip_port_vlan_add()
1264 static int gswip_port_vlan_del(struct dsa_switch *ds, int port, in gswip_port_vlan_del() argument
1267 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); in gswip_port_vlan_del()
1268 struct gswip_priv *priv = ds->priv; in gswip_port_vlan_del()
1269 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in gswip_port_vlan_del()
1271 /* We have to receive all packets on the CPU port and should not in gswip_port_vlan_del()
1276 if (dsa_is_cpu_port(ds, port)) in gswip_port_vlan_del()
1279 return gswip_vlan_remove(priv, bridge, port, vlan->vid, pvid, true); in gswip_port_vlan_del()
1282 static void gswip_port_fast_age(struct dsa_switch *ds, int port) in gswip_port_fast_age() argument
1284 struct gswip_priv *priv = ds->priv; in gswip_port_fast_age()
1295 dev_err(priv->dev, "failed to read mac bridge: %d\n", in gswip_port_fast_age()
1306 if (port != FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT, in gswip_port_fast_age()
1313 dev_err(priv->dev, "failed to write mac bridge: %d\n", in gswip_port_fast_age()
1320 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) in gswip_port_stp_state_set() argument
1322 struct gswip_priv *priv = ds->priv; in gswip_port_stp_state_set()
1328 GSWIP_SDMA_PCTRLp(port)); in gswip_port_stp_state_set()
1341 dev_err(priv->dev, "invalid STP state: %d\n", state); in gswip_port_stp_state_set()
1346 GSWIP_SDMA_PCTRLp(port)); in gswip_port_stp_state_set()
1348 GSWIP_PCE_PCTRL_0p(port)); in gswip_port_stp_state_set()
1351 static int gswip_port_fdb(struct dsa_switch *ds, int port, in gswip_port_fdb() argument
1354 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); in gswip_port_fdb()
1355 struct gswip_priv *priv = ds->priv; in gswip_port_fdb()
1357 unsigned int max_ports = priv->hw_info->max_ports; in gswip_port_fdb()
1358 int fid = -1; in gswip_port_fdb()
1363 return -EINVAL; in gswip_port_fdb()
1365 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_port_fdb()
1366 if (priv->vlans[i].bridge == bridge) { in gswip_port_fdb()
1367 fid = priv->vlans[i].fid; in gswip_port_fdb()
1372 if (fid == -1) { in gswip_port_fdb()
1373 dev_err(priv->dev, "no FID found for bridge %s\n", in gswip_port_fdb()
1374 bridge->name); in gswip_port_fdb()
1375 return -EINVAL; in gswip_port_fdb()
1384 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */ in gswip_port_fdb()
1390 dev_err(priv->dev, "failed to write mac bridge: %d\n", err); in gswip_port_fdb()
1395 static int gswip_port_fdb_add(struct dsa_switch *ds, int port, in gswip_port_fdb_add() argument
1399 return gswip_port_fdb(ds, port, addr, vid, true); in gswip_port_fdb_add()
1402 static int gswip_port_fdb_del(struct dsa_switch *ds, int port, in gswip_port_fdb_del() argument
1406 return gswip_port_fdb(ds, port, addr, vid, false); in gswip_port_fdb_del()
1409 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port, in gswip_port_fdb_dump() argument
1412 struct gswip_priv *priv = ds->priv; in gswip_port_fdb_dump()
1424 dev_err(priv->dev, in gswip_port_fdb_dump()
1440 if (mac_bridge.val[0] & BIT(port)) { in gswip_port_fdb_dump()
1446 if (port == FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT, in gswip_port_fdb_dump()
1457 static int gswip_port_max_mtu(struct dsa_switch *ds, int port) in gswip_port_max_mtu() argument
1460 return GSWIP_MAX_PACKET_LENGTH - VLAN_ETH_HLEN - ETH_FCS_LEN; in gswip_port_max_mtu()
1463 static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) in gswip_port_change_mtu() argument
1465 struct gswip_priv *priv = ds->priv; in gswip_port_change_mtu()
1467 /* CPU port always has maximum mtu of user ports, so use it to set in gswip_port_change_mtu()
1470 if (dsa_is_cpu_port(ds, port)) { in gswip_port_change_mtu()
1476 /* Enable MLEN for ports with non-standard MTUs, including the special in gswip_port_change_mtu()
1477 * header on the CPU port added above. in gswip_port_change_mtu()
1481 GSWIP_MAC_CTRL_2p(port)); in gswip_port_change_mtu()
1484 GSWIP_MAC_CTRL_2p(port)); in gswip_port_change_mtu()
1489 static void gswip_xrx200_phylink_get_caps(struct dsa_switch *ds, int port, in gswip_xrx200_phylink_get_caps() argument
1492 switch (port) { in gswip_xrx200_phylink_get_caps()
1495 phy_interface_set_rgmii(config->supported_interfaces); in gswip_xrx200_phylink_get_caps()
1497 config->supported_interfaces); in gswip_xrx200_phylink_get_caps()
1499 config->supported_interfaces); in gswip_xrx200_phylink_get_caps()
1501 config->supported_interfaces); in gswip_xrx200_phylink_get_caps()
1509 config->supported_interfaces); in gswip_xrx200_phylink_get_caps()
1513 phy_interface_set_rgmii(config->supported_interfaces); in gswip_xrx200_phylink_get_caps()
1515 config->supported_interfaces); in gswip_xrx200_phylink_get_caps()
1519 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | in gswip_xrx200_phylink_get_caps()
1523 static void gswip_xrx300_phylink_get_caps(struct dsa_switch *ds, int port, in gswip_xrx300_phylink_get_caps() argument
1526 switch (port) { in gswip_xrx300_phylink_get_caps()
1528 phy_interface_set_rgmii(config->supported_interfaces); in gswip_xrx300_phylink_get_caps()
1530 config->supported_interfaces); in gswip_xrx300_phylink_get_caps()
1532 config->supported_interfaces); in gswip_xrx300_phylink_get_caps()
1541 config->supported_interfaces); in gswip_xrx300_phylink_get_caps()
1545 phy_interface_set_rgmii(config->supported_interfaces); in gswip_xrx300_phylink_get_caps()
1547 config->supported_interfaces); in gswip_xrx300_phylink_get_caps()
1549 config->supported_interfaces); in gswip_xrx300_phylink_get_caps()
1553 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | in gswip_xrx300_phylink_get_caps()
1557 static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link) in gswip_port_set_link() argument
1567 GSWIP_MDIO_PHYp(port)); in gswip_port_set_link()
1570 static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed, in gswip_port_set_speed() argument
1608 GSWIP_MDIO_PHYp(port)); in gswip_port_set_speed()
1609 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port); in gswip_port_set_speed()
1611 GSWIP_MAC_CTRL_0p(port)); in gswip_port_set_speed()
1614 static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex) in gswip_port_set_duplex() argument
1627 GSWIP_MAC_CTRL_0p(port)); in gswip_port_set_duplex()
1629 GSWIP_MDIO_PHYp(port)); in gswip_port_set_duplex()
1632 static void gswip_port_set_pause(struct gswip_priv *priv, int port, in gswip_port_set_pause() argument
1656 mac_ctrl_0, GSWIP_MAC_CTRL_0p(port)); in gswip_port_set_pause()
1660 mdio_phy, GSWIP_MDIO_PHYp(port)); in gswip_port_set_pause()
1664 unsigned int mode, in gswip_phylink_mac_config() argument
1668 struct gswip_priv *priv = dp->ds->priv; in gswip_phylink_mac_config()
1669 int port = dp->index; in gswip_phylink_mac_config() local
1674 switch (state->interface) { in gswip_phylink_mac_config()
1695 dev_err(dp->ds->dev, in gswip_phylink_mac_config()
1696 "Unsupported interface: %d\n", state->interface); in gswip_phylink_mac_config()
1703 miicfg, port); in gswip_phylink_mac_config()
1705 switch (state->interface) { in gswip_phylink_mac_config()
1708 GSWIP_MII_PCDU_RXDLY_MASK, 0, port); in gswip_phylink_mac_config()
1711 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port); in gswip_phylink_mac_config()
1714 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port); in gswip_phylink_mac_config()
1722 unsigned int mode, in gswip_phylink_mac_link_down() argument
1726 struct gswip_priv *priv = dp->ds->priv; in gswip_phylink_mac_link_down()
1727 int port = dp->index; in gswip_phylink_mac_link_down() local
1729 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port); in gswip_phylink_mac_link_down()
1732 gswip_port_set_link(priv, port, false); in gswip_phylink_mac_link_down()
1737 unsigned int mode, in gswip_phylink_mac_link_up() argument
1743 struct gswip_priv *priv = dp->ds->priv; in gswip_phylink_mac_link_up()
1744 int port = dp->index; in gswip_phylink_mac_link_up() local
1747 gswip_port_set_link(priv, port, true); in gswip_phylink_mac_link_up()
1748 gswip_port_set_speed(priv, port, speed, interface); in gswip_phylink_mac_link_up()
1749 gswip_port_set_duplex(priv, port, duplex); in gswip_phylink_mac_link_up()
1750 gswip_port_set_pause(priv, port, tx_pause, rx_pause); in gswip_phylink_mac_link_up()
1753 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port); in gswip_phylink_mac_link_up()
1756 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset, in gswip_get_strings() argument
1783 dev_err(priv->dev, "timeout while reading table: %u, index: %u\n", in gswip_bcm_ram_entry_read()
1794 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port, in gswip_get_ethtool_stats() argument
1797 struct gswip_priv *priv = ds->priv; in gswip_get_ethtool_stats()
1805 data[i] = gswip_bcm_ram_entry_read(priv, port, in gswip_get_ethtool_stats()
1806 rmon_cnt->offset); in gswip_get_ethtool_stats()
1807 if (rmon_cnt->size == 2) { in gswip_get_ethtool_stats()
1808 high = gswip_bcm_ram_entry_read(priv, port, in gswip_get_ethtool_stats()
1809 rmon_cnt->offset + 1); in gswip_get_ethtool_stats()
1815 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset) in gswip_get_sset_count() argument
1891 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL },
1892 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data },
1893 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data },
1894 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data },
1895 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data },
1901 struct device *dev = priv->dev; in gswip_gphy_fw_load()
1909 ret = clk_prepare_enable(gphy_fw->clk_gate); in gswip_gphy_fw_load()
1913 reset_control_assert(gphy_fw->reset); in gswip_gphy_fw_load()
1921 ret = request_firmware(&fw, gphy_fw->fw_name, dev); in gswip_gphy_fw_load()
1924 gphy_fw->fw_name); in gswip_gphy_fw_load()
1929 size = fw->size + XRX200_GPHY_FW_ALIGN; in gswip_gphy_fw_load()
1935 memcpy(fw_addr, fw->data, fw->size); in gswip_gphy_fw_load()
1938 return dev_err_probe(dev, -ENOMEM, in gswip_gphy_fw_load()
1944 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr); in gswip_gphy_fw_load()
1948 reset_control_deassert(gphy_fw->reset); in gswip_gphy_fw_load()
1957 struct device *dev = priv->dev; in gswip_gphy_fw_probe()
1964 gphy_fw->clk_gate = devm_clk_get(dev, gphyname); in gswip_gphy_fw_probe()
1965 if (IS_ERR(gphy_fw->clk_gate)) { in gswip_gphy_fw_probe()
1966 return dev_err_probe(dev, PTR_ERR(gphy_fw->clk_gate), in gswip_gphy_fw_probe()
1970 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset); in gswip_gphy_fw_probe()
1974 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode); in gswip_gphy_fw_probe()
1975 /* Default to GE mode */ in gswip_gphy_fw_probe()
1981 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name; in gswip_gphy_fw_probe()
1984 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name; in gswip_gphy_fw_probe()
1987 return dev_err_probe(dev, -EINVAL, "Unknown GPHY mode %d\n", in gswip_gphy_fw_probe()
1991 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np); in gswip_gphy_fw_probe()
1992 if (IS_ERR(gphy_fw->reset)) in gswip_gphy_fw_probe()
1993 return dev_err_probe(dev, PTR_ERR(gphy_fw->reset), in gswip_gphy_fw_probe()
2005 if (!gphy_fw->fw_name) in gswip_gphy_fw_remove()
2008 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0); in gswip_gphy_fw_remove()
2010 dev_err(priv->dev, "can not reset GPHY FW pointer\n"); in gswip_gphy_fw_remove()
2012 clk_disable_unprepare(gphy_fw->clk_gate); in gswip_gphy_fw_remove()
2014 reset_control_put(gphy_fw->reset); in gswip_gphy_fw_remove()
2020 struct device *dev = priv->dev; in gswip_gphy_fw_list()
2030 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) { in gswip_gphy_fw_list()
2033 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data; in gswip_gphy_fw_list()
2036 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data; in gswip_gphy_fw_list()
2039 return dev_err_probe(dev, -ENOENT, in gswip_gphy_fw_list()
2046 if (match && match->data) in gswip_gphy_fw_list()
2047 priv->gphy_fw_name_cfg = match->data; in gswip_gphy_fw_list()
2049 if (!priv->gphy_fw_name_cfg) in gswip_gphy_fw_list()
2050 return dev_err_probe(dev, -ENOENT, in gswip_gphy_fw_list()
2053 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np); in gswip_gphy_fw_list()
2054 if (!priv->num_gphy_fw) in gswip_gphy_fw_list()
2055 return -ENOENT; in gswip_gphy_fw_list()
2057 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np, in gswip_gphy_fw_list()
2059 if (IS_ERR(priv->rcu_regmap)) in gswip_gphy_fw_list()
2060 return PTR_ERR(priv->rcu_regmap); in gswip_gphy_fw_list()
2062 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw, in gswip_gphy_fw_list()
2063 sizeof(*priv->gphy_fw), in gswip_gphy_fw_list()
2065 if (!priv->gphy_fw) in gswip_gphy_fw_list()
2066 return -ENOMEM; in gswip_gphy_fw_list()
2069 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i], in gswip_gphy_fw_list()
2080 * taken out of reset. For the SoC-internal GPHY variant there in gswip_gphy_fw_list()
2091 for (i = 0; i < priv->num_gphy_fw; i++) in gswip_gphy_fw_list()
2092 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); in gswip_gphy_fw_list()
2099 struct device *dev = &pdev->dev; in gswip_probe()
2107 return -ENOMEM; in gswip_probe()
2109 priv->gswip = devm_platform_ioremap_resource(pdev, 0); in gswip_probe()
2110 if (IS_ERR(priv->gswip)) in gswip_probe()
2111 return PTR_ERR(priv->gswip); in gswip_probe()
2113 priv->mdio = devm_platform_ioremap_resource(pdev, 1); in gswip_probe()
2114 if (IS_ERR(priv->mdio)) in gswip_probe()
2115 return PTR_ERR(priv->mdio); in gswip_probe()
2117 priv->mii = devm_platform_ioremap_resource(pdev, 2); in gswip_probe()
2118 if (IS_ERR(priv->mii)) in gswip_probe()
2119 return PTR_ERR(priv->mii); in gswip_probe()
2121 priv->hw_info = of_device_get_match_data(dev); in gswip_probe()
2122 if (!priv->hw_info) in gswip_probe()
2123 return -EINVAL; in gswip_probe()
2125 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); in gswip_probe()
2126 if (!priv->ds) in gswip_probe()
2127 return -ENOMEM; in gswip_probe()
2129 priv->ds->dev = dev; in gswip_probe()
2130 priv->ds->num_ports = priv->hw_info->max_ports; in gswip_probe()
2131 priv->ds->priv = priv; in gswip_probe()
2132 priv->ds->ops = priv->hw_info->ops; in gswip_probe()
2133 priv->ds->phylink_mac_ops = &gswip_phylink_mac_ops; in gswip_probe()
2134 priv->dev = dev; in gswip_probe()
2135 mutex_init(&priv->pce_table_lock); in gswip_probe()
2138 np = dev->of_node; in gswip_probe()
2142 if (!of_device_is_compatible(np, "lantiq,xrx200-gswip")) in gswip_probe()
2143 return -EINVAL; in gswip_probe()
2147 if (!of_device_is_compatible(np, "lantiq,xrx300-gswip") && in gswip_probe()
2148 !of_device_is_compatible(np, "lantiq,xrx330-gswip")) in gswip_probe()
2149 return -EINVAL; in gswip_probe()
2152 return dev_err_probe(dev, -ENOENT, in gswip_probe()
2157 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw"); in gswip_probe()
2173 err = dsa_register_switch(priv->ds); in gswip_probe()
2178 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) { in gswip_probe()
2179 err = dev_err_probe(dev, -EINVAL, in gswip_probe()
2180 "wrong CPU port defined, HW only supports port: %i\n", in gswip_probe()
2181 priv->hw_info->cpu_port); in gswip_probe()
2194 dsa_unregister_switch(priv->ds); in gswip_probe()
2196 for (i = 0; i < priv->num_gphy_fw; i++) in gswip_probe()
2197 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); in gswip_probe()
2212 dsa_unregister_switch(priv->ds); in gswip_remove()
2214 for (i = 0; i < priv->num_gphy_fw; i++) in gswip_remove()
2215 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); in gswip_remove()
2225 dsa_switch_shutdown(priv->ds); in gswip_shutdown()
2243 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 },
2244 { .compatible = "lantiq,xrx300-gswip", .data = &gswip_xrx300 },
2245 { .compatible = "lantiq,xrx330-gswip", .data = &gswip_xrx300 },
2268 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");