Lines Matching +full:unimac +full:- +full:mdio
1 // SPDX-License-Identifier: GPL-2.0-or-later
37 switch (priv->type) { in bcm_sf2_reg_rgmii_cntrl()
76 switch (priv->type) { in bcm_sf2_reg_led_base()
99 switch (priv->type) { in bcm_sf2_port_override_offset()
108 WARN_ONCE(1, "Unsupported device: %d\n", priv->type); in bcm_sf2_port_override_offset()
121 for (port = 0; port < ds->num_ports; port++) { in bcm_sf2_num_active_ports()
124 if (priv->port_sts[port].enabled) in bcm_sf2_num_active_ports()
145 if (ports_active == 0 || !priv->clk_mdiv) in bcm_sf2_recalc_clock()
154 new_rate = rate_table[ports_active - 1]; in bcm_sf2_recalc_clock()
155 clk_set_rate(priv->clk_mdiv, new_rate); in bcm_sf2_recalc_clock()
199 priv->port_sts[port].enabled = true; in bcm_sf2_imp_setup()
223 /* Use PHY-driven LED signaling */ in bcm_sf2_gphy_enable_set()
227 if (priv->type == BCM7278_DEVICE_ID || in bcm_sf2_gphy_enable_set()
228 priv->type == BCM7445_DEVICE_ID) { in bcm_sf2_gphy_enable_set()
290 priv->port_sts[port].enabled = true; in bcm_sf2_port_setup()
300 if (priv->brcm_tag_mask & BIT(port)) in bcm_sf2_port_setup()
311 /* Re-enable the GPHY and re-apply workarounds */ in bcm_sf2_port_setup()
312 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { in bcm_sf2_port_setup()
324 phy->state = PHY_READY; in bcm_sf2_port_setup()
330 if (port == priv->moca_port) in bcm_sf2_port_setup()
333 /* Set per-queue pause threshold to 32 */ in bcm_sf2_port_setup()
355 if (priv->wol_ports_mask & (1 << port)) { in bcm_sf2_port_disable()
362 if (port == priv->moca_port) in bcm_sf2_port_disable()
365 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) in bcm_sf2_port_disable()
375 priv->port_sts[port].enabled = false; in bcm_sf2_port_disable()
414 struct bcm_sf2_priv *priv = bus->priv; in bcm_sf2_sw_mdio_read()
416 /* Intercept reads from Broadcom pseudo-PHY address, else, send in bcm_sf2_sw_mdio_read()
417 * them to our master MDIO bus controller in bcm_sf2_sw_mdio_read()
419 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) in bcm_sf2_sw_mdio_read()
422 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); in bcm_sf2_sw_mdio_read()
428 struct bcm_sf2_priv *priv = bus->priv; in bcm_sf2_sw_mdio_write()
430 /* Intercept writes to the Broadcom pseudo-PHY address, else, in bcm_sf2_sw_mdio_write()
431 * send them to our master MDIO bus controller in bcm_sf2_sw_mdio_write()
433 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) in bcm_sf2_sw_mdio_write()
436 return mdiobus_write_nested(priv->master_mii_bus, addr, in bcm_sf2_sw_mdio_write()
445 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & in bcm_sf2_switch_0_isr()
446 ~priv->irq0_mask; in bcm_sf2_switch_0_isr()
447 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); in bcm_sf2_switch_0_isr()
457 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & in bcm_sf2_switch_1_isr()
458 ~priv->irq1_mask; in bcm_sf2_switch_1_isr()
459 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); in bcm_sf2_switch_1_isr()
461 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { in bcm_sf2_switch_1_isr()
462 priv->port_sts[7].link = true; in bcm_sf2_switch_1_isr()
465 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { in bcm_sf2_switch_1_isr()
466 priv->port_sts[7].link = false; in bcm_sf2_switch_1_isr()
482 if (priv->type == BCM7278_DEVICE_ID) { in bcm_sf2_sw_rst()
483 ret = reset_control_assert(priv->rcdev); in bcm_sf2_sw_rst()
487 return reset_control_deassert(priv->rcdev); in bcm_sf2_sw_rst()
500 } while (timeout-- > 0); in bcm_sf2_sw_rst()
503 return -ETIMEDOUT; in bcm_sf2_sw_rst()
510 struct device *dev = priv->dev->ds->dev; in bcm_sf2_crossbar_setup()
516 mask = BIT(priv->num_crossbar_int_ports) - 1; in bcm_sf2_crossbar_setup()
519 switch (priv->type) { in bcm_sf2_crossbar_setup()
521 shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports; in bcm_sf2_crossbar_setup()
525 else if (priv->int_phy_mask & BIT(7)) in bcm_sf2_crossbar_setup()
527 else if (phy_interface_mode_is_rgmii(priv->port_sts[7].mode)) in bcm_sf2_crossbar_setup()
538 for (i = 0; i < priv->num_crossbar_int_ports; i++) { in bcm_sf2_crossbar_setup()
539 shift = i * priv->num_crossbar_int_ports; in bcm_sf2_crossbar_setup()
541 dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i, in bcm_sf2_crossbar_setup()
557 struct device *dev = priv->dev->ds->dev; in bcm_sf2_identify_ports()
564 priv->moca_port = -1; in bcm_sf2_identify_ports()
575 port_st = &priv->port_sts[port_num]; in bcm_sf2_identify_ports()
577 /* Internal PHYs get assigned a specific 'phy-mode' property in bcm_sf2_identify_ports()
578 * value: "internal" to help flag them before MDIO probing in bcm_sf2_identify_ports()
582 err = of_get_phy_mode(port, &port_st->mode); in bcm_sf2_identify_ports()
586 if (port_st->mode == PHY_INTERFACE_MODE_INTERNAL) in bcm_sf2_identify_ports()
587 priv->int_phy_mask |= 1 << port_num; in bcm_sf2_identify_ports()
589 if (port_st->mode == PHY_INTERFACE_MODE_MOCA) in bcm_sf2_identify_ports()
590 priv->moca_port = port_num; in bcm_sf2_identify_ports()
592 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) in bcm_sf2_identify_ports()
593 priv->brcm_tag_mask |= 1 << port_num; in bcm_sf2_identify_ports()
599 if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) { in bcm_sf2_identify_ports()
616 /* Find our integrated MDIO bus node */ in bcm_sf2_mdio_register()
617 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); in bcm_sf2_mdio_register()
618 priv->master_mii_bus = of_mdio_find_bus(dn); in bcm_sf2_mdio_register()
619 if (!priv->master_mii_bus) { in bcm_sf2_mdio_register()
620 err = -EPROBE_DEFER; in bcm_sf2_mdio_register()
624 priv->user_mii_bus = mdiobus_alloc(); in bcm_sf2_mdio_register()
625 if (!priv->user_mii_bus) { in bcm_sf2_mdio_register()
626 err = -ENOMEM; in bcm_sf2_mdio_register()
630 priv->user_mii_bus->priv = priv; in bcm_sf2_mdio_register()
631 priv->user_mii_bus->name = "sf2 user mii"; in bcm_sf2_mdio_register()
632 priv->user_mii_bus->read = bcm_sf2_sw_mdio_read; in bcm_sf2_mdio_register()
633 priv->user_mii_bus->write = bcm_sf2_sw_mdio_write; in bcm_sf2_mdio_register()
634 snprintf(priv->user_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", in bcm_sf2_mdio_register()
637 /* Include the pseudo-PHY address to divert reads towards our in bcm_sf2_mdio_register()
639 * disconnects the internal switch pseudo-PHY such that we can use the in bcm_sf2_mdio_register()
643 * otherwise make all other PHY read/writes go to the master MDIO bus in bcm_sf2_mdio_register()
644 * controller that comes with this switch backed by the "mdio-unimac" in bcm_sf2_mdio_register()
648 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0); in bcm_sf2_mdio_register()
650 priv->indir_phy_mask = 0; in bcm_sf2_mdio_register()
652 ds->phys_mii_mask = priv->indir_phy_mask; in bcm_sf2_mdio_register()
653 ds->user_mii_bus = priv->user_mii_bus; in bcm_sf2_mdio_register()
654 priv->user_mii_bus->parent = ds->dev->parent; in bcm_sf2_mdio_register()
655 priv->user_mii_bus->phy_mask = ~priv->indir_phy_mask; in bcm_sf2_mdio_register()
666 if (!(priv->indir_phy_mask & BIT(reg))) in bcm_sf2_mdio_register()
684 err = mdiobus_register(priv->user_mii_bus); in bcm_sf2_mdio_register()
693 mdiobus_free(priv->user_mii_bus); in bcm_sf2_mdio_register()
695 put_device(&priv->master_mii_bus->dev); in bcm_sf2_mdio_register()
703 mdiobus_unregister(priv->user_mii_bus); in bcm_sf2_mdio_unregister()
704 mdiobus_free(priv->user_mii_bus); in bcm_sf2_mdio_unregister()
705 put_device(&priv->master_mii_bus->dev); in bcm_sf2_mdio_unregister()
716 if (priv->int_phy_mask & BIT(port)) in bcm_sf2_sw_get_phy_flags()
717 return priv->hw_params.gphy_rev; in bcm_sf2_sw_get_phy_flags()
727 unsigned long *interfaces = config->supported_interfaces; in bcm_sf2_sw_get_caps()
730 if (priv->int_phy_mask & BIT(port)) { in bcm_sf2_sw_get_caps()
732 } else if (priv->moca_port == port) { in bcm_sf2_sw_get_caps()
741 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | in bcm_sf2_sw_get_caps()
755 priv = bcm_sf2_to_priv(dp->ds); in bcm_sf2_sw_mac_config()
757 if (dp->index == core_readl(priv, CORE_IMP0_PRT_ID)) in bcm_sf2_sw_mac_config()
760 switch (state->interface) { in bcm_sf2_sw_mac_config()
778 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, dp->index); in bcm_sf2_sw_mac_config()
823 int port = dp->index; in bcm_sf2_sw_mac_link_down()
826 priv = bcm_sf2_to_priv(dp->ds); in bcm_sf2_sw_mac_link_down()
827 if (priv->wol_ports_mask & BIT(port)) in bcm_sf2_sw_mac_link_down()
835 bcm_sf2_sw_mac_link_set(dp->ds, port, interface, false); in bcm_sf2_sw_mac_link_down()
849 int port = dp->index; in bcm_sf2_sw_mac_link_up()
852 bcm_sf2_sw_mac_link_set(dp->ds, port, interface, true); in bcm_sf2_sw_mac_link_up()
854 priv = bcm_sf2_to_priv(dp->ds); in bcm_sf2_sw_mac_link_up()
874 if (priv->type == BCM4908_DEVICE_ID) in bcm_sf2_sw_mac_link_up()
901 p = &priv->dev->ports[port].eee; in bcm_sf2_sw_mac_link_up()
902 p->eee_enabled = b53_eee_init(dp->ds, port, phydev); in bcm_sf2_sw_mac_link_up()
911 status->link = false; in bcm_sf2_sw_fixed_state()
921 if (port == priv->moca_port) { in bcm_sf2_sw_fixed_state()
922 status->link = priv->port_sts[port].link; in bcm_sf2_sw_fixed_state()
924 * since some version of the user-space daemon (mocad) use in bcm_sf2_sw_fixed_state()
925 * cmd->autoneg to force the link, which messes up the PHY in bcm_sf2_sw_fixed_state()
928 if (!status->link) in bcm_sf2_sw_fixed_state()
929 netif_carrier_off(dsa_to_port(ds, port)->user); in bcm_sf2_sw_fixed_state()
930 status->duplex = DUPLEX_FULL; in bcm_sf2_sw_fixed_state()
932 status->link = true; in bcm_sf2_sw_fixed_state()
961 for (port = 0; port < ds->num_ports; port++) { in bcm_sf2_sw_suspend()
966 if (!priv->wol_ports_mask) in bcm_sf2_sw_suspend()
967 clk_disable_unprepare(priv->clk); in bcm_sf2_sw_suspend()
977 if (!priv->wol_ports_mask) in bcm_sf2_sw_resume()
978 clk_prepare_enable(priv->clk); in bcm_sf2_sw_resume()
992 if (priv->hw_params.num_gphy == 1) in bcm_sf2_sw_resume()
995 ds->ops->setup(ds); in bcm_sf2_sw_resume()
1008 if (p->ethtool_ops->get_wol) in bcm_sf2_sw_get_wol()
1009 p->ethtool_ops->get_wol(p, &pwol); in bcm_sf2_sw_get_wol()
1012 wol->supported = pwol.supported; in bcm_sf2_sw_get_wol()
1013 memset(&wol->sopass, 0, sizeof(wol->sopass)); in bcm_sf2_sw_get_wol()
1016 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); in bcm_sf2_sw_get_wol()
1018 if (priv->wol_ports_mask & (1 << port)) in bcm_sf2_sw_get_wol()
1019 wol->wolopts = pwol.wolopts; in bcm_sf2_sw_get_wol()
1021 wol->wolopts = 0; in bcm_sf2_sw_get_wol()
1029 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; in bcm_sf2_sw_set_wol()
1032 if (p->ethtool_ops->get_wol) in bcm_sf2_sw_set_wol()
1033 p->ethtool_ops->get_wol(p, &pwol); in bcm_sf2_sw_set_wol()
1034 if (wol->wolopts & ~pwol.supported) in bcm_sf2_sw_set_wol()
1035 return -EINVAL; in bcm_sf2_sw_set_wol()
1037 if (wol->wolopts) in bcm_sf2_sw_set_wol()
1038 priv->wol_ports_mask |= (1 << port); in bcm_sf2_sw_set_wol()
1040 priv->wol_ports_mask &= ~(1 << port); in bcm_sf2_sw_set_wol()
1046 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) in bcm_sf2_sw_set_wol()
1047 priv->wol_ports_mask |= (1 << cpu_port); in bcm_sf2_sw_set_wol()
1049 priv->wol_ports_mask &= ~(1 << cpu_port); in bcm_sf2_sw_set_wol()
1051 return p->ethtool_ops->set_wol(p, wol); in bcm_sf2_sw_set_wol()
1060 for (port = 0; port < priv->hw_params.num_ports; port++) { in bcm_sf2_sw_setup()
1083 * bus-glue understands.
1090 struct bcm_sf2_priv *priv = dev->priv; in bcm_sf2_core_read8()
1100 struct bcm_sf2_priv *priv = dev->priv; in bcm_sf2_core_read16()
1110 struct bcm_sf2_priv *priv = dev->priv; in bcm_sf2_core_read32()
1120 struct bcm_sf2_priv *priv = dev->priv; in bcm_sf2_core_read64()
1130 struct bcm_sf2_priv *priv = dev->priv; in bcm_sf2_core_write8()
1140 struct bcm_sf2_priv *priv = dev->priv; in bcm_sf2_core_write16()
1150 struct bcm_sf2_priv *priv = dev->priv; in bcm_sf2_core_write32()
1160 struct bcm_sf2_priv *priv = dev->priv; in bcm_sf2_core_write64()
1341 { .compatible = "brcm,bcm4908-switch",
1344 { .compatible = "brcm,bcm7445-switch-v4.0",
1347 { .compatible = "brcm,bcm7278-switch-v4.0",
1350 { .compatible = "brcm,bcm7278-switch-v4.8",
1360 struct device_node *dn = pdev->dev.of_node; in bcm_sf2_sw_probe()
1374 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in bcm_sf2_sw_probe()
1376 return -ENOMEM; in bcm_sf2_sw_probe()
1378 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); in bcm_sf2_sw_probe()
1380 return -ENOMEM; in bcm_sf2_sw_probe()
1382 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); in bcm_sf2_sw_probe()
1384 return -ENOMEM; in bcm_sf2_sw_probe()
1386 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); in bcm_sf2_sw_probe()
1388 return -ENOMEM; in bcm_sf2_sw_probe()
1391 if (!of_id || !of_id->data) in bcm_sf2_sw_probe()
1392 return -EINVAL; in bcm_sf2_sw_probe()
1394 data = of_id->data; in bcm_sf2_sw_probe()
1397 priv->type = data->type; in bcm_sf2_sw_probe()
1398 priv->reg_offsets = data->reg_offsets; in bcm_sf2_sw_probe()
1399 priv->core_reg_align = data->core_reg_align; in bcm_sf2_sw_probe()
1400 priv->num_cfp_rules = data->num_cfp_rules; in bcm_sf2_sw_probe()
1401 priv->num_crossbar_int_ports = data->num_crossbar_int_ports; in bcm_sf2_sw_probe()
1403 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev, in bcm_sf2_sw_probe()
1405 if (IS_ERR(priv->rcdev)) in bcm_sf2_sw_probe()
1406 return PTR_ERR(priv->rcdev); in bcm_sf2_sw_probe()
1408 /* Auto-detection using standard registers will not work, so in bcm_sf2_sw_probe()
1412 pdata->chip_id = priv->type; in bcm_sf2_sw_probe()
1413 dev->pdata = pdata; in bcm_sf2_sw_probe()
1415 priv->dev = dev; in bcm_sf2_sw_probe()
1416 ds = dev->ds; in bcm_sf2_sw_probe()
1417 ds->ops = &bcm_sf2_ops; in bcm_sf2_sw_probe()
1418 ds->phylink_mac_ops = &bcm_sf2_phylink_mac_ops; in bcm_sf2_sw_probe()
1421 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; in bcm_sf2_sw_probe()
1423 dev_set_drvdata(&pdev->dev, priv); in bcm_sf2_sw_probe()
1425 spin_lock_init(&priv->indir_lock); in bcm_sf2_sw_probe()
1426 mutex_init(&priv->cfp.lock); in bcm_sf2_sw_probe()
1427 INIT_LIST_HEAD(&priv->cfp.rules_list); in bcm_sf2_sw_probe()
1432 set_bit(0, priv->cfp.used); in bcm_sf2_sw_probe()
1433 set_bit(0, priv->cfp.unique); in bcm_sf2_sw_probe()
1443 priv->irq0 = irq_of_parse_and_map(dn, 0); in bcm_sf2_sw_probe()
1444 priv->irq1 = irq_of_parse_and_map(dn, 1); in bcm_sf2_sw_probe()
1446 base = &priv->core; in bcm_sf2_sw_probe()
1456 priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch"); in bcm_sf2_sw_probe()
1457 if (IS_ERR(priv->clk)) in bcm_sf2_sw_probe()
1458 return PTR_ERR(priv->clk); in bcm_sf2_sw_probe()
1460 ret = clk_prepare_enable(priv->clk); in bcm_sf2_sw_probe()
1464 priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv"); in bcm_sf2_sw_probe()
1465 if (IS_ERR(priv->clk_mdiv)) { in bcm_sf2_sw_probe()
1466 ret = PTR_ERR(priv->clk_mdiv); in bcm_sf2_sw_probe()
1470 ret = clk_prepare_enable(priv->clk_mdiv); in bcm_sf2_sw_probe()
1482 bcm_sf2_gphy_enable_set(priv->dev->ds, true); in bcm_sf2_sw_probe()
1486 pr_err("failed to register MDIO bus\n"); in bcm_sf2_sw_probe()
1490 bcm_sf2_gphy_enable_set(priv->dev->ds, false); in bcm_sf2_sw_probe()
1501 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, in bcm_sf2_sw_probe()
1508 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, in bcm_sf2_sw_probe()
1523 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; in bcm_sf2_sw_probe()
1524 if (priv->hw_params.num_ports > DSA_MAX_PORTS) in bcm_sf2_sw_probe()
1525 priv->hw_params.num_ports = DSA_MAX_PORTS; in bcm_sf2_sw_probe()
1528 if (of_property_read_u32(dn, "brcm,num-gphy", in bcm_sf2_sw_probe()
1529 &priv->hw_params.num_gphy)) in bcm_sf2_sw_probe()
1530 priv->hw_params.num_gphy = 1; in bcm_sf2_sw_probe()
1533 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & in bcm_sf2_sw_probe()
1535 priv->hw_params.core_rev = (rev & SF2_REV_MASK); in bcm_sf2_sw_probe()
1538 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; in bcm_sf2_sw_probe()
1544 dev_info(&pdev->dev, in bcm_sf2_sw_probe()
1546 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, in bcm_sf2_sw_probe()
1547 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, in bcm_sf2_sw_probe()
1548 priv->irq0, priv->irq1); in bcm_sf2_sw_probe()
1555 clk_disable_unprepare(priv->clk_mdiv); in bcm_sf2_sw_probe()
1557 clk_disable_unprepare(priv->clk); in bcm_sf2_sw_probe()
1568 priv->wol_ports_mask = 0; in bcm_sf2_sw_remove()
1571 dsa_unregister_switch(priv->dev->ds); in bcm_sf2_sw_remove()
1572 bcm_sf2_cfp_exit(priv->dev->ds); in bcm_sf2_sw_remove()
1574 clk_disable_unprepare(priv->clk_mdiv); in bcm_sf2_sw_remove()
1575 clk_disable_unprepare(priv->clk); in bcm_sf2_sw_remove()
1576 if (priv->type == BCM7278_DEVICE_ID) in bcm_sf2_sw_remove()
1577 reset_control_assert(priv->rcdev); in bcm_sf2_sw_remove()
1588 * successful MDIO bus scan to occur. If we did turn off the GPHY in bcm_sf2_sw_shutdown()
1593 if (priv->hw_params.num_gphy == 1) in bcm_sf2_sw_shutdown()
1594 bcm_sf2_gphy_enable_set(priv->dev->ds, true); in bcm_sf2_sw_shutdown()
1596 dsa_switch_shutdown(priv->dev->ds); in bcm_sf2_sw_shutdown()
1606 return dsa_switch_suspend(priv->dev->ds); in bcm_sf2_suspend()
1613 return dsa_switch_resume(priv->dev->ds); in bcm_sf2_resume()
1626 .name = "brcm-sf2",
1636 MODULE_ALIAS("platform:brcm-sf2");