Lines Matching +full:even +full:- +full:numbered
1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
28 #include <linux/can/rx-offload.h>
36 #define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */
37 #define MAX_TX_PRIO 0x3F /* hardware value - do not change */
55 #define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1)
56 #define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
62 * changed while CAN-bus traffic is being received.
64 #define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)
65 #define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1)
93 #define HECC_CANTOC 0x60 /* HECC only: Time-out control */
94 #define HECC_CANTOS 0x64 /* HECC only: Time-out status */
113 #define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */
115 #define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */
194 return priv->tx_head & HECC_TX_MB_MASK; in get_tx_head_mb()
199 return priv->tx_tail & HECC_TX_MB_MASK; in get_tx_tail_mb()
204 return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO; in get_tx_head_prio()
209 __raw_writel(val, priv->hecc_ram + mbxno * 4); in hecc_write_lam()
214 return __raw_readl(priv->hecc_ram + HECC_CANMOTS + mbxno * 4); in hecc_read_stamp()
220 __raw_writel(val, priv->mbx + mbxno * 0x10 + reg); in hecc_write_mbx()
225 return __raw_readl(priv->mbx + mbxno * 0x10 + reg); in hecc_read_mbx()
230 __raw_writel(val, priv->base + reg); in hecc_write()
235 return __raw_readl(priv->base + reg); in hecc_read()
257 struct can_bittiming *bit_timing = &priv->can.bittiming; in ti_hecc_set_btc()
260 can_btc = (bit_timing->phase_seg2 - 1) & 0x7; in ti_hecc_set_btc()
261 can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1) in ti_hecc_set_btc()
263 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) { in ti_hecc_set_btc()
264 if (bit_timing->brp > 4) in ti_hecc_set_btc()
267 netdev_warn(priv->ndev, in ti_hecc_set_btc()
270 can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8; in ti_hecc_set_btc()
271 can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16; in ti_hecc_set_btc()
276 netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc); in ti_hecc_set_btc()
284 if (!priv->reg_xceiver) in ti_hecc_transceiver_switch()
288 return regulator_enable(priv->reg_xceiver); in ti_hecc_transceiver_switch()
290 return regulator_disable(priv->reg_xceiver); in ti_hecc_transceiver_switch()
305 * set and hw seems to be ok even if this bit is not set so in ti_hecc_reset()
310 --cnt; in ti_hecc_reset()
323 /* INFO: CAN net stack handles bus off and hence disabling auto-bus-on in ti_hecc_reset()
328 * set and hw seems to be ok even if this bit is not set so in ti_hecc_reset()
332 --cnt; in ti_hecc_reset()
360 priv->tx_head = HECC_TX_MASK; in ti_hecc_start()
361 priv->tx_tail = HECC_TX_MASK; in ti_hecc_start()
368 mbxno = HECC_MAX_MAILBOXES - 1 - cnt; in ti_hecc_start()
379 hecc_set_bit(priv, HECC_CANMIM, BIT(HECC_MAX_TX_MBOX) - 1); in ti_hecc_start()
381 /* Prevent message over-write to create a rx fifo, but not for in ti_hecc_start()
390 if (priv->use_hecc1int) { in ti_hecc_start()
399 priv->can.state = CAN_STATE_ERROR_ACTIVE; in ti_hecc_start()
413 priv->can.state = CAN_STATE_STOPPED; in ti_hecc_stop()
426 ret = -EOPNOTSUPP; in ti_hecc_do_set_mode()
438 bec->txerr = hecc_read(priv, HECC_CANTEC); in ti_hecc_get_berr_counter()
439 bec->rxerr = hecc_read(priv, HECC_CANREC); in ti_hecc_get_berr_counter()
450 * priority field the highest numbered mailbox is transmitted first.
453 * highest numbered mailbox with highest priority level and move on to the next
456 * until we reach the lowest priority level on the lowest numbered mailbox
458 * restart at highest numbered mailbox with highest priority.
463 * value roll-over happens.
468 struct can_frame *cf = (struct can_frame *)skb->data; in ti_hecc_xmit()
477 spin_lock_irqsave(&priv->mbx_lock, flags); in ti_hecc_xmit()
479 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_xmit()
481 netdev_err(priv->ndev, in ti_hecc_xmit()
483 priv->tx_head, priv->tx_tail); in ti_hecc_xmit()
486 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_xmit()
489 data = cf->len | (get_tx_head_prio(priv) << 8); in ti_hecc_xmit()
490 if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */ in ti_hecc_xmit()
494 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ in ti_hecc_xmit()
495 data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE; in ti_hecc_xmit()
497 data = (cf->can_id & CAN_SFF_MASK) << 18; in ti_hecc_xmit()
500 be32_to_cpu(*(__be32 *)(cf->data))); in ti_hecc_xmit()
501 if (cf->len > 4) in ti_hecc_xmit()
503 be32_to_cpu(*(__be32 *)(cf->data + 4))); in ti_hecc_xmit()
505 *(u32 *)(cf->data + 4) = 0; in ti_hecc_xmit()
508 spin_lock_irqsave(&priv->mbx_lock, flags); in ti_hecc_xmit()
509 --priv->tx_head; in ti_hecc_xmit()
511 (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) { in ti_hecc_xmit()
515 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_xmit()
540 skb = ERR_PTR(-ENOBUFS); in ti_hecc_mailbox_read()
544 skb = alloc_can_skb(offload->dev, &cf); in ti_hecc_mailbox_read()
546 skb = ERR_PTR(-ENOMEM); in ti_hecc_mailbox_read()
552 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; in ti_hecc_mailbox_read()
554 cf->can_id = (data >> 18) & CAN_SFF_MASK; in ti_hecc_mailbox_read()
558 cf->can_id |= CAN_RTR_FLAG; in ti_hecc_mailbox_read()
559 cf->len = can_cc_dlc2len(data & 0xF); in ti_hecc_mailbox_read()
562 *(__be32 *)(cf->data) = cpu_to_be32(data); in ti_hecc_mailbox_read()
563 if (cf->len > 4) { in ti_hecc_mailbox_read()
565 *(__be32 *)(cf->data + 4) = cpu_to_be32(data); in ti_hecc_mailbox_read()
580 * Return an error to let rx-offload discard this CAN frame. in ti_hecc_mailbox_read()
584 skb = ERR_PTR(-ENOBUFS); in ti_hecc_mailbox_read()
606 netdev_err(priv->ndev, in ti_hecc_error()
609 return -ENOMEM; in ti_hecc_error()
612 ++priv->can.can_stats.bus_error; in ti_hecc_error()
613 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; in ti_hecc_error()
615 cf->data[2] |= CAN_ERR_PROT_FORM; in ti_hecc_error()
617 cf->data[2] |= CAN_ERR_PROT_BIT; in ti_hecc_error()
619 cf->data[2] |= CAN_ERR_PROT_STUFF; in ti_hecc_error()
621 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; in ti_hecc_error()
623 cf->data[3] = CAN_ERR_PROT_LOC_ACK; in ti_hecc_error()
626 err = can_rx_offload_queue_timestamp(&priv->offload, skb, in ti_hecc_error()
629 ndev->stats.rx_fifo_errors++; in ti_hecc_error()
647 skb = alloc_can_err_skb(priv->ndev, &cf); in ti_hecc_change_state()
649 priv->can.state = max(tx_state, rx_state); in ti_hecc_change_state()
653 can_change_state(priv->ndev, cf, tx_state, rx_state); in ti_hecc_change_state()
656 cf->can_id |= CAN_ERR_CNT; in ti_hecc_change_state()
657 cf->data[6] = hecc_read(priv, HECC_CANTEC); in ti_hecc_change_state()
658 cf->data[7] = hecc_read(priv, HECC_CANREC); in ti_hecc_change_state()
662 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); in ti_hecc_change_state()
664 ndev->stats.rx_fifo_errors++; in ti_hecc_change_state()
671 struct net_device_stats *stats = &ndev->stats; in ti_hecc_interrupt()
677 priv->use_hecc1int ? in ti_hecc_interrupt()
696 netdev_dbg(priv->ndev, "Error Warning interrupt\n"); in ti_hecc_interrupt()
704 netdev_dbg(priv->ndev, "Error passive interrupt\n"); in ti_hecc_interrupt()
712 netdev_dbg(priv->ndev, "Bus off interrupt\n"); in ti_hecc_interrupt()
719 } else if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE)) { in ti_hecc_interrupt()
731 if (new_state < priv->can.state) { in ti_hecc_interrupt()
739 while (priv->tx_tail - priv->tx_head > 0) { in ti_hecc_interrupt()
745 spin_lock_irqsave(&priv->mbx_lock, flags); in ti_hecc_interrupt()
747 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_interrupt()
749 stats->tx_bytes += in ti_hecc_interrupt()
750 can_rx_offload_get_echo_skb_queue_timestamp(&priv->offload, in ti_hecc_interrupt()
752 stats->tx_packets++; in ti_hecc_interrupt()
753 --priv->tx_tail; in ti_hecc_interrupt()
756 /* restart queue if wrap-up or if queue stalled on last pkt */ in ti_hecc_interrupt()
757 if ((priv->tx_head == priv->tx_tail && in ti_hecc_interrupt()
758 ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) || in ti_hecc_interrupt()
759 (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) && in ti_hecc_interrupt()
760 ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK))) in ti_hecc_interrupt()
765 can_rx_offload_irq_offload_timestamp(&priv->offload, in ti_hecc_interrupt()
770 /* clear all interrupt conditions - read back to avoid spurious ints */ in ti_hecc_interrupt()
771 if (priv->use_hecc1int) { in ti_hecc_interrupt()
779 can_rx_offload_irq_finish(&priv->offload); in ti_hecc_interrupt()
789 err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED, in ti_hecc_open()
790 ndev->name, ndev); in ti_hecc_open()
803 free_irq(ndev->irq, ndev); in ti_hecc_open()
808 can_rx_offload_enable(&priv->offload); in ti_hecc_open()
819 can_rx_offload_disable(&priv->offload); in ti_hecc_close()
821 free_irq(ndev->irq, ndev); in ti_hecc_close()
841 .compatible = "ti,am3517-hecc",
851 struct device_node *np = pdev->dev.of_node; in ti_hecc_probe()
853 int err = -ENODEV; in ti_hecc_probe()
856 return -EINVAL; in ti_hecc_probe()
858 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); in ti_hecc_probe()
859 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER) in ti_hecc_probe()
860 return -EPROBE_DEFER; in ti_hecc_probe()
866 dev_err(&pdev->dev, "alloc_candev failed\n"); in ti_hecc_probe()
867 return -ENOMEM; in ti_hecc_probe()
872 priv->base = devm_platform_ioremap_resource_byname(pdev, "hecc"); in ti_hecc_probe()
873 if (IS_ERR(priv->base)) { in ti_hecc_probe()
874 dev_err(&pdev->dev, "hecc ioremap failed\n"); in ti_hecc_probe()
875 err = PTR_ERR(priv->base); in ti_hecc_probe()
879 /* handle hecc-ram memory */ in ti_hecc_probe()
880 priv->hecc_ram = devm_platform_ioremap_resource_byname(pdev, in ti_hecc_probe()
881 "hecc-ram"); in ti_hecc_probe()
882 if (IS_ERR(priv->hecc_ram)) { in ti_hecc_probe()
883 dev_err(&pdev->dev, "hecc-ram ioremap failed\n"); in ti_hecc_probe()
884 err = PTR_ERR(priv->hecc_ram); in ti_hecc_probe()
889 priv->mbx = devm_platform_ioremap_resource_byname(pdev, "mbx"); in ti_hecc_probe()
890 if (IS_ERR(priv->mbx)) { in ti_hecc_probe()
891 dev_err(&pdev->dev, "mbx ioremap failed\n"); in ti_hecc_probe()
892 err = PTR_ERR(priv->mbx); in ti_hecc_probe()
896 ndev->irq = platform_get_irq(pdev, 0); in ti_hecc_probe()
897 if (ndev->irq < 0) { in ti_hecc_probe()
898 err = ndev->irq; in ti_hecc_probe()
902 priv->ndev = ndev; in ti_hecc_probe()
903 priv->reg_xceiver = reg_xceiver; in ti_hecc_probe()
904 priv->use_hecc1int = of_property_read_bool(np, "ti,use-hecc1int"); in ti_hecc_probe()
906 priv->can.bittiming_const = &ti_hecc_bittiming_const; in ti_hecc_probe()
907 priv->can.do_set_mode = ti_hecc_do_set_mode; in ti_hecc_probe()
908 priv->can.do_get_berr_counter = ti_hecc_get_berr_counter; in ti_hecc_probe()
909 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; in ti_hecc_probe()
911 spin_lock_init(&priv->mbx_lock); in ti_hecc_probe()
912 ndev->flags |= IFF_ECHO; in ti_hecc_probe()
914 SET_NETDEV_DEV(ndev, &pdev->dev); in ti_hecc_probe()
915 ndev->netdev_ops = &ti_hecc_netdev_ops; in ti_hecc_probe()
916 ndev->ethtool_ops = &ti_hecc_ethtool_ops; in ti_hecc_probe()
918 priv->clk = clk_get(&pdev->dev, "hecc_ck"); in ti_hecc_probe()
919 if (IS_ERR(priv->clk)) { in ti_hecc_probe()
920 dev_err(&pdev->dev, "No clock available\n"); in ti_hecc_probe()
921 err = PTR_ERR(priv->clk); in ti_hecc_probe()
922 priv->clk = NULL; in ti_hecc_probe()
925 priv->can.clock.freq = clk_get_rate(priv->clk); in ti_hecc_probe()
927 err = clk_prepare_enable(priv->clk); in ti_hecc_probe()
929 dev_err(&pdev->dev, "clk_prepare_enable() failed\n"); in ti_hecc_probe()
933 priv->offload.mailbox_read = ti_hecc_mailbox_read; in ti_hecc_probe()
934 priv->offload.mb_first = HECC_RX_FIRST_MBOX; in ti_hecc_probe()
935 priv->offload.mb_last = HECC_RX_LAST_MBOX; in ti_hecc_probe()
936 err = can_rx_offload_add_timestamp(ndev, &priv->offload); in ti_hecc_probe()
938 dev_err(&pdev->dev, "can_rx_offload_add_timestamp() failed\n"); in ti_hecc_probe()
944 dev_err(&pdev->dev, "register_candev() failed\n"); in ti_hecc_probe()
948 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n", in ti_hecc_probe()
949 priv->base, (u32)ndev->irq); in ti_hecc_probe()
954 can_rx_offload_del(&priv->offload); in ti_hecc_probe()
956 clk_disable_unprepare(priv->clk); in ti_hecc_probe()
958 clk_put(priv->clk); in ti_hecc_probe()
971 clk_disable_unprepare(priv->clk); in ti_hecc_remove()
972 clk_put(priv->clk); in ti_hecc_remove()
973 can_rx_offload_del(&priv->offload); in ti_hecc_remove()
989 priv->can.state = CAN_STATE_SLEEPING; in ti_hecc_suspend()
991 clk_disable_unprepare(priv->clk); in ti_hecc_suspend()
1002 err = clk_prepare_enable(priv->clk); in ti_hecc_resume()
1007 priv->can.state = CAN_STATE_ERROR_ACTIVE; in ti_hecc_resume()