Lines Matching +full:64 +full:bit
25 * MX25 FlexCAN2 03.00.00.00 no no no no no no 64
26 * MX28 FlexCAN2 03.00.04.00 yes yes no no no no 64
27 * MX35 FlexCAN2 03.00.00.00 no no no no no no 64
28 * MX53 FlexCAN2 03.00.00.00 yes no no no no no 64
29 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes no 64
30 * MX8QM FlexCAN3 03.00.23.00 yes yes no no yes yes 64
31 * MX8MP FlexCAN3 03.00.17.01 yes yes no yes yes yes 64
32 * VF610 FlexCAN3 ? no yes no yes yes? no 64
33 * LS1021A FlexCAN2 03.00.04.00 no yes no no yes no 64
34 * LX2160A FlexCAN3 03.00.23.00 no yes no yes yes yes 64
40 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1)
42 #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2)
43 /* Enable EACEN and RRS bit in ctrl2 */
44 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3)
46 #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4)
48 #define FLEXCAN_QUIRK_USE_RX_MAILBOX BIT(5)
50 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6)
52 #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7)
54 #define FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR BIT(8)
56 #define FLEXCAN_QUIRK_SUPPORT_FD BIT(9)
58 #define FLEXCAN_QUIRK_SUPPORT_ECC BIT(10)
60 #define FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW BIT(11)
62 #define FLEXCAN_QUIRK_NR_IRQ_3 BIT(12)
64 #define FLEXCAN_QUIRK_NR_MB_16 BIT(13)
66 #define FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX BIT(14)
68 #define FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR BIT(15)
70 #define FLEXCAN_QUIRK_SUPPORT_RX_FIFO BIT(16)
72 #define FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI BIT(17)