Lines Matching +full:0 +full:x4d
15 #define USE_CLSR BIT(0)
18 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
19 #define SPINOR_OP_CLPEF 0x82 /* Clear program/erase failure flags */
20 #define SPINOR_OP_CYPRESS_DIE_ERASE 0x61 /* Chip (die) erase */
21 #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
22 #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
23 #define SPINOR_REG_CYPRESS_VREG 0x00800000
24 #define SPINOR_REG_CYPRESS_STR1 0x0
27 #define SPINOR_REG_CYPRESS_CFR1 0x2
29 #define SPINOR_REG_CYPRESS_CFR2 0x3
32 #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK GENMASK(3, 0)
33 #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb
35 #define SPINOR_REG_CYPRESS_CFR3 0x4
37 #define SPINOR_REG_CYPRESS_CFR5 0x6
40 #define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0)
45 #define SPINOR_OP_CYPRESS_RD_FAST 0xee
46 #define SPINOR_REG_CYPRESS_ARCFN 0x00000006
50 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 0), \
51 SPI_MEM_OP_ADDR(naddr, addr, 0), \
53 SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
56 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 0), \
57 SPI_MEM_OP_ADDR(naddr, addr, 0), \
58 SPI_MEM_OP_DUMMY(ndummy, 0), \
59 SPI_MEM_OP_DATA_IN(1, buf, 0))
62 SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
93 NULL, 0); in spansion_nor_clear_sr()
105 0, nor->bouncebuf); in cypress_nor_sr_ready_and_clear_reg()
117 if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { in cypress_nor_sr_ready_and_clear_reg()
118 if (nor->bouncebuf[0] & SR_E_ERR) in cypress_nor_sr_ready_and_clear_reg()
132 return !(nor->bouncebuf[0] & SR_WIP); in cypress_nor_sr_ready_and_clear_reg()
140 * Return: 1 if ready, 0 if not ready, -errno on errors.
149 for (i = 0; i < params->n_dice; i++) { in cypress_nor_sr_ready_and_clear()
152 if (ret < 0) in cypress_nor_sr_ready_and_clear()
154 else if (ret == 0) in cypress_nor_sr_ready_and_clear()
155 return 0; in cypress_nor_sr_ready_and_clear()
169 CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, buf); in cypress_nor_set_memlat()
188 return 0; in cypress_nor_set_memlat()
197 buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN; in cypress_nor_set_octal_dtr_bits()
212 for (i = 0; i < params->n_dice; i++) { in cypress_nor_octal_dtr_en()
235 return 0; in cypress_nor_octal_dtr_en()
246 * just initialize the value to 0 and let the transaction go on. in cypress_nor_set_single_spi_bits()
248 buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS; in cypress_nor_set_single_spi_bits()
249 buf[1] = 0; in cypress_nor_set_single_spi_bits()
262 for (i = 0; i < params->n_dice; i++) { in cypress_nor_octal_dtr_dis()
270 ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); in cypress_nor_octal_dtr_dis()
279 return 0; in cypress_nor_octal_dtr_dis()
290 CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, in cypress_nor_quad_enable_volatile_reg()
297 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1_QUAD_EN) in cypress_nor_quad_enable_volatile_reg()
298 return 0; in cypress_nor_quad_enable_volatile_reg()
301 nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1_QUAD_EN; in cypress_nor_quad_enable_volatile_reg()
309 cfr1v_written = nor->bouncebuf[0]; in cypress_nor_quad_enable_volatile_reg()
313 CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, in cypress_nor_quad_enable_volatile_reg()
319 if (nor->bouncebuf[0] != cfr1v_written) { in cypress_nor_quad_enable_volatile_reg()
324 return 0; in cypress_nor_quad_enable_volatile_reg()
339 * Return: 0 on success, -errno otherwise.
348 for (i = 0; i < params->n_dice; i++) { in cypress_nor_quad_enable_volatile()
355 return 0; in cypress_nor_quad_enable_volatile()
369 * Return: 0 on success, -errno otherwise.
375 CYPRESS_NOR_RD_ANY_REG_OP(3, SPINOR_REG_CYPRESS_STR1V, 0, in cypress_nor_determine_addr_mode_by_sr1()
388 is3byte = (nor->bouncebuf[0] == nor->bouncebuf[1]); in cypress_nor_determine_addr_mode_by_sr1()
391 CYPRESS_NOR_RD_ANY_REG_OP(4, SPINOR_REG_CYPRESS_STR1V, 0, in cypress_nor_determine_addr_mode_by_sr1()
397 is4byte = (nor->bouncebuf[0] == nor->bouncebuf[1]); in cypress_nor_determine_addr_mode_by_sr1()
406 return 0; in cypress_nor_determine_addr_mode_by_sr1()
418 * Return: 0 on success, -errno otherwise.
450 0, nor->bouncebuf); in cypress_nor_set_addr_mode_nbytes()
455 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR2_ADRBYT) { in cypress_nor_set_addr_mode_nbytes()
466 return 0; in cypress_nor_set_addr_mode_nbytes()
477 * Return: 0 on success, -errno otherwise.
483 0, 0, nor->bouncebuf); in cypress_nor_get_page_size()
493 for (i = 0; i < params->n_dice; i++) { in cypress_nor_get_page_size()
500 if (!(nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3_PGSZ)) in cypress_nor_get_page_size()
501 return 0; in cypress_nor_get_page_size()
506 return 0; in cypress_nor_get_page_size()
541 /* ARCFN value must be 0 if uniform sector is selected */ in s25fs256t_post_bfpt_fixup()
542 if (nor->bouncebuf[0]) in s25fs256t_post_bfpt_fixup()
545 return 0; in s25fs256t_post_bfpt_fixup()
561 params->vreg_offset[0] = SPINOR_REG_CYPRESS_VREG; in s25fs256t_post_sfdp_fixup()
577 return 0; in s25fs256t_late_init()
600 return 0; in s25hx_t_post_bfpt_fixup()
623 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { in s25hx_t_post_sfdp_fixup()
649 return 0; in s25hx_t_late_init()
666 * Return: 0 on success, -errno otherwise.
690 * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. in s28hx_t_post_sfdp_fixup()
692 if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0) in s28hx_t_post_sfdp_fixup()
708 * address bytes needed for Read Status Register command as 0 but the in s28hx_t_post_sfdp_fixup()
731 return 0; in s28hx_t_late_init()
753 return 0; in s25fs_s_nor_post_bfpt_fixups()
762 .id = SNOR_ID(0x01, 0x02, 0x12),
766 .id = SNOR_ID(0x01, 0x02, 0x13),
770 .id = SNOR_ID(0x01, 0x02, 0x14),
774 .id = SNOR_ID(0x01, 0x02, 0x15, 0x4d, 0x00),
779 .id = SNOR_ID(0x01, 0x02, 0x15),
783 .id = SNOR_ID(0x01, 0x02, 0x16, 0x4d, 0x00),
788 .id = SNOR_ID(0x01, 0x02, 0x16),
792 .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x00, 0x80),
799 .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x00, 0x81),
806 .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x01, 0x80),
812 .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x01, 0x81),
818 .id = SNOR_ID(0x01, 0x02, 0x20, 0x4d, 0x00, 0x80),
826 .id = SNOR_ID(0x01, 0x02, 0x20, 0x4d, 0x00, 0x81),
834 .id = SNOR_ID(0x01, 0x20, 0x18, 0x03, 0x00),
839 .id = SNOR_ID(0x01, 0x20, 0x18, 0x03, 0x01),
843 .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x00, 0x80),
850 .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x00),
857 .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x80),
863 .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x81),
870 .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01),
876 .id = SNOR_ID(0x01, 0x40, 0x13),
881 .id = SNOR_ID(0x01, 0x40, 0x14),
886 .id = SNOR_ID(0x01, 0x40, 0x15),
891 .id = SNOR_ID(0x01, 0x40, 0x16),
896 .id = SNOR_ID(0x01, 0x40, 0x17),
901 .id = SNOR_ID(0x01, 0x60, 0x17),
907 .id = SNOR_ID(0x01, 0x60, 0x18),
913 .id = SNOR_ID(0x01, 0x60, 0x19),
919 .id = SNOR_ID(0x04, 0x2c, 0xc2, 0x7f, 0x7f, 0x7f),
925 .id = SNOR_ID(0x34, 0x2a, 0x1a, 0x0f, 0x03, 0x90),
930 .id = SNOR_ID(0x34, 0x2a, 0x1b, 0x0f, 0x03, 0x90),
935 .id = SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90),
940 .id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90),
945 .id = SNOR_ID(0x34, 0x2b, 0x1a, 0x0f, 0x03, 0x90),
950 .id = SNOR_ID(0x34, 0x2b, 0x1b, 0x0f, 0x03, 0x90),
955 .id = SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90),
960 .id = SNOR_ID(0x34, 0x5a, 0x1a),
965 .id = SNOR_ID(0x34, 0x5a, 0x1b),
970 .id = SNOR_ID(0x34, 0x5b, 0x19),
974 .id = SNOR_ID(0x34, 0x5b, 0x1a),
979 .id = SNOR_ID(0x34, 0x5b, 0x1b),
984 .id = SNOR_ID(0x34, 0x5b, 0x1c),
989 .id = SNOR_ID(0xef, 0x40, 0x13),
994 .id = SNOR_ID(0xef, 0x40, 0x14),
999 .id = SNOR_ID(0xef, 0x40, 0x15),
1004 .id = SNOR_ID(0xef, 0x40, 0x17),
1016 * Return: 1 if ready, 0 if not ready, -errno on errors.
1026 if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { in spansion_nor_sr_ready_and_clear()
1027 if (nor->bouncebuf[0] & SR_E_ERR) in spansion_nor_sr_ready_and_clear()
1047 return !(nor->bouncebuf[0] & SR_WIP); in spansion_nor_sr_ready_and_clear()
1079 return 0; in spansion_nor_late_init()