Lines Matching +full:quad +full:- +full:phase

1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define SFDP_DWORD(i)		((i) - 1)
56  * Quad Enable Requirements (QER):
57  * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
59  *         instruction phase.
60  * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
63  *         Writing only one byte to the status register has the side-effect of
67  * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
70  * - 011b: QE is bit 7 of status register 2. It is set via Write status
74  * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
79  * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
132 #define BFPT_DWORD18_CMD_EXT_16B		(0x3UL << 29) /* 16-bit opcode */