Lines Matching +full:quad +full:- +full:phase
1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mtd/spi-nor.h>
30 * For everything but full-chip erase; probably could be much smaller, but kept
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
47 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
60 switch (nor->cmd_ext_type) { in spi_nor_get_cmd_ext()
62 return ~op->cmd.opcode; in spi_nor_get_cmd_ext()
65 return op->cmd.opcode; in spi_nor_get_cmd_ext()
68 dev_err(nor->dev, "Unknown command extension type\n"); in spi_nor_get_cmd_ext()
74 * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op.
86 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto); in spi_nor_spimem_setup_op()
88 if (op->addr.nbytes) in spi_nor_spimem_setup_op()
89 op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto); in spi_nor_spimem_setup_op()
91 if (op->dummy.nbytes) in spi_nor_spimem_setup_op()
92 op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto); in spi_nor_spimem_setup_op()
94 if (op->data.nbytes) in spi_nor_spimem_setup_op()
95 op->data.buswidth = spi_nor_get_protocol_data_nbits(proto); in spi_nor_spimem_setup_op()
101 * something like 4S-4D-4D, but SPI NOR can't. So, set all 4 in spi_nor_spimem_setup_op()
104 op->cmd.dtr = true; in spi_nor_spimem_setup_op()
105 op->addr.dtr = true; in spi_nor_spimem_setup_op()
106 op->dummy.dtr = true; in spi_nor_spimem_setup_op()
107 op->data.dtr = true; in spi_nor_spimem_setup_op()
110 op->dummy.nbytes *= 2; in spi_nor_spimem_setup_op()
113 op->cmd.opcode = (op->cmd.opcode << 8) | ext; in spi_nor_spimem_setup_op()
114 op->cmd.nbytes = 2; in spi_nor_spimem_setup_op()
119 * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data
130 /* op->data.buf.in occupies the same memory as op->data.buf.out */ in spi_nor_spimem_bounce()
131 if (object_is_on_stack(op->data.buf.in) || in spi_nor_spimem_bounce()
132 !virt_addr_valid(op->data.buf.in)) { in spi_nor_spimem_bounce()
133 if (op->data.nbytes > nor->bouncebuf_size) in spi_nor_spimem_bounce()
134 op->data.nbytes = nor->bouncebuf_size; in spi_nor_spimem_bounce()
135 op->data.buf.in = nor->bouncebuf; in spi_nor_spimem_bounce()
143 * spi_nor_spimem_exec_op() - execute a memory operation
147 * Return: 0 on success, -error otherwise.
153 error = spi_mem_adjust_op_size(nor->spimem, op); in spi_nor_spimem_exec_op()
157 return spi_mem_exec_op(nor->spimem, op); in spi_nor_spimem_exec_op()
163 if (spi_nor_protocol_is_dtr(nor->reg_proto)) in spi_nor_controller_ops_read_reg()
164 return -EOPNOTSUPP; in spi_nor_controller_ops_read_reg()
166 return nor->controller_ops->read_reg(nor, opcode, buf, len); in spi_nor_controller_ops_read_reg()
172 if (spi_nor_protocol_is_dtr(nor->reg_proto)) in spi_nor_controller_ops_write_reg()
173 return -EOPNOTSUPP; in spi_nor_controller_ops_write_reg()
175 return nor->controller_ops->write_reg(nor, opcode, buf, len); in spi_nor_controller_ops_write_reg()
180 if (spi_nor_protocol_is_dtr(nor->reg_proto)) in spi_nor_controller_ops_erase()
181 return -EOPNOTSUPP; in spi_nor_controller_ops_erase()
183 return nor->controller_ops->erase(nor, offs); in spi_nor_controller_ops_erase()
187 * spi_nor_spimem_read_data() - read data from flash's memory region via
188 * spi-mem
194 * Return: number of bytes read successfully, -errno otherwise
200 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0), in spi_nor_spimem_read_data()
201 SPI_MEM_OP_ADDR(nor->addr_nbytes, from, 0), in spi_nor_spimem_read_data()
202 SPI_MEM_OP_DUMMY(nor->read_dummy, 0), in spi_nor_spimem_read_data()
208 spi_nor_spimem_setup_op(nor, &op, nor->read_proto); in spi_nor_spimem_read_data()
211 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; in spi_nor_spimem_read_data()
212 if (spi_nor_protocol_is_dtr(nor->read_proto)) in spi_nor_spimem_read_data()
217 if (nor->dirmap.rdesc) { in spi_nor_spimem_read_data()
218 nbytes = spi_mem_dirmap_read(nor->dirmap.rdesc, op.addr.val, in spi_nor_spimem_read_data()
234 * spi_nor_read_data() - read data from flash memory
240 * Return: number of bytes read successfully, -errno otherwise
244 if (nor->spimem) in spi_nor_read_data()
247 return nor->controller_ops->read(nor, from, len, buf); in spi_nor_read_data()
251 * spi_nor_spimem_write_data() - write data to flash memory via
252 * spi-mem
258 * Return: number of bytes written successfully, -errno otherwise
264 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0), in spi_nor_spimem_write_data()
265 SPI_MEM_OP_ADDR(nor->addr_nbytes, to, 0), in spi_nor_spimem_write_data()
271 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) in spi_nor_spimem_write_data()
274 spi_nor_spimem_setup_op(nor, &op, nor->write_proto); in spi_nor_spimem_write_data()
277 memcpy(nor->bouncebuf, buf, op.data.nbytes); in spi_nor_spimem_write_data()
279 if (nor->dirmap.wdesc) { in spi_nor_spimem_write_data()
280 nbytes = spi_mem_dirmap_write(nor->dirmap.wdesc, op.addr.val, in spi_nor_spimem_write_data()
293 * spi_nor_write_data() - write data to flash memory
299 * Return: number of bytes written successfully, -errno otherwise
304 if (nor->spimem) in spi_nor_write_data()
307 return nor->controller_ops->write(nor, to, len, buf); in spi_nor_write_data()
311 * spi_nor_read_any_reg() - read any register from flash memory, nonvolatile or
314 * @op: SPI memory operation. op->data.buf must be DMA-able.
317 * Return: zero on success, -errno otherwise
322 if (!nor->spimem) in spi_nor_read_any_reg()
323 return -EOPNOTSUPP; in spi_nor_read_any_reg()
330 * spi_nor_write_any_volatile_reg() - write any volatile register to flash
333 * @op: SPI memory operation. op->data.buf must be DMA-able.
339 * Return: zero on success, -errno otherwise
346 if (!nor->spimem) in spi_nor_write_any_volatile_reg()
347 return -EOPNOTSUPP; in spi_nor_write_any_volatile_reg()
357 * spi_nor_write_enable() - Set write enable latch with Write Enable command.
360 * Return: 0 on success, -errno otherwise.
366 if (nor->spimem) { in spi_nor_write_enable()
369 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spi_nor_write_enable()
371 ret = spi_mem_exec_op(nor->spimem, &op); in spi_nor_write_enable()
378 dev_dbg(nor->dev, "error %d on Write Enable\n", ret); in spi_nor_write_enable()
384 * spi_nor_write_disable() - Send Write Disable instruction to the chip.
387 * Return: 0 on success, -errno otherwise.
393 if (nor->spimem) { in spi_nor_write_disable()
396 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spi_nor_write_disable()
398 ret = spi_mem_exec_op(nor->spimem, &op); in spi_nor_write_disable()
405 dev_dbg(nor->dev, "error %d on Write Disable\n", ret); in spi_nor_write_disable()
411 * spi_nor_read_id() - Read the JEDEC ID.
417 * @id: pointer to a DMA-able buffer where the value of the JEDEC ID
421 * Return: 0 on success, -errno otherwise.
428 if (nor->spimem) { in spi_nor_read_id()
433 ret = spi_mem_exec_op(nor->spimem, &op); in spi_nor_read_id()
435 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id, in spi_nor_read_id()
442 * spi_nor_read_sr() - Read the Status Register.
444 * @sr: pointer to a DMA-able buffer where the value of the
447 * Return: 0 on success, -errno otherwise.
453 if (nor->spimem) { in spi_nor_read_sr()
456 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { in spi_nor_read_sr()
457 op.addr.nbytes = nor->params->rdsr_addr_nbytes; in spi_nor_read_sr()
458 op.dummy.nbytes = nor->params->rdsr_dummy; in spi_nor_read_sr()
466 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spi_nor_read_sr()
468 ret = spi_mem_exec_op(nor->spimem, &op); in spi_nor_read_sr()
475 dev_dbg(nor->dev, "error %d reading SR\n", ret); in spi_nor_read_sr()
481 * spi_nor_read_cr() - Read the Configuration Register using the
484 * @cr: pointer to a DMA-able buffer where the value of the
487 * Return: 0 on success, -errno otherwise.
493 if (nor->spimem) { in spi_nor_read_cr()
496 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spi_nor_read_cr()
498 ret = spi_mem_exec_op(nor->spimem, &op); in spi_nor_read_cr()
505 dev_dbg(nor->dev, "error %d reading CR\n", ret); in spi_nor_read_cr()
511 * spi_nor_set_4byte_addr_mode_en4b_ex4b() - Enter/Exit 4-byte address mode
515 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
518 * Return: 0 on success, -errno otherwise.
524 if (nor->spimem) { in spi_nor_set_4byte_addr_mode_en4b_ex4b()
527 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spi_nor_set_4byte_addr_mode_en4b_ex4b()
529 ret = spi_mem_exec_op(nor->spimem, &op); in spi_nor_set_4byte_addr_mode_en4b_ex4b()
538 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); in spi_nor_set_4byte_addr_mode_en4b_ex4b()
544 * spi_nor_set_4byte_addr_mode_wren_en4b_ex4b() - Set 4-byte address mode using
548 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
551 * Return: 0 on success, -errno otherwise.
569 * spi_nor_set_4byte_addr_mode_brwr() - Set 4-byte address mode using
572 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
575 * 8-bit volatile bank register used to define A[30:A24] bits. MSB (bit[7]) is
576 * used to enable/disable 4-byte address mode. When MSB is set to ‘1’, 4-byte
580 * Return: 0 on success, -errno otherwise.
586 nor->bouncebuf[0] = enable << 7; in spi_nor_set_4byte_addr_mode_brwr()
588 if (nor->spimem) { in spi_nor_set_4byte_addr_mode_brwr()
589 struct spi_mem_op op = SPI_NOR_BRWR_OP(nor->bouncebuf); in spi_nor_set_4byte_addr_mode_brwr()
591 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spi_nor_set_4byte_addr_mode_brwr()
593 ret = spi_mem_exec_op(nor->spimem, &op); in spi_nor_set_4byte_addr_mode_brwr()
596 nor->bouncebuf, 1); in spi_nor_set_4byte_addr_mode_brwr()
600 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); in spi_nor_set_4byte_addr_mode_brwr()
606 * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready
610 * Return: 1 if ready, 0 if not ready, -errno on errors.
616 ret = spi_nor_read_sr(nor, nor->bouncebuf); in spi_nor_sr_ready()
620 return !(nor->bouncebuf[0] & SR_WIP); in spi_nor_sr_ready()
624 * spi_nor_use_parallel_locking() - Checks if RWW locking scheme shall be used
631 return nor->flags & SNOR_F_RWW; in spi_nor_use_parallel_locking()
637 struct spi_nor_rww *rww = &nor->rww; in spi_nor_rww_start_rdst()
638 int ret = -EAGAIN; in spi_nor_rww_start_rdst()
640 mutex_lock(&nor->lock); in spi_nor_rww_start_rdst()
642 if (rww->ongoing_io || rww->ongoing_rd) in spi_nor_rww_start_rdst()
645 rww->ongoing_io = true; in spi_nor_rww_start_rdst()
646 rww->ongoing_rd = true; in spi_nor_rww_start_rdst()
650 mutex_unlock(&nor->lock); in spi_nor_rww_start_rdst()
656 struct spi_nor_rww *rww = &nor->rww; in spi_nor_rww_end_rdst()
658 mutex_lock(&nor->lock); in spi_nor_rww_end_rdst()
660 rww->ongoing_io = false; in spi_nor_rww_end_rdst()
661 rww->ongoing_rd = false; in spi_nor_rww_end_rdst()
663 mutex_unlock(&nor->lock); in spi_nor_rww_end_rdst()
678 wake_up(&nor->rww.wait); in spi_nor_unlock_rdst()
683 * spi_nor_ready() - Query the flash to see if it is ready for new commands.
686 * Return: 1 if ready, 0 if not ready, -errno on errors.
697 if (nor->params->ready) in spi_nor_ready()
698 ret = nor->params->ready(nor); in spi_nor_ready()
708 * spi_nor_wait_till_ready_with_timeout() - Service routine to read the
713 * Return: 0 on success, -errno otherwise.
736 dev_dbg(nor->dev, "flash operation timed out\n"); in spi_nor_wait_till_ready_with_timeout()
738 return -ETIMEDOUT; in spi_nor_wait_till_ready_with_timeout()
742 * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the
746 * Return: 0 on success, -errno otherwise.
755 * spi_nor_global_block_unlock() - Unlock Global Block Protection.
758 * Return: 0 on success, -errno otherwise.
768 if (nor->spimem) { in spi_nor_global_block_unlock()
771 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spi_nor_global_block_unlock()
773 ret = spi_mem_exec_op(nor->spimem, &op); in spi_nor_global_block_unlock()
780 dev_dbg(nor->dev, "error %d on Global Block Unlock\n", ret); in spi_nor_global_block_unlock()
788 * spi_nor_write_sr() - Write the Status Register.
790 * @sr: pointer to DMA-able buffer to write to the Status Register.
793 * Return: 0 on success, -errno otherwise.
803 if (nor->spimem) { in spi_nor_write_sr()
806 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spi_nor_write_sr()
808 ret = spi_mem_exec_op(nor->spimem, &op); in spi_nor_write_sr()
815 dev_dbg(nor->dev, "error %d writing SR\n", ret); in spi_nor_write_sr()
823 * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and
828 * Return: 0 on success, -errno otherwise.
834 nor->bouncebuf[0] = sr1; in spi_nor_write_sr1_and_check()
836 ret = spi_nor_write_sr(nor, nor->bouncebuf, 1); in spi_nor_write_sr1_and_check()
840 ret = spi_nor_read_sr(nor, nor->bouncebuf); in spi_nor_write_sr1_and_check()
844 if (nor->bouncebuf[0] != sr1) { in spi_nor_write_sr1_and_check()
845 dev_dbg(nor->dev, "SR1: read back test failed\n"); in spi_nor_write_sr1_and_check()
846 return -EIO; in spi_nor_write_sr1_and_check()
853 * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the
855 * Register 1 match the received value, and that the 16-bit Write did not
860 * Return: 0 on success, -errno otherwise.
865 u8 *sr_cr = nor->bouncebuf; in spi_nor_write_16bit_sr_and_check()
869 if (!(nor->flags & SNOR_F_NO_READ_CR)) { in spi_nor_write_16bit_sr_and_check()
873 } else if (spi_nor_get_protocol_width(nor->read_proto) == 4 && in spi_nor_write_16bit_sr_and_check()
874 spi_nor_get_protocol_width(nor->write_proto) == 4 && in spi_nor_write_16bit_sr_and_check()
875 nor->params->quad_enable) { in spi_nor_write_16bit_sr_and_check()
879 * change the value of the SR2 Quad Enable bit. in spi_nor_write_16bit_sr_and_check()
881 * When the Quad Enable method is set and the buswidth is 4, we in spi_nor_write_16bit_sr_and_check()
883 * consequence of the nor->params->quad_enable() call. in spi_nor_write_16bit_sr_and_check()
886 * bits 22:20, the 16-bit Write Status (01h) command is in spi_nor_write_16bit_sr_and_check()
906 dev_dbg(nor->dev, "SR: Read back test failed\n"); in spi_nor_write_16bit_sr_and_check()
907 return -EIO; in spi_nor_write_16bit_sr_and_check()
910 if (nor->flags & SNOR_F_NO_READ_CR) in spi_nor_write_16bit_sr_and_check()
920 dev_dbg(nor->dev, "CR: read back test failed\n"); in spi_nor_write_16bit_sr_and_check()
921 return -EIO; in spi_nor_write_16bit_sr_and_check()
928 * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the
930 * Configuration Register match the received value, and that the 16-bit Write
935 * Return: 0 on success, -errno otherwise.
940 u8 *sr_cr = nor->bouncebuf; in spi_nor_write_16bit_cr_and_check()
961 dev_dbg(nor->dev, "SR: Read back test failed\n"); in spi_nor_write_16bit_cr_and_check()
962 return -EIO; in spi_nor_write_16bit_cr_and_check()
965 if (nor->flags & SNOR_F_NO_READ_CR) in spi_nor_write_16bit_cr_and_check()
973 dev_dbg(nor->dev, "CR: read back test failed\n"); in spi_nor_write_16bit_cr_and_check()
974 return -EIO; in spi_nor_write_16bit_cr_and_check()
981 * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that
987 * Return: 0 on success, -errno otherwise.
991 if (nor->flags & SNOR_F_HAS_16BIT_SR) in spi_nor_write_sr_and_check()
998 * spi_nor_write_sr2() - Write the Status Register 2 using the
1001 * @sr2: pointer to DMA-able buffer to write to the Status Register 2.
1003 * Return: 0 on success, -errno otherwise.
1013 if (nor->spimem) { in spi_nor_write_sr2()
1016 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spi_nor_write_sr2()
1018 ret = spi_mem_exec_op(nor->spimem, &op); in spi_nor_write_sr2()
1025 dev_dbg(nor->dev, "error %d writing SR2\n", ret); in spi_nor_write_sr2()
1033 * spi_nor_read_sr2() - Read the Status Register 2 using the
1036 * @sr2: pointer to DMA-able buffer where the value of the
1039 * Return: 0 on success, -errno otherwise.
1045 if (nor->spimem) { in spi_nor_read_sr2()
1048 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spi_nor_read_sr2()
1050 ret = spi_mem_exec_op(nor->spimem, &op); in spi_nor_read_sr2()
1057 dev_dbg(nor->dev, "error %d reading SR2\n", ret); in spi_nor_read_sr2()
1063 * spi_nor_erase_die() - Erase the entire die.
1068 * Return: 0 on success, -errno otherwise.
1072 bool multi_die = nor->mtd.size != die_size; in spi_nor_erase_die()
1075 dev_dbg(nor->dev, " %lldKiB\n", (long long)(die_size >> 10)); in spi_nor_erase_die()
1077 if (nor->spimem) { in spi_nor_erase_die()
1079 SPI_NOR_DIE_ERASE_OP(nor->params->die_erase_opcode, in spi_nor_erase_die()
1080 nor->addr_nbytes, addr, multi_die); in spi_nor_erase_die()
1082 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spi_nor_erase_die()
1084 ret = spi_mem_exec_op(nor->spimem, &op); in spi_nor_erase_die()
1087 return -EOPNOTSUPP; in spi_nor_erase_die()
1095 dev_dbg(nor->dev, "error %d erasing chip\n", ret); in spi_nor_erase_die()
1161 return !!nor->params->erase_map.uniform_region.erase_mask; in spi_nor_has_uniform_erase()
1166 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); in spi_nor_set_4byte_opcodes()
1167 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode); in spi_nor_set_4byte_opcodes()
1168 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode); in spi_nor_set_4byte_opcodes()
1171 struct spi_nor_erase_map *map = &nor->params->erase_map; in spi_nor_set_4byte_opcodes()
1176 erase = &map->erase_type[i]; in spi_nor_set_4byte_opcodes()
1177 erase->opcode = in spi_nor_set_4byte_opcodes()
1178 spi_nor_convert_3to4_erase(erase->opcode); in spi_nor_set_4byte_opcodes()
1187 if (nor->controller_ops && nor->controller_ops->prepare) in spi_nor_prep()
1188 ret = nor->controller_ops->prepare(nor); in spi_nor_prep()
1195 if (nor->controller_ops && nor->controller_ops->unprepare) in spi_nor_unprep()
1196 nor->controller_ops->unprepare(nor); in spi_nor_unprep()
1204 *last = DIV_ROUND_DOWN_ULL(start + len - 1, bank_size); in spi_nor_offset_to_banks()
1210 struct spi_nor_rww *rww = &nor->rww; in spi_nor_rww_start_io()
1213 mutex_lock(&nor->lock); in spi_nor_rww_start_io()
1215 if (rww->ongoing_io) in spi_nor_rww_start_io()
1218 rww->ongoing_io = true; in spi_nor_rww_start_io()
1222 mutex_unlock(&nor->lock); in spi_nor_rww_start_io()
1228 mutex_lock(&nor->lock); in spi_nor_rww_end_io()
1229 nor->rww.ongoing_io = false; in spi_nor_rww_end_io()
1230 mutex_unlock(&nor->lock); in spi_nor_rww_end_io()
1238 return wait_event_killable(nor->rww.wait, spi_nor_rww_start_io(nor)); in spi_nor_lock_device()
1245 wake_up(&nor->rww.wait); in spi_nor_unlock_device()
1252 struct spi_nor_rww *rww = &nor->rww; in spi_nor_rww_start_exclusive()
1255 mutex_lock(&nor->lock); in spi_nor_rww_start_exclusive()
1257 if (rww->ongoing_io || rww->ongoing_rd || rww->ongoing_pe) in spi_nor_rww_start_exclusive()
1260 rww->ongoing_io = true; in spi_nor_rww_start_exclusive()
1261 rww->ongoing_rd = true; in spi_nor_rww_start_exclusive()
1262 rww->ongoing_pe = true; in spi_nor_rww_start_exclusive()
1266 mutex_unlock(&nor->lock); in spi_nor_rww_start_exclusive()
1272 struct spi_nor_rww *rww = &nor->rww; in spi_nor_rww_end_exclusive()
1274 mutex_lock(&nor->lock); in spi_nor_rww_end_exclusive()
1275 rww->ongoing_io = false; in spi_nor_rww_end_exclusive()
1276 rww->ongoing_rd = false; in spi_nor_rww_end_exclusive()
1277 rww->ongoing_pe = false; in spi_nor_rww_end_exclusive()
1278 mutex_unlock(&nor->lock); in spi_nor_rww_end_exclusive()
1290 mutex_lock(&nor->lock); in spi_nor_prep_and_lock()
1292 ret = wait_event_killable(nor->rww.wait, in spi_nor_prep_and_lock()
1301 mutex_unlock(&nor->lock); in spi_nor_unlock_and_unprep()
1304 wake_up(&nor->rww.wait); in spi_nor_unlock_and_unprep()
1313 struct spi_nor_rww *rww = &nor->rww; in spi_nor_rww_start_pe()
1319 mutex_lock(&nor->lock); in spi_nor_rww_start_pe()
1321 if (rww->ongoing_io || rww->ongoing_rd || rww->ongoing_pe) in spi_nor_rww_start_pe()
1324 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last); in spi_nor_rww_start_pe()
1326 if (rww->used_banks & BIT(bank)) in spi_nor_rww_start_pe()
1332 rww->used_banks |= used_banks; in spi_nor_rww_start_pe()
1333 rww->ongoing_pe = true; in spi_nor_rww_start_pe()
1337 mutex_unlock(&nor->lock); in spi_nor_rww_start_pe()
1343 struct spi_nor_rww *rww = &nor->rww; in spi_nor_rww_end_pe()
1347 mutex_lock(&nor->lock); in spi_nor_rww_end_pe()
1349 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last); in spi_nor_rww_end_pe()
1351 rww->used_banks &= ~BIT(bank); in spi_nor_rww_end_pe()
1353 rww->ongoing_pe = false; in spi_nor_rww_end_pe()
1355 mutex_unlock(&nor->lock); in spi_nor_rww_end_pe()
1367 mutex_lock(&nor->lock); in spi_nor_prep_and_lock_pe()
1369 ret = wait_event_killable(nor->rww.wait, in spi_nor_prep_and_lock_pe()
1378 mutex_unlock(&nor->lock); in spi_nor_unlock_and_unprep_pe()
1381 wake_up(&nor->rww.wait); in spi_nor_unlock_and_unprep_pe()
1390 struct spi_nor_rww *rww = &nor->rww; in spi_nor_rww_start_rd()
1396 mutex_lock(&nor->lock); in spi_nor_rww_start_rd()
1398 if (rww->ongoing_io || rww->ongoing_rd) in spi_nor_rww_start_rd()
1401 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last); in spi_nor_rww_start_rd()
1403 if (rww->used_banks & BIT(bank)) in spi_nor_rww_start_rd()
1409 rww->used_banks |= used_banks; in spi_nor_rww_start_rd()
1410 rww->ongoing_io = true; in spi_nor_rww_start_rd()
1411 rww->ongoing_rd = true; in spi_nor_rww_start_rd()
1415 mutex_unlock(&nor->lock); in spi_nor_rww_start_rd()
1421 struct spi_nor_rww *rww = &nor->rww; in spi_nor_rww_end_rd()
1425 mutex_lock(&nor->lock); in spi_nor_rww_end_rd()
1427 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last); in spi_nor_rww_end_rd()
1429 nor->rww.used_banks &= ~BIT(bank); in spi_nor_rww_end_rd()
1431 rww->ongoing_io = false; in spi_nor_rww_end_rd()
1432 rww->ongoing_rd = false; in spi_nor_rww_end_rd()
1434 mutex_unlock(&nor->lock); in spi_nor_rww_end_rd()
1446 mutex_lock(&nor->lock); in spi_nor_prep_and_lock_rd()
1448 ret = wait_event_killable(nor->rww.wait, in spi_nor_prep_and_lock_rd()
1457 mutex_unlock(&nor->lock); in spi_nor_unlock_and_unprep_rd()
1460 wake_up(&nor->rww.wait); in spi_nor_unlock_and_unprep_rd()
1473 if (nor->spimem) { in spi_nor_erase_sector()
1475 SPI_NOR_SECTOR_ERASE_OP(nor->erase_opcode, in spi_nor_erase_sector()
1476 nor->addr_nbytes, addr); in spi_nor_erase_sector()
1478 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spi_nor_erase_sector()
1480 return spi_mem_exec_op(nor->spimem, &op); in spi_nor_erase_sector()
1481 } else if (nor->controller_ops->erase) { in spi_nor_erase_sector()
1489 for (i = nor->addr_nbytes - 1; i >= 0; i--) { in spi_nor_erase_sector()
1490 nor->bouncebuf[i] = addr & 0xff; in spi_nor_erase_sector()
1494 return spi_nor_controller_ops_write_reg(nor, nor->erase_opcode, in spi_nor_erase_sector()
1495 nor->bouncebuf, nor->addr_nbytes); in spi_nor_erase_sector()
1499 * spi_nor_div_by_erase_size() - calculate remainder and update new dividend
1510 *remainder = (u32)dividend & erase->size_mask; in spi_nor_div_by_erase_size()
1511 return dividend >> erase->size_shift; in spi_nor_div_by_erase_size()
1515 * spi_nor_find_best_erase_type() - find the best erase type for the given
1540 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { in spi_nor_find_best_erase_type()
1542 if (!(region->erase_mask & BIT(i))) in spi_nor_find_best_erase_type()
1545 erase = &map->erase_type[i]; in spi_nor_find_best_erase_type()
1546 if (!erase->size) in spi_nor_find_best_erase_type()
1550 if (region->overlaid && region->size <= len) in spi_nor_find_best_erase_type()
1554 if (erase->size > len) in spi_nor_find_best_erase_type()
1566 * spi_nor_init_erase_cmd() - initialize an erase command
1570 * Return: the pointer to the allocated erase command, ERR_PTR(-errno)
1581 return ERR_PTR(-ENOMEM); in spi_nor_init_erase_cmd()
1583 INIT_LIST_HEAD(&cmd->list); in spi_nor_init_erase_cmd()
1584 cmd->opcode = erase->opcode; in spi_nor_init_erase_cmd()
1585 cmd->count = 1; in spi_nor_init_erase_cmd()
1587 if (region->overlaid) in spi_nor_init_erase_cmd()
1588 cmd->size = region->size; in spi_nor_init_erase_cmd()
1590 cmd->size = erase->size; in spi_nor_init_erase_cmd()
1596 * spi_nor_destroy_erase_cmd_list() - destroy erase command list
1604 list_del(&cmd->list); in spi_nor_destroy_erase_cmd_list()
1610 * spi_nor_init_erase_cmd_list() - initialize erase command list
1620 * Return: 0 on success, -errno otherwise.
1626 const struct spi_nor_erase_map *map = &nor->params->erase_map; in spi_nor_init_erase_cmd_list()
1632 int ret = -EINVAL; in spi_nor_init_erase_cmd_list()
1634 for (i = 0; i < map->n_regions && len; i++) { in spi_nor_init_erase_cmd_list()
1635 region = &map->regions[i]; in spi_nor_init_erase_cmd_list()
1636 region_end = region->offset + region->size; in spi_nor_init_erase_cmd_list()
1638 while (len && addr >= region->offset && addr < region_end) { in spi_nor_init_erase_cmd_list()
1644 if (prev_erase != erase || erase->size != cmd->size || in spi_nor_init_erase_cmd_list()
1645 region->overlaid) { in spi_nor_init_erase_cmd_list()
1652 list_add_tail(&cmd->list, erase_list); in spi_nor_init_erase_cmd_list()
1654 cmd->count++; in spi_nor_init_erase_cmd_list()
1657 len -= cmd->size; in spi_nor_init_erase_cmd_list()
1658 addr += cmd->size; in spi_nor_init_erase_cmd_list()
1671 * spi_nor_erase_multi_sectors() - perform a non-uniform erase
1679 * Return: 0 on success, -errno otherwise.
1692 nor->erase_opcode = cmd->opcode; in spi_nor_erase_multi_sectors()
1693 while (cmd->count) { in spi_nor_erase_multi_sectors()
1694 …dev_vdbg(nor->dev, "erase_cmd->size = 0x%08x, erase_cmd->opcode = 0x%02x, erase_cmd->count = %u\n", in spi_nor_erase_multi_sectors()
1695 cmd->size, cmd->opcode, cmd->count); in spi_nor_erase_multi_sectors()
1716 addr += cmd->size; in spi_nor_erase_multi_sectors()
1717 cmd->count--; in spi_nor_erase_multi_sectors()
1719 list_del(&cmd->list); in spi_nor_erase_multi_sectors()
1744 (unsigned long)(nor->mtd.size / SZ_2M)); in spi_nor_erase_dice()
1768 len -= die_size; in spi_nor_erase_dice()
1782 u8 n_dice = nor->params->n_dice; in spi_nor_erase()
1788 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, in spi_nor_erase()
1789 (long long)instr->len); in spi_nor_erase()
1792 div_u64_rem(instr->len, mtd->erasesize, &rem); in spi_nor_erase()
1794 return -EINVAL; in spi_nor_erase()
1797 addr = instr->addr; in spi_nor_erase()
1798 len = instr->len; in spi_nor_erase()
1801 die_size = div_u64(mtd->size, n_dice); in spi_nor_erase()
1802 if (!(len & (die_size - 1)) && !(addr & (die_size - 1))) in spi_nor_erase()
1805 die_size = mtd->size; in spi_nor_erase()
1808 ret = spi_nor_prep_and_lock_pe(nor, instr->addr, instr->len); in spi_nor_erase()
1813 if ((len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) || in spi_nor_erase()
1824 /* "sector"-at-a-time erase */ in spi_nor_erase()
1846 addr += mtd->erasesize; in spi_nor_erase()
1847 len -= mtd->erasesize; in spi_nor_erase()
1860 spi_nor_unlock_and_unprep_pe(nor, instr->addr, instr->len); in spi_nor_erase()
1866 * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
1872 * Return: 0 on success, -errno otherwise.
1878 ret = spi_nor_read_sr(nor, nor->bouncebuf); in spi_nor_sr1_bit6_quad_enable()
1882 if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) in spi_nor_sr1_bit6_quad_enable()
1885 nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; in spi_nor_sr1_bit6_quad_enable()
1887 return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); in spi_nor_sr1_bit6_quad_enable()
1891 * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
1897 * Return: 0 on success, -errno otherwise.
1903 if (nor->flags & SNOR_F_NO_READ_CR) in spi_nor_sr2_bit1_quad_enable()
1906 ret = spi_nor_read_cr(nor, nor->bouncebuf); in spi_nor_sr2_bit1_quad_enable()
1910 if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1) in spi_nor_sr2_bit1_quad_enable()
1913 nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1; in spi_nor_sr2_bit1_quad_enable()
1915 return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]); in spi_nor_sr2_bit1_quad_enable()
1919 * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
1922 * Set the Quad Enable (QE) bit in the Status Register 2.
1928 * Return: 0 on success, -errno otherwise.
1932 u8 *sr2 = nor->bouncebuf; in spi_nor_sr2_bit7_quad_enable()
1936 /* Check current Quad Enable bit value. */ in spi_nor_sr2_bit7_quad_enable()
1943 /* Update the Quad Enable bit. */ in spi_nor_sr2_bit7_quad_enable()
1958 dev_dbg(nor->dev, "SR2: Read back test failed\n"); in spi_nor_sr2_bit7_quad_enable()
1959 return -EIO; in spi_nor_sr2_bit7_quad_enable()
1983 .name = "spi-nor-generic",
1993 for (j = 0; j < manufacturers[i]->nparts; j++) { in spi_nor_match_id()
1994 part = &manufacturers[i]->parts[j]; in spi_nor_match_id()
1995 if (part->id && in spi_nor_match_id()
1996 !memcmp(part->id->bytes, id, part->id->len)) { in spi_nor_match_id()
1997 nor->manufacturer = manufacturers[i]; in spi_nor_match_id()
2009 u8 *id = nor->bouncebuf; in spi_nor_detect()
2012 ret = spi_nor_read_id(nor, 0, 0, id, nor->reg_proto); in spi_nor_detect()
2014 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret); in spi_nor_detect()
2019 nor->id = devm_kmemdup(nor->dev, id, SPI_NOR_MAX_ID_LEN, GFP_KERNEL); in spi_nor_detect()
2020 if (!nor->id) in spi_nor_detect()
2021 return ERR_PTR(-ENOMEM); in spi_nor_detect()
2033 dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n", in spi_nor_detect()
2035 return ERR_PTR(-ENODEV); in spi_nor_detect()
2048 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); in spi_nor_read()
2059 /* We shouldn't see 0-length reads */ in spi_nor_read()
2060 ret = -EIO; in spi_nor_read()
2070 len -= ret; in spi_nor_read()
2091 u32 page_size = nor->params->page_size; in spi_nor_write()
2093 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); in spi_nor_write()
2102 size_t page_offset = addr & (page_size - 1); in spi_nor_write()
2104 size_t page_remain = min_t(size_t, page_size - page_offset, len - i); in spi_nor_write()
2137 if (!nor->dev || in spi_nor_check()
2138 (!nor->spimem && !nor->controller_ops) || in spi_nor_check()
2139 (!nor->spimem && nor->controller_ops && in spi_nor_check()
2140 (!nor->controller_ops->read || in spi_nor_check()
2141 !nor->controller_ops->write || in spi_nor_check()
2142 !nor->controller_ops->read_reg || in spi_nor_check()
2143 !nor->controller_ops->write_reg))) { in spi_nor_check()
2144 pr_err("spi-nor: please fill all the necessary fields!\n"); in spi_nor_check()
2145 return -EINVAL; in spi_nor_check()
2148 if (nor->spimem && nor->controller_ops) { in spi_nor_check()
2149 …dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one… in spi_nor_check()
2150 return -EINVAL; in spi_nor_check()
2163 read->num_mode_clocks = num_mode_clocks; in spi_nor_set_read_settings()
2164 read->num_wait_states = num_wait_states; in spi_nor_set_read_settings()
2165 read->opcode = opcode; in spi_nor_set_read_settings()
2166 read->proto = proto; in spi_nor_set_read_settings()
2172 pp->opcode = opcode; in spi_nor_set_pp_settings()
2173 pp->proto = proto; in spi_nor_set_pp_settings()
2184 return -EINVAL; in spi_nor_hwcaps2cmd()
2230 * spi_nor_spimem_check_op - check if the operation is supported
2235 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
2246 op->addr.nbytes = 4; in spi_nor_spimem_check_op()
2247 if (!spi_mem_supports_op(nor->spimem, op)) { in spi_nor_spimem_check_op()
2248 if (nor->params->size > SZ_16M) in spi_nor_spimem_check_op()
2249 return -EOPNOTSUPP; in spi_nor_spimem_check_op()
2252 op->addr.nbytes = 3; in spi_nor_spimem_check_op()
2253 if (!spi_mem_supports_op(nor->spimem, op)) in spi_nor_spimem_check_op()
2254 return -EOPNOTSUPP; in spi_nor_spimem_check_op()
2261 * spi_nor_spimem_check_readop - check if the read op is supported
2266 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
2271 struct spi_mem_op op = SPI_NOR_READ_OP(read->opcode); in spi_nor_spimem_check_readop()
2273 spi_nor_spimem_setup_op(nor, &op, read->proto); in spi_nor_spimem_check_readop()
2276 op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) * in spi_nor_spimem_check_readop()
2278 if (spi_nor_protocol_is_dtr(nor->read_proto)) in spi_nor_spimem_check_readop()
2285 * spi_nor_spimem_check_pp - check if the page program op is supported
2290 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
2295 struct spi_mem_op op = SPI_NOR_PP_OP(pp->opcode); in spi_nor_spimem_check_pp()
2297 spi_nor_spimem_setup_op(nor, &op, pp->proto); in spi_nor_spimem_check_pp()
2303 * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol
2312 struct spi_nor_flash_parameter *params = nor->params; in spi_nor_spimem_adjust_hwcaps()
2315 /* X-X-X modes are not supported yet, mask them all. */ in spi_nor_spimem_adjust_hwcaps()
2322 if (nor->flags & SNOR_F_BROKEN_RESET) in spi_nor_spimem_adjust_hwcaps()
2333 spi_nor_spimem_check_readop(nor, ¶ms->reads[rdidx])) in spi_nor_spimem_adjust_hwcaps()
2341 ¶ms->page_programs[ppidx])) in spi_nor_spimem_adjust_hwcaps()
2347 * spi_nor_set_erase_type() - set a SPI NOR erase type
2355 erase->size = size; in spi_nor_set_erase_type()
2356 erase->opcode = opcode; in spi_nor_set_erase_type()
2358 erase->size_shift = ffs(erase->size) - 1; in spi_nor_set_erase_type()
2359 erase->size_mask = (1 << erase->size_shift) - 1; in spi_nor_set_erase_type()
2363 * spi_nor_mask_erase_type() - mask out a SPI NOR erase type
2368 erase->size = 0; in spi_nor_mask_erase_type()
2372 * spi_nor_init_uniform_erase_map() - Initialize uniform erase map
2381 map->uniform_region.offset = 0; in spi_nor_init_uniform_erase_map()
2382 map->uniform_region.size = flash_size; in spi_nor_init_uniform_erase_map()
2383 map->uniform_region.erase_mask = erase_mask; in spi_nor_init_uniform_erase_map()
2384 map->regions = &map->uniform_region; in spi_nor_init_uniform_erase_map()
2385 map->n_regions = 1; in spi_nor_init_uniform_erase_map()
2394 if (nor->manufacturer && nor->manufacturer->fixups && in spi_nor_post_bfpt_fixups()
2395 nor->manufacturer->fixups->post_bfpt) { in spi_nor_post_bfpt_fixups()
2396 ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header, in spi_nor_post_bfpt_fixups()
2402 if (nor->info->fixups && nor->info->fixups->post_bfpt) in spi_nor_post_bfpt_fixups()
2403 return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt); in spi_nor_post_bfpt_fixups()
2411 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1; in spi_nor_select_read()
2415 return -EINVAL; in spi_nor_select_read()
2419 return -EINVAL; in spi_nor_select_read()
2421 read = &nor->params->reads[cmd]; in spi_nor_select_read()
2422 nor->read_opcode = read->opcode; in spi_nor_select_read()
2423 nor->read_proto = read->proto; in spi_nor_select_read()
2429 * flash memory to know whether it should enter or leave its 0-4-4 in spi_nor_select_read()
2431 * eXecution In Place is out of the scope of the mtd sub-system. in spi_nor_select_read()
2435 nor->read_dummy = read->num_mode_clocks + read->num_wait_states; in spi_nor_select_read()
2442 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1; in spi_nor_select_pp()
2446 return -EINVAL; in spi_nor_select_pp()
2450 return -EINVAL; in spi_nor_select_pp()
2452 pp = &nor->params->page_programs[cmd]; in spi_nor_select_pp()
2453 nor->program_opcode = pp->opcode; in spi_nor_select_pp()
2454 nor->write_proto = pp->proto; in spi_nor_select_pp()
2459 * spi_nor_select_uniform_erase() - select optimum uniform erase type
2472 u8 uniform_erase_type = map->uniform_region.erase_mask; in spi_nor_select_uniform_erase()
2478 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { in spi_nor_select_uniform_erase()
2482 tested_erase = &map->erase_type[i]; in spi_nor_select_uniform_erase()
2485 if (!tested_erase->size) in spi_nor_select_uniform_erase()
2493 tested_erase->size == SZ_4K) { in spi_nor_select_uniform_erase()
2502 if (!erase && tested_erase->size) in spi_nor_select_uniform_erase()
2511 map->uniform_region.erase_mask = BIT(erase - map->erase_type); in spi_nor_select_uniform_erase()
2517 struct spi_nor_erase_map *map = &nor->params->erase_map; in spi_nor_select_erase()
2519 struct mtd_info *mtd = &nor->mtd; in spi_nor_select_erase()
2533 return -EINVAL; in spi_nor_select_erase()
2534 nor->erase_opcode = erase->opcode; in spi_nor_select_erase()
2535 mtd->erasesize = erase->size; in spi_nor_select_erase()
2540 * For non-uniform SPI flash memory, set mtd->erasesize to the in spi_nor_select_erase()
2541 * maximum erase sector size. No need to set nor->erase_opcode. in spi_nor_select_erase()
2543 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { in spi_nor_select_erase()
2544 if (map->erase_type[i].size) { in spi_nor_select_erase()
2545 erase = &map->erase_type[i]; in spi_nor_select_erase()
2551 return -EINVAL; in spi_nor_select_erase()
2553 mtd->erasesize = erase->size; in spi_nor_select_erase()
2559 if (nor->params->addr_nbytes) { in spi_nor_set_addr_nbytes()
2560 nor->addr_nbytes = nor->params->addr_nbytes; in spi_nor_set_addr_nbytes()
2561 } else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) { in spi_nor_set_addr_nbytes()
2563 * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So in spi_nor_set_addr_nbytes()
2565 * then the address phase would only span a cycle and a half. in spi_nor_set_addr_nbytes()
2567 * the dummy phase in the middle of a cycle and so too the data in spi_nor_set_addr_nbytes()
2568 * phase, and we will end the transaction with half a cycle left in spi_nor_set_addr_nbytes()
2571 * Force all 8D-8D-8D flashes to use an addr_nbytes of 4 to in spi_nor_set_addr_nbytes()
2574 nor->addr_nbytes = 4; in spi_nor_set_addr_nbytes()
2575 } else if (nor->info->addr_nbytes) { in spi_nor_set_addr_nbytes()
2576 nor->addr_nbytes = nor->info->addr_nbytes; in spi_nor_set_addr_nbytes()
2578 nor->addr_nbytes = 3; in spi_nor_set_addr_nbytes()
2581 if (nor->addr_nbytes == 3 && nor->params->size > 0x1000000) { in spi_nor_set_addr_nbytes()
2582 /* enable 4-byte addressing if the device exceeds 16MiB */ in spi_nor_set_addr_nbytes()
2583 nor->addr_nbytes = 4; in spi_nor_set_addr_nbytes()
2586 if (nor->addr_nbytes > SPI_NOR_MAX_ADDR_NBYTES) { in spi_nor_set_addr_nbytes()
2587 dev_dbg(nor->dev, "The number of address bytes is too large: %u\n", in spi_nor_set_addr_nbytes()
2588 nor->addr_nbytes); in spi_nor_set_addr_nbytes()
2589 return -EINVAL; in spi_nor_set_addr_nbytes()
2593 if (nor->addr_nbytes == 4 && nor->flags & SNOR_F_4B_OPCODES && in spi_nor_set_addr_nbytes()
2594 !(nor->flags & SNOR_F_HAS_4BAIT)) in spi_nor_set_addr_nbytes()
2603 struct spi_nor_flash_parameter *params = nor->params; in spi_nor_setup()
2611 shared_mask = hwcaps->mask & params->hwcaps.mask; in spi_nor_setup()
2613 if (nor->spimem) { in spi_nor_setup()
2622 * SPI n-n-n protocols are not supported when the SPI in spi_nor_setup()
2624 * Yet another reason to switch to spi-mem. in spi_nor_setup()
2628 dev_dbg(nor->dev, in spi_nor_setup()
2629 "SPI n-n-n protocols are not supported.\n"); in spi_nor_setup()
2637 dev_dbg(nor->dev, in spi_nor_setup()
2645 dev_dbg(nor->dev, in spi_nor_setup()
2653 dev_dbg(nor->dev, in spi_nor_setup()
2662 * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and
2663 * settings based on MFR register and ->default_init() hook.
2668 if (nor->manufacturer && nor->manufacturer->fixups && in spi_nor_manufacturer_init_params()
2669 nor->manufacturer->fixups->default_init) in spi_nor_manufacturer_init_params()
2670 nor->manufacturer->fixups->default_init(nor); in spi_nor_manufacturer_init_params()
2672 if (nor->info->fixups && nor->info->fixups->default_init) in spi_nor_manufacturer_init_params()
2673 nor->info->fixups->default_init(nor); in spi_nor_manufacturer_init_params()
2677 * spi_nor_no_sfdp_init_params() - Initialize the flash's parameters and
2678 * settings based on nor->info->sfdp_flags. This method should be called only by
2687 struct spi_nor_flash_parameter *params = nor->params; in spi_nor_no_sfdp_init_params()
2688 struct spi_nor_erase_map *map = ¶ms->erase_map; in spi_nor_no_sfdp_init_params()
2689 const struct flash_info *info = nor->info; in spi_nor_no_sfdp_init_params()
2690 const u8 no_sfdp_flags = info->no_sfdp_flags; in spi_nor_no_sfdp_init_params()
2694 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; in spi_nor_no_sfdp_init_params()
2695 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], in spi_nor_no_sfdp_init_params()
2701 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; in spi_nor_no_sfdp_init_params()
2702 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], in spi_nor_no_sfdp_init_params()
2708 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8; in spi_nor_no_sfdp_init_params()
2709 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8], in spi_nor_no_sfdp_init_params()
2715 params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; in spi_nor_no_sfdp_init_params()
2716 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR], in spi_nor_no_sfdp_init_params()
2722 params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR; in spi_nor_no_sfdp_init_params()
2727 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR], in spi_nor_no_sfdp_init_params()
2739 spi_nor_set_erase_type(&map->erase_type[i], 4096u, in spi_nor_no_sfdp_init_params()
2744 spi_nor_set_erase_type(&map->erase_type[i], in spi_nor_no_sfdp_init_params()
2745 info->sector_size ?: SPI_NOR_DEFAULT_SECTOR_SIZE, in spi_nor_no_sfdp_init_params()
2747 spi_nor_init_uniform_erase_map(map, erase_mask, params->size); in spi_nor_no_sfdp_init_params()
2751 * spi_nor_init_flags() - Initialize NOR flags for settings that are not defined
2758 const u16 flags = nor->info->flags; in spi_nor_init_flags()
2760 if (of_property_read_bool(np, "broken-flash-reset")) in spi_nor_init_flags()
2761 nor->flags |= SNOR_F_BROKEN_RESET; in spi_nor_init_flags()
2763 if (of_property_read_bool(np, "no-wp")) in spi_nor_init_flags()
2764 nor->flags |= SNOR_F_NO_WP; in spi_nor_init_flags()
2767 nor->flags |= SNOR_F_SWP_IS_VOLATILE; in spi_nor_init_flags()
2770 nor->flags |= SNOR_F_HAS_LOCK; in spi_nor_init_flags()
2773 nor->flags |= SNOR_F_HAS_SR_TB; in spi_nor_init_flags()
2775 nor->flags |= SNOR_F_HAS_SR_TB_BIT6; in spi_nor_init_flags()
2779 nor->flags |= SNOR_F_HAS_4BIT_BP; in spi_nor_init_flags()
2781 nor->flags |= SNOR_F_HAS_SR_BP3_BIT6; in spi_nor_init_flags()
2784 if (flags & SPI_NOR_RWW && nor->params->n_banks > 1 && in spi_nor_init_flags()
2785 !nor->controller_ops) in spi_nor_init_flags()
2786 nor->flags |= SNOR_F_RWW; in spi_nor_init_flags()
2790 * spi_nor_init_fixup_flags() - Initialize NOR flags for settings that can not
2799 const u8 fixup_flags = nor->info->fixup_flags; in spi_nor_init_fixup_flags()
2802 nor->flags |= SNOR_F_4B_OPCODES; in spi_nor_init_fixup_flags()
2805 nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; in spi_nor_init_fixup_flags()
2809 * spi_nor_late_init_params() - Late initialization of default flash parameters.
2818 struct spi_nor_flash_parameter *params = nor->params; in spi_nor_late_init_params()
2821 if (nor->manufacturer && nor->manufacturer->fixups && in spi_nor_late_init_params()
2822 nor->manufacturer->fixups->late_init) { in spi_nor_late_init_params()
2823 ret = nor->manufacturer->fixups->late_init(nor); in spi_nor_late_init_params()
2831 if (nor->info->fixups && nor->info->fixups->late_init) { in spi_nor_late_init_params()
2832 ret = nor->info->fixups->late_init(nor); in spi_nor_late_init_params()
2837 if (!nor->params->die_erase_opcode) in spi_nor_late_init_params()
2838 nor->params->die_erase_opcode = SPINOR_OP_CHIP_ERASE; in spi_nor_late_init_params()
2841 if (!params->set_4byte_addr_mode) in spi_nor_late_init_params()
2842 params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_brwr; in spi_nor_late_init_params()
2850 if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops) in spi_nor_late_init_params()
2853 if (params->n_banks > 1) in spi_nor_late_init_params()
2854 params->bank_size = div_u64(params->size, params->n_banks); in spi_nor_late_init_params()
2860 * spi_nor_sfdp_init_params_deprecated() - Deprecated way of initializing flash
2864 * The method has a roll-back mechanism: in case the SFDP parsing fails, the
2871 memcpy(&sfdp_params, nor->params, sizeof(sfdp_params)); in spi_nor_sfdp_init_params_deprecated()
2874 memcpy(nor->params, &sfdp_params, sizeof(*nor->params)); in spi_nor_sfdp_init_params_deprecated()
2875 nor->flags &= ~SNOR_F_4B_OPCODES; in spi_nor_sfdp_init_params_deprecated()
2880 * spi_nor_init_params_deprecated() - Deprecated way of initializing flash
2894 if (nor->info->no_sfdp_flags & (SPI_NOR_DUAL_READ | in spi_nor_init_params_deprecated()
2902 * spi_nor_init_default_params() - Default initialization of flash parameters
2909 struct spi_nor_flash_parameter *params = nor->params; in spi_nor_init_default_params()
2910 const struct flash_info *info = nor->info; in spi_nor_init_default_params()
2913 params->quad_enable = spi_nor_sr2_bit1_quad_enable; in spi_nor_init_default_params()
2914 params->otp.org = info->otp; in spi_nor_init_default_params()
2916 /* Default to 16-bit Write Status (01h) Command */ in spi_nor_init_default_params()
2917 nor->flags |= SNOR_F_HAS_16BIT_SR; in spi_nor_init_default_params()
2920 params->writesize = 1; in spi_nor_init_default_params()
2921 params->size = info->size; in spi_nor_init_default_params()
2922 params->bank_size = params->size; in spi_nor_init_default_params()
2923 params->page_size = info->page_size ?: SPI_NOR_DEFAULT_PAGE_SIZE; in spi_nor_init_default_params()
2924 params->n_banks = info->n_banks ?: SPI_NOR_DEFAULT_N_BANKS; in spi_nor_init_default_params()
2926 /* Default to Fast Read for non-DT and enable it if requested by DT. */ in spi_nor_init_default_params()
2927 if (!np || of_property_read_bool(np, "m25p,fast-read")) in spi_nor_init_default_params()
2928 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; in spi_nor_init_default_params()
2931 params->hwcaps.mask |= SNOR_HWCAPS_READ; in spi_nor_init_default_params()
2932 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], in spi_nor_init_default_params()
2936 if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST) in spi_nor_init_default_params()
2937 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], in spi_nor_init_default_params()
2941 params->hwcaps.mask |= SNOR_HWCAPS_PP; in spi_nor_init_default_params()
2942 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], in spi_nor_init_default_params()
2945 if (info->flags & SPI_NOR_QUAD_PP) { in spi_nor_init_default_params()
2946 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; in spi_nor_init_default_params()
2947 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], in spi_nor_init_default_params()
2953 * spi_nor_init_params() - Initialize the flash's parameters and settings.
2960 * based on nor->info data:
2966 * based on MFR, by using specific flash_info tweeks, ->default_init():
2974 * Please note that there is a ->post_bfpt() fixup hook that can overwrite
2987 * Return: 0 on success, -errno otherwise.
2993 nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL); in spi_nor_init_params()
2994 if (!nor->params) in spi_nor_init_params()
2995 return -ENOMEM; in spi_nor_init_params()
3002 …dev_err(nor->dev, "BFPT parsing failed. Please consider using SPI_NOR_SKIP_SFDP when declaring the… in spi_nor_init_params()
3005 } else if (nor->info->no_sfdp_flags & SPI_NOR_SKIP_SFDP) { in spi_nor_init_params()
3015 if (WARN_ON(!is_power_of_2(nor->params->page_size))) in spi_nor_init_params()
3016 return -EINVAL; in spi_nor_init_params()
3021 /** spi_nor_set_octal_dtr() - enable or disable Octal DTR I/O.
3025 * Return: 0 on success, -errno otherwise.
3031 if (!nor->params->set_octal_dtr) in spi_nor_set_octal_dtr()
3034 if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR && in spi_nor_set_octal_dtr()
3035 nor->write_proto == SNOR_PROTO_8_8_8_DTR)) in spi_nor_set_octal_dtr()
3038 if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE)) in spi_nor_set_octal_dtr()
3041 ret = nor->params->set_octal_dtr(nor, enable); in spi_nor_set_octal_dtr()
3046 nor->reg_proto = SNOR_PROTO_8_8_8_DTR; in spi_nor_set_octal_dtr()
3048 nor->reg_proto = SNOR_PROTO_1_1_1; in spi_nor_set_octal_dtr()
3054 * spi_nor_quad_enable() - enable Quad I/O if needed.
3057 * Return: 0 on success, -errno otherwise.
3061 if (!nor->params->quad_enable) in spi_nor_quad_enable()
3064 if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 || in spi_nor_quad_enable()
3065 spi_nor_get_protocol_width(nor->write_proto) == 4)) in spi_nor_quad_enable()
3068 return nor->params->quad_enable(nor); in spi_nor_quad_enable()
3072 * spi_nor_set_4byte_addr_mode() - Set address mode.
3076 * Return: 0 on success, -errno otherwise.
3080 struct spi_nor_flash_parameter *params = nor->params; in spi_nor_set_4byte_addr_mode()
3091 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, in spi_nor_set_4byte_addr_mode()
3095 ret = params->set_4byte_addr_mode(nor, enable); in spi_nor_set_4byte_addr_mode()
3096 if (ret && ret != -EOPNOTSUPP) in spi_nor_set_4byte_addr_mode()
3100 params->addr_nbytes = 4; in spi_nor_set_4byte_addr_mode()
3101 params->addr_mode_nbytes = 4; in spi_nor_set_4byte_addr_mode()
3103 params->addr_nbytes = 3; in spi_nor_set_4byte_addr_mode()
3104 params->addr_mode_nbytes = 3; in spi_nor_set_4byte_addr_mode()
3116 dev_dbg(nor->dev, "octal mode not supported\n"); in spi_nor_init()
3122 dev_dbg(nor->dev, "quad mode not supported\n"); in spi_nor_init()
3127 * Some SPI NOR flashes are write protected by default after a power-on in spi_nor_init()
3128 * reset cycle, in order to avoid inadvertent writes during power-up. in spi_nor_init()
3130 * array at power-up by default. Depending on the kernel configuration in spi_nor_init()
3138 nor->flags & SNOR_F_SWP_IS_VOLATILE)) in spi_nor_init()
3141 if (nor->addr_nbytes == 4 && in spi_nor_init()
3142 nor->read_proto != SNOR_PROTO_8_8_8_DTR && in spi_nor_init()
3143 !(nor->flags & SNOR_F_4B_OPCODES)) in spi_nor_init()
3150 * spi_nor_soft_reset() - Perform a software reset
3154 * the device to its power-on-reset state. This is useful when the software has
3162 * Return: 0 on success, -errno otherwise.
3171 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spi_nor_soft_reset()
3173 ret = spi_mem_exec_op(nor->spimem, &op); in spi_nor_soft_reset()
3175 if (ret != -EOPNOTSUPP) in spi_nor_soft_reset()
3176 dev_warn(nor->dev, "Software reset failed: %d\n", ret); in spi_nor_soft_reset()
3182 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spi_nor_soft_reset()
3184 ret = spi_mem_exec_op(nor->spimem, &op); in spi_nor_soft_reset()
3186 dev_warn(nor->dev, "Software reset failed: %d\n", ret); in spi_nor_soft_reset()
3193 * microseconds. So, sleep for a range of 200-400 us. in spi_nor_soft_reset()
3207 dev_err(nor->dev, "suspend() failed\n"); in spi_nor_suspend()
3216 struct device *dev = nor->dev; in spi_nor_resume()
3219 /* re-initialize the nor chip */ in spi_nor_resume()
3231 if (nor->spimem) in spi_nor_get_device()
3232 dev = nor->spimem->spi->controller->dev.parent; in spi_nor_get_device()
3234 dev = nor->dev; in spi_nor_get_device()
3236 if (!try_module_get(dev->driver->owner)) in spi_nor_get_device()
3237 return -ENODEV; in spi_nor_get_device()
3248 if (nor->spimem) in spi_nor_put_device()
3249 dev = nor->spimem->spi->controller->dev.parent; in spi_nor_put_device()
3251 dev = nor->dev; in spi_nor_put_device()
3253 module_put(dev->driver->owner); in spi_nor_put_device()
3261 if (nor->addr_nbytes == 4 && !(nor->flags & SNOR_F_4B_OPCODES) && in spi_nor_restore()
3262 nor->flags & SNOR_F_BROKEN_RESET) { in spi_nor_restore()
3267 * will default to the 3-byte address mode after the in spi_nor_restore()
3270 dev_err(nor->dev, "Failed to exit 4-byte address mode, err = %d\n", ret); in spi_nor_restore()
3273 if (nor->flags & SNOR_F_SOFT_RESET) in spi_nor_restore()
3283 for (j = 0; j < manufacturers[i]->nparts; j++) { in spi_nor_match_name()
3284 if (manufacturers[i]->parts[j].name && in spi_nor_match_name()
3285 !strcmp(name, manufacturers[i]->parts[j].name)) { in spi_nor_match_name()
3286 nor->manufacturer = manufacturers[i]; in spi_nor_match_name()
3287 return &manufacturers[i]->parts[j]; in spi_nor_match_name()
3303 * Auto-detect if chip name wasn't specified or not found, or the chip in spi_nor_get_flash_info()
3305 * auto-detection to compare it later. in spi_nor_get_flash_info()
3307 if (!info || info->id) { in spi_nor_get_flash_info()
3319 dev_warn(nor->dev, "found %s, expected %s\n", in spi_nor_get_flash_info()
3320 jinfo->name, info->name); in spi_nor_get_flash_info()
3335 if (region->overlaid) in spi_nor_get_region_erasesize()
3336 return region->size; in spi_nor_get_region_erasesize()
3338 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { in spi_nor_get_region_erasesize()
3339 if (region->erase_mask & BIT(i)) in spi_nor_get_region_erasesize()
3348 const struct spi_nor_erase_map *map = &nor->params->erase_map; in spi_nor_set_mtd_eraseregions()
3349 const struct spi_nor_erase_region *region = map->regions; in spi_nor_set_mtd_eraseregions()
3351 struct mtd_info *mtd = &nor->mtd; in spi_nor_set_mtd_eraseregions()
3354 mtd_region = devm_kcalloc(nor->dev, map->n_regions, sizeof(*mtd_region), in spi_nor_set_mtd_eraseregions()
3357 return -ENOMEM; in spi_nor_set_mtd_eraseregions()
3359 for (i = 0; i < map->n_regions; i++) { in spi_nor_set_mtd_eraseregions()
3361 map->erase_type); in spi_nor_set_mtd_eraseregions()
3363 return -EINVAL; in spi_nor_set_mtd_eraseregions()
3370 mtd->numeraseregions = map->n_regions; in spi_nor_set_mtd_eraseregions()
3371 mtd->eraseregions = mtd_region; in spi_nor_set_mtd_eraseregions()
3378 struct mtd_info *mtd = &nor->mtd; in spi_nor_set_mtd_info()
3379 struct device *dev = nor->dev; in spi_nor_set_mtd_info()
3384 mtd->dev.parent = dev; in spi_nor_set_mtd_info()
3385 if (!mtd->name) in spi_nor_set_mtd_info()
3386 mtd->name = dev_name(dev); in spi_nor_set_mtd_info()
3387 mtd->type = MTD_NORFLASH; in spi_nor_set_mtd_info()
3388 mtd->flags = MTD_CAP_NORFLASH; in spi_nor_set_mtd_info()
3390 if (nor->flags & SNOR_F_ECC) in spi_nor_set_mtd_info()
3391 mtd->flags &= ~MTD_BIT_WRITEABLE; in spi_nor_set_mtd_info()
3392 if (nor->info->flags & SPI_NOR_NO_ERASE) in spi_nor_set_mtd_info()
3393 mtd->flags |= MTD_NO_ERASE; in spi_nor_set_mtd_info()
3395 mtd->_erase = spi_nor_erase; in spi_nor_set_mtd_info()
3396 mtd->writesize = nor->params->writesize; in spi_nor_set_mtd_info()
3397 mtd->writebufsize = nor->params->page_size; in spi_nor_set_mtd_info()
3398 mtd->size = nor->params->size; in spi_nor_set_mtd_info()
3399 mtd->_read = spi_nor_read; in spi_nor_set_mtd_info()
3401 if (!mtd->_write) in spi_nor_set_mtd_info()
3402 mtd->_write = spi_nor_write; in spi_nor_set_mtd_info()
3403 mtd->_suspend = spi_nor_suspend; in spi_nor_set_mtd_info()
3404 mtd->_resume = spi_nor_resume; in spi_nor_set_mtd_info()
3405 mtd->_get_device = spi_nor_get_device; in spi_nor_set_mtd_info()
3406 mtd->_put_device = spi_nor_put_device; in spi_nor_set_mtd_info()
3418 reset = devm_gpiod_get_optional(nor->dev, "reset", GPIOD_OUT_LOW); in spi_nor_hw_reset()
3439 struct device *dev = nor->dev; in spi_nor_scan()
3447 nor->reg_proto = SNOR_PROTO_1_1_1; in spi_nor_scan()
3448 nor->read_proto = SNOR_PROTO_1_1_1; in spi_nor_scan()
3449 nor->write_proto = SNOR_PROTO_1_1_1; in spi_nor_scan()
3453 * through the spi-mem layer (buffers have to be DMA-able). in spi_nor_scan()
3454 * For spi-mem drivers, we'll reallocate a new buffer if in spi_nor_scan()
3455 * nor->params->page_size turns out to be greater than PAGE_SIZE (which in spi_nor_scan()
3459 nor->bouncebuf_size = PAGE_SIZE; in spi_nor_scan()
3460 nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size, in spi_nor_scan()
3462 if (!nor->bouncebuf) in spi_nor_scan()
3463 return -ENOMEM; in spi_nor_scan()
3473 nor->info = info; in spi_nor_scan()
3475 mutex_init(&nor->lock); in spi_nor_scan()
3483 init_waitqueue_head(&nor->rww.wait); in spi_nor_scan()
3487 * - select op codes for (Fast) Read, Page Program and Sector Erase. in spi_nor_scan()
3488 * - set the number of dummy cycles (mode cycles + wait states). in spi_nor_scan()
3489 * - set the SPI protocols for register and memory accesses. in spi_nor_scan()
3490 * - set the number of address bytes. in spi_nor_scan()
3507 SPI_NOR_MAX_ID_LEN, nor->id); in spi_nor_scan()
3516 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0), in spi_nor_create_read_dirmap()
3517 SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0), in spi_nor_create_read_dirmap()
3518 SPI_MEM_OP_DUMMY(nor->read_dummy, 0), in spi_nor_create_read_dirmap()
3521 .length = nor->params->size, in spi_nor_create_read_dirmap()
3525 spi_nor_spimem_setup_op(nor, op, nor->read_proto); in spi_nor_create_read_dirmap()
3528 op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8; in spi_nor_create_read_dirmap()
3529 if (spi_nor_protocol_is_dtr(nor->read_proto)) in spi_nor_create_read_dirmap()
3530 op->dummy.nbytes *= 2; in spi_nor_create_read_dirmap()
3534 * of data bytes is non-zero, the data buswidth won't be set here. So, in spi_nor_create_read_dirmap()
3537 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); in spi_nor_create_read_dirmap()
3539 nor->dirmap.rdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem, in spi_nor_create_read_dirmap()
3541 return PTR_ERR_OR_ZERO(nor->dirmap.rdesc); in spi_nor_create_read_dirmap()
3547 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0), in spi_nor_create_write_dirmap()
3548 SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0), in spi_nor_create_write_dirmap()
3552 .length = nor->params->size, in spi_nor_create_write_dirmap()
3556 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) in spi_nor_create_write_dirmap()
3557 op->addr.nbytes = 0; in spi_nor_create_write_dirmap()
3559 spi_nor_spimem_setup_op(nor, op, nor->write_proto); in spi_nor_create_write_dirmap()
3563 * of data bytes is non-zero, the data buswidth won't be set here. So, in spi_nor_create_write_dirmap()
3566 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); in spi_nor_create_write_dirmap()
3568 nor->dirmap.wdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem, in spi_nor_create_write_dirmap()
3570 return PTR_ERR_OR_ZERO(nor->dirmap.wdesc); in spi_nor_create_write_dirmap()
3575 struct spi_device *spi = spimem->spi; in spi_nor_probe()
3576 struct flash_platform_data *data = dev_get_platdata(&spi->dev); in spi_nor_probe()
3586 nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL); in spi_nor_probe()
3588 return -ENOMEM; in spi_nor_probe()
3590 nor->spimem = spimem; in spi_nor_probe()
3591 nor->dev = &spi->dev; in spi_nor_probe()
3592 spi_nor_set_flash_node(nor, spi->dev.of_node); in spi_nor_probe()
3596 if (data && data->name) in spi_nor_probe()
3597 nor->mtd.name = data->name; in spi_nor_probe()
3599 if (!nor->mtd.name) in spi_nor_probe()
3600 nor->mtd.name = spi_mem_get_name(spimem); in spi_nor_probe()
3608 if (data && data->type) in spi_nor_probe()
3609 flash_name = data->type; in spi_nor_probe()
3610 else if (!strcmp(spi->modalias, "spi-nor")) in spi_nor_probe()
3611 flash_name = NULL; /* auto-detect */ in spi_nor_probe()
3613 flash_name = spi->modalias; in spi_nor_probe()
3626 if (nor->params->page_size > PAGE_SIZE) { in spi_nor_probe()
3627 nor->bouncebuf_size = nor->params->page_size; in spi_nor_probe()
3628 devm_kfree(nor->dev, nor->bouncebuf); in spi_nor_probe()
3629 nor->bouncebuf = devm_kmalloc(nor->dev, in spi_nor_probe()
3630 nor->bouncebuf_size, in spi_nor_probe()
3632 if (!nor->bouncebuf) in spi_nor_probe()
3633 return -ENOMEM; in spi_nor_probe()
3644 return mtd_device_register(&nor->mtd, data ? data->parts : NULL, in spi_nor_probe()
3645 data ? data->nr_parts : 0); in spi_nor_probe()
3655 return mtd_device_unregister(&nor->mtd); in spi_nor_remove()
3670 * differences can often be differentiated by the JEDEC read-ID command, we
3671 * encourage new users to add support to the spi-nor library, and simply bind
3672 * against a generic string here (e.g., "jedec,spi-nor").
3679 * Allow non-DT platform devices to bind to the "spi-nor" modalias, and
3683 {"spi-nor"},
3687 * them with "spi-nor" in platform data.
3692 * Entries that were used in DTs without "jedec,spi-nor" fallback and
3708 {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"},
3709 {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"},
3710 {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"},
3712 /* Everspin MRAMs (non-JEDEC) */
3727 { .compatible = "jedec,spi-nor" },
3733 * REVISIT: many of these chips have deep power-down modes, which
3740 .name = "spi-nor",